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Hoyoung Yoo
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2020 – today
- 2024
- [j14]Muhammad Junaid
, Hayotjon Aliev, Sangbo Park, HyungWon Kim
Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training. Sensors 24(7): 2145 (2024) - [c18]Yongtaek Hwang, Jiwoo Hwang, Yuseok Lee, Hoyoung Yoo:
Efficient CRC-BCH Unified Encoder for Global Positioning System. ICEIC 2024: 1-3 - [c17]Jiho Park, Hee-Hun Yang, Donghun Lee, Hoyoung Yoo:
Physical Unclonable Function Using Programmable Delay Lines. ICEIC 2024: 1-4 - 2023
- [c16]Byeong Yong Kong
An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency. ICEIC 2023: 1-4 - [c15]Eunchae Lee, Soyeon Choi, Jiho Park, Sungkyun Shin, Hoyoung Yoo:
Practical Analysis of Xilinx FPGAs' Bitstream Encryption. ICEIC 2023: 1-3 - [c14]Sangwon Lee, Jiho Park, Jeongho Kim, Yongtaek Hwang, Soyeon Choi, Hoyoung Yoo:
Quantitative Analysis of Various 2D CNN Structures based on Dataflow. ICEIC 2023: 1-4 - 2022
- [j13]Nari Im
S-Box Attack Using FPGA Reverse Engineering for Lightweight Cryptography. IEEE Internet Things J. 9(24): 25165-25180 (2022) - [c13]Sungkyun Shin, Soyeon Choi, Eunchae Lee, Songyeon Lee, Hoyoung Yoo:
Implementation of Aurora Interface using SFP+ Transceiver. ISOCC 2022: 350-351 - 2021
- [j12]Dongyun Kam
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1083-1094 (2021) - [c12]Soyeon Choi, Yerin Shin, Hoyoung Yoo:
Analysis of Ring-Oscillator-based True Random Number Generator on FPGAs. ICEIC 2021: 1-3 - [c11]Sungryoung Lee, Hoyoung Yoo:
Configurable Digital Pulse Generator for Neuromorphic Devices. ICEIC 2021: 1-3 - [c10]Jiwoon Park, Gwang Hee Jo, Jinseok Kim, Hoyoung Yoo:
Area-Efficient On-the-Fly Code Generator for BDS B1C Receivers. ICEIC 2021: 1-4 - [c9]Soyeon Choi, Nari Im, Hoyoung Yoo:
FPGA Design Duplication based on the Bitstream Extraction. ISOCC 2021: 373-374 - 2020
- [c8]Soyeon Choi, Jieun Yeo, Hoyoung Yoo:
Extraction of ROM Data from Bitstream in Xilinx FPGA. ISOCC 2020: 97-98
2010 – 2019
- 2019
- [c7]Hyeonkyu Kim, Soyeon Choi, Hoyoung Yoo
On-demand Syndrome Calculation for BCH decoding. ICEIC 2019: 1-4 - 2018
- [j11]Eunmi Chu
Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis. Comput. Electr. Eng. 71: 321-330 (2018) - [c6]Soyeon Choi, Hoyoung Yoo
Hybrid Decoding for Polar Codes. ISOCC 2018: 121-122 - 2016
- [j10]Hoyoung Yoo
Efficient Pruning for Successive-Cancellation Decoding of Polar Codes. IEEE Commun. Lett. 20(12): 2362-2365 (2016) - [j9]Hoyoung Yoo
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach. IEEE Trans. Circuits Syst. II Express Briefs 63-II(3): 269-273 (2016) - [j8]Byeong Yong Kong
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 673-677 (2016) - [j7]Jihyuck Jo
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 754-758 (2016) - 2015
- [j6]Hoyoung Yoo
Partially Parallel Encoder Architecture for Long Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 306-310 (2015) - [j5]Jaehwan Jung, Hoyoung Yoo
Efficient Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1068-1072 (2015) - 2014
- [j4]Youngjoo Lee
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1183-1187 (2014) - [c5]Hoyoung Yoo
7.3 Gb/s universal BCH encoder and decoder for SSD controllers. ASP-DAC 2014: 37-38 - 2013
- [j3]Youngjoo Lee
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits 48(10): 2531-2540 (2013) - [j2]Hoyoung Yoo
Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 872-876 (2013) - [c4]Youngjoo Lee
A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process. ASP-DAC 2013: 85-86 - 2012
- [c3]Youngjoo Lee
Small-area parallel syndrome calculation for strong BCH decoding. ICASSP 2012: 1609-1612 - [c2]Hoyoung Yoo
Low-latency area-efficient decoding architecture for shortened reed-solomon codes. ISOCC 2012: 223-226 - [c1]Youngjoo Lee
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. ISSCC 2012: 426-428 - 2011
- [j1]Youngjoo Lee
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 522-526 (2011)
Coauthor Index
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