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Takayuki Kawahara
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2020 – today
- 2024
- [j29]Taichi Megumi
, Akari Endo
Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI. IEEE Access 12: 19711-19723 (2024) - [j28]Shinjiro Kitahara, Taichi Megumi, Akari Endo, Takayuki Kawahara
Implementation and Evaluation of Two Independent Ising Machines on Same FPGA Board by Reducing Number of Interactions Inside Ising Machine. IEEE Access 12: 145530-145539 (2024) - [j27]Yuya Fujiwara, Takayuki Kawahara
TGBNN: Training Algorithm of Binarized Neural Network With Ternary Gradients for MRAM-Based Computing-in-Memory Architecture. IEEE Access 12: 150962-150974 (2024) - 2023
- [c35]Yuya Fujiwara, Takayuki Kawahara:
BNN Training Algorithm with Ternary Gradients and BNN based on MRAM Array. TENCON 2023: 311-316 - [c34]Yuya Hayakawa, Yuga Aoki, Kenjiro Mori, Takumi Ito, Takayuki Kawahara:
Experimental Investigation of the Generalization Performance of Neural Network in Defect Localization System for Steel Pipe Health Monitoring. TENCON 2023: 942-947 - 2022
- [j26]Kaoru Yamamoto, Takayuki Kawahara
Scalable fully coupled annealing processing system and multi-chip FPGA implementation. Microprocess. Microsystems 95: 104674 (2022) - [c33]Akihiro Yamada, Yuwa Kishi, Takayuki Kawahara:
Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM. IMW 2022: 1-4 - 2021
- [j25]Ryoma Iimura
Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5061-5071 (2021) - [c32]Yudai Taguchi, Ryoma Iimura, Takayuki Kawahara:
FPGA Implementation of Support Vector Machine Using Ising Model for AI on Things. CIVEMSA 2021: 1-5 - 2020
- [j24]Ryoto Ono, Kenta Someya, Takayuki Kawahara
A novel Ising model processing achieving all interactions only by adjacent spins for a high-speed solver for versatile Ising machines. Microprocess. Microsystems 78: 103251 (2020) - [c31]Kohei Koike, Kenta Suzuki, Mengnan Ke, Kenjiro Mori, Takumi Ito, Takayuki Kawahara:
Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning. APCCAS 2020: 114-117 - [c30]Kenta Suzuki, Takumi Ito, Kohei Koike, Takayuki Kawahara, Mengnan Ke, Kenjiro Mori:
Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning. APCCAS 2020: 197-200 - [c29]Ryoma Iimura, Satoshi Kitamura, Takayuki Kawahara
Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips. MWSCAS 2020: 85-88
2010 – 2019
- 2019
- [c28]Ryota Tanida, Jing Ma, Takashi Nakajima, Mikio Hasegawa, Takahiro Yamamoto, Takumi Ito, Takayuki Kawahara
Machine Learning Classification Methods using Data of 3-axis Acceleration Sensors equipped with Wireless Communication Means for Locating Wooden House Structural Damage. APCCAS 2019: 337-340 - [c27]Tatsuya Hiejima, Shun Kawashima, Mengnan Ke, Takayuki Kawahara
Effectiveness of Synchronization and Cooperative Behavior of Multiple Robots based on Swarm AI. APCCAS 2019: 341-344 - [c26]Akira Minamisawa, Ryoma Iimura, Takayuki Kawahara
High-speed Sparse Ising Model on FPGA. MWSCAS 2019: 670-673 - 2018
- [c25]Ryota Tanida, Ryo Oiwa, Takumi Ito, Takayuki Kawahara
Wooden Framed House Structural Health Monitoring by System Identification and Damage Detection under Dynamic Motion with Artificial Intelligence Sensor using a Model of House including Braces. CIVEMSA 2018: 1-5 - [c24]Takumi Ito, Changhoon Choi, Takahiro Yamamoto, Takashi Nakajima, Takayuki Kawahara
Live Demonstration of IoT and AI System for Recognition of States of Buildings subjected to Seismic Vibration Motion. ISCAS 2018: 1- - 2017
- [j23]Zule Xu, Takayuki Kawahara
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. IEICE Trans. Electron. 100-C(4): 370-372 (2017) - [j22]Yasushi Fukuda, Zule Xu, Takayuki Kawahara
Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. IEICE Trans. Electron. 100-C(12): 1118-1121 (2017) - [c23]Ryo Oiwa, Takumi Ito, Takayuki Kawahara
Timber Health Monitoring using piezoelectric sensor and machine learning. CIVEMSA 2017: 123-128 - 2016
- [c22]Kenta Someya, Ryoto Ono, Takayuki Kawahara
Novel Ising model using dimension-control for high-speed solver for Ising machines. NEWCAS 2016: 1-4 - 2015
- [c21]Yuki Fukushima, Isamu Wakabayashi, Takayuki Kawahara
Equalization for the FDM System Using Mach-Zehnder Filters. AINA Workshops 2015: 727-732 - [c20]Isamu Wakabayashi, Yuki Fukushima, Takayuki Kawahara
An eight-channel FDM system using Mach-Zehnder filters with cosine roll-off band-limiting characteristics. APSITT 2015: 1-3 - [c19]H. Kazama, Takayuki Kawahara
STT-RAM read stability in DRAM operating region. NVMTS 2015: 1-4 - 2014
- [c18]Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara:
What is a good way to expand a silicon value to a solution value? A-SSCC 2014: 389-394 - 2013
- [c17]Yoshimitsu Yanagawa, Naoshi Itabashi, Sonoko Migitaka, Takahide Yokoi, Makiko Yoshida, Takayuki Kawahara
On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer. BioCAS 2013: 178-181 - 2012
- [j21]Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. IEICE Trans. Electron. 95-C(4): 651-660 (2012) - [j20]Takayuki Kawahara
Spin-transfer torque RAM technology: Review and prospect. Microelectron. Reliab. 52(4): 613-627 (2012) - [c16]Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. ISCAS 2012: 2299-2302 - 2011
- [j19]Takayuki Kawahara
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing. IEEE Des. Test Comput. 28(1): 52-63 (2011) - 2010
- [j18]Riichiro Takemura, Takayuki Kawahara
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits 45(4): 869-879 (2010)
2000 – 2009
- 2008
- [j17]Takayuki Kawahara
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE J. Solid State Circuits 43(1): 109-120 (2008) - [c15]Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC 2008: 286-289 - 2007
- [j16]Takayuki Kawahara
Low-Voltage Embedded RAMs in Nanometer Era. IEICE Trans. Electron. 90-C(4): 735-742 (2007) - [j15]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. IEICE Trans. Electron. 90-C(4): 758-764 (2007) - [c14]Masanao Yamaoka, Takayuki Kawahara
Operating-margin-improved SRAM with column-at-a-time body-bias control technique. ESSCIRC 2007: 396-399 - [c13]Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI 2007: 529-533 - [c12]Takayuki Kawahara
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. ICECS 2007: 1011-1014 - [c11]Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC 2007: 474-616 - [c10]Takayuki Kawahara
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. ISSCC 2007: 480-617 - 2006
- [j14]Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits 41(1): 107-112 (2006) - [j13]Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits 41(3): 705-711 (2006) - [j12]Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. IEEE J. Solid State Circuits 41(11): 2366-2372 (2006) - [c9]Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara:
Ultra-low voltage nano-scale embedded RAMs. ISCAS 2006 - 2005
- [j11]Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. IEEE J. Solid State Circuits 40(2): 523-531 (2005) - [j10]Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. IEEE J. Solid State Circuits 40(4): 853-861 (2005) - [c8]Kenichi Osada, Takayuki Kawahara
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC 2005: 431-434 - [c7]Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara:
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC 2005: 1048-1052 - [c6]Masayuki Miyazaki, Goichi Ono, Takayuki Kawahara
Optimum threshold-voltage tuning for low-power, high-performance microprocessor. ISCAS (1) 2005: 17-20 - [c5]Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara
An LSI system with locked in temperature insensitive state achieved by using body bias technique. ISCAS (1) 2005: 632-635 - 2004
- [j9]Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. IEEE J. Solid State Circuits 39(5): 827-833 (2004) - [c4]Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara:
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC 2004: 357-360 - [c3]Goichi Ono, Masayuki Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, Takayuki Kawahara:
Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]. ESSCIRC 2004: 391-394 - [c2]Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara
Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS 2004: 3-15 - 2003
- [j8]Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara
Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. 47(5-6): 525-552 (2003) - [c1]Masayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano:
Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment. ISLPED 2003: 193-198
1990 – 1999
- 1998
- [j7]Takayuki Kawahara
20-Mb/s erase/record flash memory by asymmetrical operation. IEEE J. Solid State Circuits 33(1): 119-125 (1998) - [j6]Takayuki Kawahara
Internal voltage generator for low voltage, quarter-micrometer flash memories. IEEE J. Solid State Circuits 33(1): 126-132 (1998) - 1996
- [j5]Takayuki Kawahara
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. IEEE J. Solid State Circuits 31(11): 1590-1600 (1996) - 1995
- [j4]Takayuki Kawahara
High reliability electron-ejection method for high density flash memories. IEEE J. Solid State Circuits 30(12): 1554-1562 (1995)
1980 – 1989
- 1989
- [j3]Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara
A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. IEEE J. Solid State Circuits 24(3): 597-602 (1989) - [j2]Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara
Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. IEEE J. Solid State Circuits 24(3): 771-778 (1989) - [j1]Takayuki Kawahara
Substrate current reduction techniques for BiCMOS DRAM. IEEE J. Solid State Circuits 24(5): 1381-1389 (1989)
Coauthor Index
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