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Hideaki Kurata
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2000 – 2009
- 2008
- [j8]Shinya Kajiyama, Ken'ichiro Sonoda, Kazuo Otsuga, Hideaki Kurata, Kiyoshi Ishikawa:
A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model. IEICE Trans. Electron. 91-C(4): 526-533 (2008) - [j7]Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi:
Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits 43(4): 762-768 (2008) - 2007
- [j6]Kazuo Otsuga, Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi:
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories. IEICE Trans. Electron. 90-C(4): 772-778 (2007) - [j5]Hideaki Kurata, Satoshi Noda, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume, Kazuki Homma, Teruhiko Ito, Yoshinori Sakamoto, Masahiro Shimizu, Yoshinori Ikeda, Osamu Tsuchiya, Kazunori Furusawa:
A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology. IEICE Trans. Electron. 90-C(11): 2146-2156 (2007) - [j4]Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya:
Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. IEEE J. Solid State Circuits 42(6): 1362-1369 (2007) - 2006
- [j3]Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa:
A 130-nm CMOS 95-mm2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput. IEICE Trans. Electron. 89-C(10): 1469-1479 (2006) - 2005
- [j2]Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara
:
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. IEEE J. Solid State Circuits 40(2): 523-531 (2005) - 2002
- [c1]Kazuo Kiguchi, Koya Iwami, Makoto Yasuda, Hideaki Kurata, Keigo Watanabe, Toshio Fukuda:
Intelligent Interface and Control of an Exoskeletal Robot for Human Shoulder Motion Support Considering Subject's Arm Posture. ICRA 2002: 3230-3235
1990 – 1999
- 1999
- [j1]Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications. IEEE J. Solid State Circuits 34(11): 1544-1550 (1999)
Coauthor Index
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