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Eduardo Marques
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2020 – today
- 2022
- [j9]Rui Lopes
, Filipe Rocha, Susana Sargento
A multi-layer probing approach for video over 5G in vehicular scenarios. Veh. Commun. 38: 100534 (2022)
2010 – 2019
- 2019
- [c36]Frederica Gonçalves
Tourism Guidance Tracking and Safety Platform. INTSYS 2019: 162-171 - 2017
- [c35]Carlos Alberto Oliveira De Souza
A Hardware/Software Codesign for the Chemical Reactivity of BRAMS. DSD 2017: 70-77 - [c34]André B. Perina, Paulo Matias
Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA. DSD 2017: 516-519 - 2016
- [j8]Luiz G. A. Martins
Clustering-Based Selection for the Exploration of Compiler Optimization Sequences. ACM Trans. Archit. Code Optim. 13(1): 8:1-8:28 (2016) - [c33]José Arnaldo Mascagni de Holanda, João Manuel Paiva Cardoso
A pipelined multi-softcore approach for the HOG algorithm. DASIP 2016: 146-153 - [c32]Leandro Andrade Martinez, Eduardo Marques:
A hardware/software codesign framework for vision-based ADAS. FPL 2016: 1-2 - [c31]José Arnaldo Mascagni de Holanda, João Manuel Paiva Cardoso
Towards a multi-softcore FPGA approach for the HOG algorithm. INDIN 2016: 117-122 - 2015
- [j7]Hervé Paulino
Heterogeneous programming with Single Operation Multiple Data. J. Comput. Syst. Sci. 81(1): 16-37 (2015) - [c30]Maikon Adiles Fernandez Bueno, Carlos R. P. Almeida Jr., José A. M. de Holanda, Eduardo Marques
Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs. ARC 2015: 435-442 - [c29]Cristiano Bacelar de Oliveira, Ricardo Menotti
A special-purpose language for implementing pipelined FPGA-based accelerators. FDL 2015: 74-81 - 2014
- [j6]Vanderlei Bonato
Practical Education Fostered by Research Projects in an Embedded Systems Course. Int. J. Reconfigurable Comput. 2014: 287205:1-287205:12 (2014) - [c28]Jecel Mattos de Assumpção Jr., Merik Voswinkel, Eduardo Marques
Adapting Processor Grain via Reconfiguration. ARC 2014: 262-267 - [c27]Luiz G. A. Martins
A clustering-based approach for exploring sequences of compiler optimizations. IEEE Congress on Evolutionary Computation 2014: 2436-2443 - [c26]Cristiano Bacelar de Oliveira, João M. P. Cardoso
High-Level Synthesis from C vs. a DSL-Based Approach. IPDPS Workshops 2014: 257-262 - [c25]Luiz G. A. Martins
Exploration of compiler optimization sequences using clustering-based selection. LCTES 2014: 63-72 - [c24]Maikon Adiles Fernandez Bueno, José A. M. de Holanda, Erinaldo Pereira, Eduardo Marques
Operating system support to an online hardware-software co-design scheduler for heterogeneous multicore architectures. RTCSA 2014: 1-10 - [c23]Victor Adriel de J. Oliveira
Tactile Interface for Navigation in Underground Mines. SVR 2014: 230-237 - 2013
- [j5]Vanderlei Bonato
A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm. J. Signal Process. Syst. 70(1): 75-85 (2013) - [c22]Luiz G. A. Martins
Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation. FPL 2013: 1-2 - [i1]Hervé Paulino, Eduardo Marques:
Heterogeneous Programming with Single Operation Multiple Data. CoRR abs/1312.4993 (2013) - 2012
- [j4]Ricardo Menotti
LALP: A Language to Program Custom FPGA-Based Acceleration Engines. Int. J. Parallel Program. 40(3): 262-289 (2012) - [c21]Cristiano B. Oliveira, Eduardo Marques
Combining data and computation transformations for fine-grain reconfigurable architectures. FPL 2012: 489-490 - [c20]Eduardo Marques, Hervé Paulino
Single Operation Multiple Data - Data Parallelism at Subroutine Level. HPCC-ICESS 2012: 254-261 - [c19]Eduardo Marques, Valter Balegas, Bruno Fontes Barroca
The RPG DSL: a case study of language engineering using MDD for generating RPG games for mobile phones. DSM@SPLASH 2012: 13-18 - 2011
- [c18]Drausio Linardi Rossi, Vanderlei Bonato
A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing. ReConFig 2011: 141-145
2000 – 2009
- 2009
- [j3]Vanderlei Bonato
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots. J. Signal Process. Syst. 56(1): 41-50 (2009) - [c17]Ricardo Menotti
Automatic generation of FPGA hardware accelerators using a domain specific language. FPL 2009: 457-461 - [c16]Ricardo Menotti
LALP: A Novel Language to Program Custom FPGA-Based Architectures. SBAC-PAD 2009: 3-10 - [c15]Vanderlei Bonato
RoboArch: A component-based tool proposal for developing hardware architecture for mobile robots. SIES 2009: 249-252 - 2008
- [j2]Vanderlei Bonato
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. IEEE Trans. Circuits Syst. Video Technol. 18(12): 1703-1712 (2008) - [c14]Vanderlei Bonato
A Parallel Hardware Architecture for Image Feature Detection. ARC 2008: 136-147 - 2007
- [c13]Ricardo Menotti
Aggressive Loop Pipelining for Reconfigurable Architectures. FPL 2007: 501-502 - [c12]Vanderlei Bonato
A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL 2007: 576-579 - [c11]Vanderlei Bonato
An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics. SIES 2007: 148-155 - [c10]José A. M. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques
On Adapting Power Estimation Models for Embedded Soft-Core Processors. SIES 2007: 345-348 - [c9]Jecel Assumpcao, Denis F. Wolf, Eduardo Marques
Towards a Hardware Accelerated Obstacle Avoidance System for Mobile Robots using Monocular Vision. SIES 2007: 365-368 - [e1]Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso
Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Lecture Notes in Computer Science 4419, Springer 2007, ISBN 978-3-540-71430-9 [contents] - 2006
- [c8]Vanderlei Bonato, José A. M. de Holanda, Eduardo Marques:
An Embedded Multi-camera System for Simultaneous Localization and Mapping. ARC 2006: 109-114 - [c7]Jorge Luiz e Silva, Eduardo Marques
Executing Algorithms for Dynamic Dataflow Reconfigurable Hardware -The Operators Protocol. ReConFig 2006: 64-70 - [c6]João Miguel Gago Pontes de Brito Lima, Ricardo Menotti
A Methodology to Design FPGA-based PID Controllers. SMC 2006: 2577-2583 - 2004
- [c5]Vanderlei Bonato, Adriano K. Sanches, Marcio Merino Fernandes, João M. P. Cardoso, Eduardo do Valle Simões, Eduardo Marques:
A Real Time Gesture Recognition System for Mobile Robots. ICINCO (2) 2004: 207-214 - [c4]Vanderlei Bonato
Teaching embedded systems with FPGAs throughout a computer science course. WCAE 2004: 4 - 2003
- [c3]Ana Cristina Bicharra Garcia, Eduardo Marques:
Web Navigation Patterns. ICEIS (4) 2003: 212-217 - [c2]R. A. Gonçalves, P. A. Moraes, João M. P. Cardoso, Denis F. Wolf, Marcio Merino Fernandes, Roseli A. Francelin Romero, Eduardo Marques:
ARCHITECT-R: A System for Reconfigurable Robots Design. SAC 2003: 679-683
1990 – 1999
- 1997
- [c1]Donald L. Hung, Antonio Arsgao, Jorge L. Silva, Eduardo Marques, Karl Hillesland:
UB1 - a recurrent neural network based parallel machine for solving simultaneous linear equations. SBRN 1997: 14-18
1980 – 1989
- 1986
- [j1]Claudio Kirner, Eduardo Marques:
Design of a distributed system support based on a centralized parallel bus. SIGARCH Comput. Archit. News 14(4): 15-26 (1986)
Coauthor Index
aka: João Manuel Paiva Cardoso
aka: José Arnaldo Mascagni de Holanda
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last updated on 2024-10-07 22:08 CEST by the dblp team
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