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Yuan Taur
Person information
- affiliation: University of California, San Diego, USA
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2010 – 2019
- 2014
- [j10]Chunmeng Dou, Dennis Lin, Abhitosh Vais, Tsvetan Ivanov, Han-Ping Chen, Koen Martens, Kuniyuki Kakushima, Hiroshi Iwai, Yuan Taur, Aaron Thean, Guido Groeseneken
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Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures. Microelectron. Reliab. 54(4): 746-754 (2014) - 2010
- [j9]Wei Wang, Huaxin Lu, Jooyoung Song, Shih-Hsien Lo, Yuan Taur:
Compact modeling of quantum effects in symmetric double-gate MOSFETs. Microelectron. J. 41(10): 688-692 (2010)
2000 – 2009
- 2009
- [j8]Jooyoung Song, Bo Yu, Yu Yuan, Yuan Taur:
A Review on Compact Modeling of Multiple-Gate MOSFETs. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1858-1869 (2009) - 2008
- [c1]Yuan Taur, Jooyoung Song, Bo Yu:
Compact modeling of multiple-gate MOSFETs. CICC 2008: 257-264 - 2001
- [j7]Yuan Taur:
Transistors and IC design. Adv. Comput. 55: 237-279 (2001) - [j6]David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, Hon-Sum Philip Wong:
Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3): 259-288 (2001)
1990 – 1999
- 1999
- [j5]Shih-Hsien Lo, Douglas A. Buchanan, Yuan Taur:
Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides. IBM J. Res. Dev. 43(3): 327-338 (1999) - 1998
- [j4]Yo-Chuol Ho, Kihong Kim, Brian A. Floyd
4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates. IEEE J. Solid State Circuits 33(12): 2066-2073 (1998) - 1997
- [j3]Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, Hon-Sum Philip Wong:
CMOS scaling into the nanometer regime. Proc. IEEE 85(4): 486-504 (1997) - 1995
- [j2]Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam G. Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman:
A half-micron CMOS logic generation. IBM J. Res. Dev. 39(1-2): 215-228 (1995) - [j1]Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak:
CMOS scaling into the 21st century: 0.1 µm and beyond. IBM J. Res. Dev. 39(1-2): 245-260 (1995)
Coauthor Index
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