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IEEE Journal of Solid-State Circuits, Volume 33
Volume 33, Number 1, January 1998
- Barrie Gilbert:
The multi-tanh principle: a tutorial overview. 2-17 - Changsik Yoo, Seung-Wook Lee, Wonchan Kim:
A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning. 18-27 - Hamid Reza Mehrvarz, Chee Yee Kwok:
A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs. 28-35 - Gabriel A. Rincón-Mora, Phillip E. Allen:
A low-voltage, low quiescent current, low drop-out regulator. 36-44 - Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez:
A Nyquist-rate delta-sigma A/D converter. 45-52 - Makoto Nagata
, Jun Funakoshi, Atsushi Iwata:
A PWM signal processing core circuit based on a switched current integration technique. 53-60 - Mohammad Hossein Shakiba, David A. Johns, Kenneth W. Martin:
An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder. 61-75 - Oliver Kromat, Ulrich Langmann, Gerhard Hanke, William J. Hillery:
A 10-Gb/s silicon bipolar IC for PRBS testing. 76-85 - Stephen Molloy, Rajeev Jain:
A 110-K transistor 25-MPixels/s configurable image transform processor unit. 86-97 - Johan Wulleman:
A BiCMOS front-end system with binary delay line for capacitive detector read-out. 98-108 - Tayfun Akin, Khalil Najafi, Robert M. Bradley:
A wireless implantable multichannel digital neural recording system for a micromachined sieve electrode. 109-118 - Takayuki Kawahara
20-Mb/s erase/record flash memory by asymmetrical operation. 119-125 - Takayuki Kawahara
Internal voltage generator for low voltage, quarter-micrometer flash memories. 126-132 - Marco Tartagni, Roberto Guerrieri:
A fingerprint sensor based on the feedback capacitive sensing scheme. 133-142 - Andrea Boni, Carlo Morandi:
High-speed, low-power BiCMOS comparator using a pMOS variable load. 143-146 - Simon J. Lovett, Marco Welten, Alan Mathewson
Optimizing MOS transistor mismatch. 147-150 - Kevin J. Page, Paul M. Chau:
Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding. 151-155 - Ali Tabatabaei, Ali Fotowat, Michael Delurio, Saeed Navid:
A high slew-rate unity-gain low-voltage buffer with large active/quiescent current ratio. 156-163 - Kiat Seng Yeo
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. 164-168 - Janusz Nieznanski
An alternative approach to the ROM-less direct digital synthesis. 169-170 - Tadao Nakagawa, Hideyuki Nosaka
Authors' Reply. 170 - Michael Schröter, David J. Walkey:
Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors". 171
Volume 33, Number 2, February 1998
- Ali Hajimiri
A general theory of phase noise in electrical oscillators. 179-194 - Wouter A. Serdijn, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund:
A wide-tunable translinear second-order oscillator. 195-201 - Francesco Piazza, Qiuting Huang:
A 1.57-GHz RF front-end for triple conversion GPS receiver. 202-209 - Akihiro Yamagishi, Masayuki Ishikawa, Tsuneo Tsukahara, Shigeru Date:
A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication. 210-217 - Jouko Vankka, Mikko Waltari, Marko Kosunen, Kari A. I. Halonen:
A direct digital synthesizer with an on-chip D/A-converter. 218-227 - Giuseppe Palmisano, Gaetano Palumbo, Salvatore Pennisi
High-drive CMOS current amplifier. 228-236 - Henrik O. Johansson, Christer Svensson:
Time resolution of NMOS sampling switches used on low-swing signals. 237-245 - James F. Ziegler, Martin E. Nelson, James Dean Shell, R. Jerry Peterson, Carl J. Gelderloos, Hans P. Muhlfeld, Charles J. Montrose:
Cosmic ray soft error rates of 16-Mb DRAM memory chips. 246-252 - Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana:
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. 253-259 - Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi:
Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. 260-267 - Takao Waho, Kevin J. Chen
Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output. 268-274 - Young-Jin Jeon, Man-Young Jeon, Jin-Myung Kim, Yoon-Ha Jeong, Dong-Ho Jeong, Dae Mann Kim:
Monolithic feedback low noise X-band amplifiers using 0.5-μm GaAs MESFETs: comparative theoretical study and experimental characterization. 275-279 - Teresa Serrano-Gotarredona
A high-precision current-mode WTA-MAX circuit with multichip capability. 280-286 - Massimo Lanzoni, G. Tondi, P. Galbiati, Bruno Riccò:
Automatic and continuous offset compensation of MOS operational amplifiers using floating-gate transistors. 287-290 - L. P. L. van Dijk, Albert C. van der Woerd, Jan Mulder, Arthur H. M. van Roermund:
An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids. 291-294 - Henrik O. Johansson:
A simple precharged CMOS phase frequency detector. 295-299 - Ion E. Opris:
Bootstrapped pad protection structure. 300-301 - Labros Bisdounis, Spiridon Nikolaidis
Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices. 302-306
Volume 33, Number 3, March 1998
- Nishath K. Verghese, David J. Allstot:
Computer-aided design considerations for mixed-signal coupling in RF integrated circuits. 314-323 - Jaijeet Roychowdhury, David E. Long, Peter Feldmann:
Cyclostationary noise analysis of large RF circuits with multitone excitations. 324-336 - James F. Parker, Daniel Ray:
A 1.6-GHz CMOS PLL with on-chip loop filter. 337-343 - David M. Binkley, James M. Rochelle, Brian K. Swann, Lloyd G. Clonts, Rhonda N. Goble:
A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications. 344-358 - Marc A. F. Borremans, Michiel S. J. Steyaert
A 2-V, low distortion, 1-GHz CMOS up-conversion mixer. 359-366 - Jind-Yeh Lee, Huan-Chang Liu, Henry Samueli:
A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications. 367-377 - Jose A. Macedo, Miles A. Copeland:
A 1.9-GHz silicon receiver with monolithic image filtering. 378-386 - Lawrence E. Larson:
Integrated circuit technology options for RFICs-present status and future directions. 387-399 - Scott C. Munroe, Albert K. Lu:
2-μm, 1.6-mW gated-gm sampler with 72-dB SFDR for fs=160 Ms/s and fin=320.25 MHz. 400-409 - Pierre Favrat, Philippe Deval, Michel J. Declercq:
A high-efficiency CMOS voltage doubler. 410-416 - Xiaodong Wang, Richard R. Spencer:
A low-power 170-MHz discrete-time analog FIR filter. 417-426 - Joshua C. Park, L. Richard Carley:
High-speed CMOS continuous-time complex graphic equalizer for magnetic recording. 427-438 - Colin C. McAndrew:
Practical modeling for circuit simulation. 439-448 - Dennis Sylvester, James C. Chen, Chenming Hu:
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation. 449-453 - Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama:
Variable supply-voltage scheme for low-power high-speed CMOS digital design. 454-462 - Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami:
Automated low-power technique exploiting multiple supply voltages applied to a media processor. 463-472 - Inyup Kang, Alan N. Willson Jr.:
Low-power Viterbi decoder for CDMA mobile terminals. 473-482 - Benoît R. Veillette, Gordon W. Roberts:
On-chip measurement of the jitter transfer function of charge-pump phase-locked loops. 483-491 - Naoya Kusayanagi, Toru Choi, Masaya Hiwatashi, Masahiro Segami, Yasukazu Akasaka, Tadashi Wakabayashi:
A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes. 492-496 - David A. Martin, Hae-Seung Lee, Ichiro Masaki:
A mixed-signal array processor with early vision applications. 497-502 - Christian Lütkemeyer, Tobias G. Noll:
A transversal equalizer with an increased adaptation speed and tracking capability. 503-507 - Jeffrey A. Kash, James C. Tsang, Richard F. Rizzolo, A. K. Patel, A. D. Shore:
Backside optical emission diagnostics for excess IDDQ. 508-511
Volume 33, Number 4, April 1998
- Ahmadreza Rofougaran, Glenn Chang, Jacob J. Rael, James Y.-C. Chang, Maryam Rofougaran, Paul J. Chang, Masoud Djafari, M.-K. Ku, Edward W. Roth, Asad A. Abidi, Henry Samueli:
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. I. Architecture and transmitter design. 515-534 - Ahmadreza Rofougaran, Glenn Chang, Jacob J. Rael, James Y.-C. Chang, Maryam Rofougaran, Paul J. Chang, Masoud Djafari, M.-K. Ku, Edward W. Roth, Asad A. Abidi, Henry Samueli:
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. II. Receiver design. 535-547 - Keng Leong Fong, Robert G. Meyer:
High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages. 548-555 - Gian Marco Bo, Daniele D. Caviglia
An analog VLSI implementation of a feature extractor for real time optical character recognition. 556-564 - Carlos Azeredo Leme, José Silva, Paulo Rodrigo, José E. da Franca:
A low-power CMOS nine-channel 40-MHz binary detection system with self-calibrated 500-μV offset. 565-572 - Karim Arabi, Bozena Kaminska:
Design for testability of embedded integrated operational amplifiers. 573-581 - Martin Pfost, Hans-Martin Rein:
Modeling and measurement of substrate coupling in Si-bipolar IC's up to 40 GHz. 582-591 - Jieh-Tsorng Wu, Kuen-Long Chang:
MOS charge pumps for low-voltage operation. 592-597 - Chi-Chang Wang, Jiin-Chuan Wu:
A 3.3-V/5-V low power TTL-to-CMOS input buffer. 598-603 - Gustavo A. Ruiz
Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits. 604-613 - Alain Fabre, Omar Saaid, Francis Wiest, Christophe Boucheron:
High-frequency high-Q BiCMOS current-mode bandpass filter and mobile communication application. 614-625 - Angelo Nagari, Germano Nicollini:
A 3 V 10 MHz pseudo-differential SC bandpass filter using gain enhancement replica amplifier. 626-630 - Henrik Sjöland
A 100-MHz CMOS wide-band IF amplifier. 631-634 - Andrea Baschirotto
A versatile high-speed bipolar charge-sensitive preamplifier for calorimeter applications. 635-639 - Jean-Paul Eggermont, Denis Flandre
Potential and modeling of 1-μm SOI CMOS operational transconductance amplifiers for applications up to 1 GHz. 640-643 - Seyed R. Zarabadi, Mohammed Ismail, Chung-Chih Hung:
High performance analog VLSI computational circuits. 644-649 - Pietro Andreani, Franco Bigongiari, Roberto Roncella
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution. 650-656 - Mankoo Lee:
A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation. 657-661 - Phillip J. Restle, Keith A. Jenkins, Alina Deutsch, Peter W. Cook:
Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor. 662-665 - Kohei Fujii:
A sophisticated analysis procedure for an MMIC phase shifter. 666-668 - Harold J. Levy, Erik S. Daniel, Thomas C. McGill:
A transistorless-current-mode static RAM architecture. 669-672
Volume 33, Number 5, May 1998
- Paul E. Gronowski, William J. Bowhill, Ronald P. Preston, Michael K. Gowan, Randy L. Allmon:
High-performance microprocessor design. 676-686 - Rajeevan Amirtharajah
Self-powered signal processing using vibration-based power generation. 687-695 - Yong Moon, Deog-Kyoon Jeong:
A 32×32-b adiabatic register file with supply clock generator. 696-701 - Masafumi Nogawa, Yusuke Ohtomo:
A data-transition look-ahead DFF circuit for statistical reduction in power consumption. 702-706 - James A. Farrell, Timothy C. Fischer:
Issue logic for a 600-MHz out-of-order execution microprocessor. 707-712 - Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz:
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. 713-722 - Weinan Gao, W. Martin Snelgrove:
A 950-MHz IF second-order integrated LC bandpass delta-sigma modulator. 723-732 - Colby D. Boles, Bernhard E. Boser, Bruce H. Hasegawa, Joseph A. Heanue:
A multimode digital detector readout for solid-state medical imaging detectors. 733-742 - C. Patrick Yue, S. Simon Wong:
On-chip spiral inductors with patterned ground shields for Si-based RF ICs. 743-752 - Keith K. Onodera, Paul R. Gray:
A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs]. 753-761 - Koji Kotani, Tadashi Shibata, Tadahiro Ohmi:
CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters. 762-769 - Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada:
400-MHz random column operating SDRAM techniques with self-skew compensation. 770-778 - Kyu-Chan Lee, Changhyun Kim, Hongil Yoon, Keum-Yong Kim, Byung-Sik Moon, Sang-Bo Lee, Jung-Hwa Lee, Nam-Jong Kim, Soo-In Cho:
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme. 779-786 - Daisaburo Takashima, Iwao Kunishima:
High-density chain ferroelectric random access memory (chain FRAM). 787-792 - Shoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi:
A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's. 793-799 - Kazushige Ayukawa, Takao Watanabe, Susumu Narita:
An access-sequence control scheme to enhance random-access performance of embedded DRAM's. 800-806 - Hiroshi Kawaguchi
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. 807-811 - Hiroshi Komurasaki, Hisayasu Sato, Nagisa Sasaki, Takahiro Miki:
A 2-V 1.9-GHz Si down-conversion mixer with an LC phase shifter. 812-815 - Kyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog-Kyoon Jeong, Gyudong Kim, Bruce Kim, Victor Da Costa:
1.04 GBd low EMI digital video interface system using small swing serial link technique. 816-823
Volume 33, Number 6, June 1998
- Christoph Kuratli, Qiuting Huang:
A fully integrated self-calibrating transmitter/receive IC for an ultrasound presence detector microsystem. 832-841 - Fernando Pardo, Bart Dierickx
Space-variant nonorthogonal structure CMOS image sensor design. 842-849 - Mehran Aliahmad, C. André T. Salama:
Integration of a short-loop SLIC in a low-voltage submicron BiCMOS technology. 850-858 - Shuo-Yuan Hsiao, Chung-Yu Wu:
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer. 859-869 - Kevin W. Kobayashi, Aaron K. Oki, Donald K. Umemoto, Tomas Ray Block, Dwight C. Streit:
A novel self-oscillating HEMT-HBT cascode VCO-mixer using an active tunable inductor. 870-876 - Alan L. L. Pun, Tony Yeung, Jack Lau, François J. R. Clément, David K. Su:
Substrate noise coupling through planar spiral inductor. 877-884 - Eleonora Franchi, Nicolò Manaresi, Riccardo Rovatti
Analog synthesis of nonlinear functions based on fuzzy logic. 885-895 - Hervé Mathias, Josette Berger-Toussan, Gilles Jacquemod, Frédéric Gaffiot, Michel Le Helley:
FLAG: a flexible layout generator for analog MOS transistors. 896-903 - Kyung-Wook Shin, Bang-Sup Song, Kantilal Bacrania:
A 200-MHz complex number multiplier using redundant binary arithmetic. 904-909 - Gab Joong Jeong, Moon Key Lee:
Design of a scalable pipelined RAM system. 910-914 - Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio:
Low-voltage class AB buffers with quiescent current control. 915-920 - Yoonjong Huh, Yungkwon Sung, Sung-Mo Kang:
A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits. 921-927 - Ali Hajimiri, Thomas H. Lee:
Corrections to "A General Theory of Phase Noise in Electrical Oscillators". 928 - Kevin J. McGee:
Comments on "A 64-point Fourier transform chip for video motion compensation using phase correlation". 928-932
Volume 33, Number 7, July 1998
- Alain Guyot, Bram Nauta:
Guest Editorial. 935-936 - Qiuting Huang, Michael Oberle:
A 0.5-mW passive telemetry IC for biomedical applications. 937-946 - Tonny A. F. Duisters, Eise Carel Dijkmans:
A -90-dB THD rail-to-rail input opamp using a new local charge pump in CMOS. 947-955 - Gerrit W. den Besten, Bram Nauta
Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology. 956-962 - Patrick J. Quinn:
High-accuracy charge-redistribution SC video bandpass filter in standard CMOS. 963-975 - Diego Vázquez, Adoración Rueda
A high-Q bandpass fully differential SC filter with enhanced testability. 976-986 - Cicero Vaucher, Dieter Kasperkovitz:
A wide-band tuning system for fully integrated satellite receivers. 987-997 - Norman M. Filiol, Thomas A. D. Riley, Calvin Plett, Miles A. Copeland:
An agile ISM band frequency synthesizer with built-in GMSK data modulation. 998-1008 - Hervé Marie, Philippe Belin:
R, G, B acquisition interface with line-locked clock generator for flat panel display. 1009-1013 - Philippe Cathelin, Andreia Cathelin, Xavier Saboret, Nicolas Krasnanski, Pierre Legras, Raed V. Moughabghab, Olivier Declerck, Marc Miodini, Frank Op't Eynde:
A fully integrated CMOS PM radio receiver for wristwatch calibration. 1014-1022 - Qiuting Huang, Francesco Piazza, Paolo Orsatti, Tatsuya Ohguro:
The impact of scaling down to deep submicron on CMOS RF circuits. 1023-1036 - Bernard M. Tenbroek, Michael S. L. Lee, William Redman-White, R. John T. Bunyan, Michael J. Uren
Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. 1037-1046 - Didier Belot, Laurent Dugoujon, S. Dedieu:
A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH. 1047-1058 - David Hossack, John I. Sewell:
A robust CMOS compander. 1059-1064 - Augusto Manuel Marques, Vincenzo Peluso, Michel S. J. Steyaert
A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology. 1065-1075 - William Redman-White, Roy Duffee, Simon Bramwell, Hans Rijns, Shirley James, James Tijou, Gerard van der Weide:
A robust analog interface system for submicron CMOS video DSP. 1076-1081 - Michele Borgatti, Marco Felici, Alberto Ferrari, Roberto Guerrieri:
A low-power integrated circuit for remote speech recognition. 1082-1089 - Donato Montanari, Jan Van Houdt, Guido Groeseneken
Novel level-identifying circuit for flash multilevel memories. 1090-1095 - Jong-Shik Kim, Yu-Soo Choi, Hoi-Jun Yoo, Kwang-Seok Seo:
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F2 cell [CMOS design]. 1096-1102 - Alvaro Bernal
A new low-power GaAs two-single-port memory cell. 1103-1110 - Diego Mateo
Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic. 1111-1116 - Mike Tuthill:
A switched-current, switched-capacitor temperature sensor in 0.6-μm CMOS. 1117-1122 - Manfred Punzenberger, Christian C. Enz:
A compact low-power BiCMOS log-domain filter. 1123-1129 - Herman Casier, Patrick Wouters, Benny Graindourze, Daniel Sallaerts:
A 3.3-V, low-distortion ISDN line driver with a novel quiescent current control circuit. 1130-1133 - David Moloney, Jerry O'Brien, Eugene O'Rourke, Francesco Brianti:
Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS]. 1134-1138 - Martin Ehlert, Heinrich Klar:
A 12-bit medium-time analog storage device in a CMOS standard process. 1139-1143
Volume 33, Number 8, August 1998
- Clemens M. Hammerschmied, Qiuting Huang:
Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD. 1148-1157 - Germano Nicollini, Sergio Pernici, Pierangelo Confalonieri, Carlo Crippa, Angelo Nagari, Sergio Mariani, Aldo Calloni, Massimo Moioli, Carlo Dallavalle:
A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones. 1158-1167 - Chun-Sup Kim, Geo-Ok Cho, Yong-Hwan Kim, Bang-Sup Song:
A CMOS 4× speed DVD read channel IC. 1168-1178 - Makoto Nakamura, Noboru Ishihara, Yukio Akazawa:
A 156-Mb/s CMOS optical receiver for burst-mode transmission. 1179-1187 - Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun, Far-Wen Jih, Ya-Tung Cherng:
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA. 1188-1198 - Vladimir Brajovic, Takao Kanade:
Computational sensor for visual tracking with attention. 1199-1207 - Bharadwaj S. Amrutur, Mark A. Horowitz:
A replica technique for wordline and sense control in low-power SRAM's. 1208-1219 - Hiroki Morimura, Nobutaro Shibata:
A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's. 1220-1227 - Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa
A multipage cell architecture for high-speed programming multilevel NAND flash memories. 1228-1238 - Enrique Palazuelos, Almudena Suárez
Hysteresis prediction in autonomous microwave circuits using commercial software: application to a Ku-band MMIC VCO. 1239-1243 - Dong-Young Chang, Seung-Hoon Lee:
Design techniques for a low-power low-cost CMOS A/D converter. 1244-1248 - Kenneth O:
Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies. 1249-1252 - Thou-Ho Chen:
A cost-effective three-step hierarchical search block-matching chip for motion estimation. 1253-1258 - Robert Berger, W. Gregory Lyons, Antonio M. Soares:
A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing. 1259-1261 - Jaume Segura
A variable threshold voltage inverter for CMOS programmable logic circuits. 1262-1265 - Jeong Beom Kim, Sung Je Hong, Jong Kim:
Design of a built-in current sensor for IDDQ testing. 1266-1272
Volume 33, Number 9, September 1998
- Jan-Erik Müller, Peter Baureis, Otto Berger, Thomas Boettner, Nicola Bovolon, Rüdiger Schultheis, Gerhard Packeiser, Peter Zwicknagl:
A small chip size 2 W, 62% efficient HBT MMIC for 3 V PCN applications. 1277-1283 - Tadayoshi Nakatsuka, Junji Itoh, Takayuki Yoshida, Mitsuru Nishitsuji, Tomoya Uda, Osamu Ishikawa:
A highly miniaturized front-end HIC for 1.9 GHz bands. 1284-1289 - Toshihiko Yoshimasu, Masanori Akagi, Noriyuki Tanba, Shinji Hara:
An HBT MMIC power amplifier with an integrated diode linearizer for low-voltage portable phone applications. 1290-1296 - Huainan Ma, Sher Jiun Fang, Fujiang Lin, Khen-Sang Tan, Junichi Shibata, Atsushi Tamura, Hiroshi Nakamura:
A GaAs upconverter MMIC with an automatic gain control amplifier for 1.9 GHz PHS. 1297-1305 - Chris Diorio, Todd Humes, Johannes K. Notthoff, Gregory Chao, Alex Lai, John Hyde, Mark Kintis, Aaron K. Oki:
A low-noise, GaAs/AlGaAs, microwave frequency-synthesizer IC. 1306-1312 - Hideyuki Suzuki, Koichi Watanabe, Kyosuke Ishikawa, Hiroshi Masuda, Kiyoshi Ouchi, Tomonori Tanoue, Ryoji Takeyari:
Very-high-speed InP/InGaAs HBT ICs for optical transmission systems. 1313-1320 - Taiichi Otsuji
An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs. 1321-1327 - Philippe André, Jean-Louis Benchimol, Patrick Desrousseaux, Anne-Marie Duchenois, Jean Godin, Agnieszka Konczykowska, Mounir Meghelli, Muriel Riet, André Scavennec:
InP DHBT technology and design methodology for high-bit-rate optical communications circuits. 1328-1335 - Yasuyuki Suzuki, Hidenori Shimawaki, Yasushi Amamiya, Nobuo Nagano, Takaki Niwa, Hitoshi Yano, Kazuhiko Honjo:
50-GHz-bandwidth baseband amplifiers using GaAs-based HBTs. 1336-1341 - Tom P. E. Broekaert, Berinder Brar, J. Paul A. van der Wagt, Alan C. Seabaugh
A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter. 1342-1349 - Jeff Durec:
An integrated silicon bipolar receiver subsystem for 900-MHz ISM band applications. 1352-1372 - Sang-Soo Lee, Carlos A. Laber:
A BiCMOS continuous-time filter for video signal processing applications. 1373-1382 - D. Scott Langford, Bruce J. Tesch, Brian E. Williams, G. Rodney Nelson Jr.:
A BiCMOS analog front-end circuit for an FDM-based ADSL system. 1383-1393 - Brent A. Myers, Scott Bardsley, Patrick Landy, Timothy Bell, Robert Ross:
A frequency agile monolithic QPSK modulator with spectral filtering and 75 Ω differential line driver. 1394-1405 - Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V 2-GHz BJT variable frequency oscillator. 1406-1410 - Mounir Meghelli, Michel Bouché, Agnieszka Konczykowska:
High power and high speed InP DHBT driver IC's for laser modulation. 1411-1416 - Rainer Götzfried, Frank Beisswanger, Stephan Gerlach:
Design of RF integrated circuits using SiGe bipolar technology. 1417-1422 - Kiyoto Watabe, Hajime Akiyama, Tomohide Terashima, Masakazu Okada, Shinji Nobuto, Masao Yamawaki, Sotoju Asa:
An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI. 1423-1427 - Jaejune Jang, Edwin C. Kan, Torkel Arnborg, Ted Johansson
Characterization of RF power BJT and improvement of thermal stability with nonlinear base ballasting. 1428-1432 - Ya-Hong Xie, Michel R. Frei, Andrew J. Becker, Clifford A. King, D. Kossives, L. T. Gomez, S. K. Theiss:
An approach for fabricating high-performance inductors on low-resistivity substrates. 1433-1438 - K. M. Walter, B. Ebersman, D. A. Sunderland, G. D. Berg, Greg G. Freeman, Robert A. Groves, D. K. Jadus, David L. Harame:
A scaleable, statistical SPICE Gummel-Poon model for SiGe HBTs. 1439-1444 - Eli Chiprout:
Interconnect and substrate modeling and analysis: an overview. 1445-1452 - James Victory, Colin C. McAndrew, Jeff Hall, Mike Zunino:
A four-terminal compact model for high voltage diffused resistors with field plates. 1453-1458
Volume 33, Number 10, October 1998
- Arnold R. Feldman, Bernhard E. Boser, Paul R. Gray:
A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications. 1462-1469 - Ali M. Niknejad, Robert G. Meyer:
Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs. 1470-1481 - Klaas-Jan de Langen, Johan H. Huijsing:
Compact low-voltage power-efficient operational amplifier cells for VLSI. 1482-1496 - Amer Aslam-Siddiqi, Werner Brockherde
A 128-pixel CMOS image sensor with integrated analog nonvolatile memory. 1497-1501 - Amer Aslam-Siddiqi, Werner Brockherde
A 16×16 nonvolatile programmable analog vector-matrix multiplier. 1502-1509 - Ana Isabela Araújo Cunha, Márcio Cherem Schneider, Carlos Galup-Montoro
An MOS transistor model for analog circuit design. 1510-1519 - Zhihao Lao, Andreas Thiede, Ulrich Nowotny, Hariolf Lienhart, Volker Hurm, Michael Schlechtweg, Jochen Hornung, Wolfgang Bronner
40-Gb/s high-power modulator driver IC for lightwave communication systems. 1520-1526 - Koichi Murata, Taiichi Otsuji
A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μm GaAs MESFET's. 1527-1535 - Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino:
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. 1536-1544 - Christopher G. Knight, Adit D. Singh, Victor P. Nelson:
An IDDQ sensor for concurrent timing error detection. 1545-1550 - Gabriel A. Rincón-Mora, Phillip E. Allen:
A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference. 1551-1554 - Henrik Sjöland
A 160-MHz bipolar wide-band IF amplifier. 1555-1558 - Yasuyuki Suzuki, Kazuhiko Honjo:
Wide-band transimpedance amplifiers using AlGaAs/InxGa1-xAs pseudomorphic 2-DEG FET's. 1559-1562 - Andrea Boni, Gebhard Melcher, Carlo Morandi:
3.3-V, 200-Ms/s BiCMOS comparator for current-mode interpolation using a transconductance stage. 1563-1567 - Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu:
New dynamic flip-flops for high-speed dual-modulus prescaler. 1568-1571 - Hun-Hsien Chang, Jiin-Chuan Wu:
A 723-MHz 17.2-mW CMOS programmable counter. 1572-1575 - Yuh-Kuang Tseng, Chung-Yu Wu:
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications. 1576-1579 - Martin Margala
Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation-a comparative study. 1580-1585 - Kai Chen, Chenming Hu:
Performance and Vdd scaling in deep submicrometer CMOS. 1586-1589 - George S. Taylor, Gerard M. Blair:
Reduced complexity two-phase micropipeline latch controller. 1590-1593
Volume 33, Number 11, November 1998
- Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka
A 1.0-GHz single-issue 64-bit powerPC integer processor. 1600-1608 - Chekib Akrout, John Bialas, Miles G. Canada, Duane Cawthron, James Corr, Bijan Davari, Robert Floyd, Stephen F. Geissler, Ronald Goldblatt, Robert Houle, Paul Kartschoke, Diane Kramer, Pete McCormick, Norman J. Rohrer, Gerard Salem, Ronald Schulz, Lisa Su, Linda Whitney:
A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects. 1609-1616 - Benedict Lau, Yiu-Fai Chan, Alfredo Moncayo, John T. C. Ho, Mike Allen, Joe Salmon, Jonathan Liu, Manish Muthal, Cliff Lee, Tim Nguyen, Bryce Horine, Mike Leddige, Kuojim Huang, Jason Wei, Leung Yu, Richard Tarver, Yuwen Hsia, Roxanne Vu, Ely Tsern, Haw-Jyh Liaw, Jim Hudson, David Nguyen, Kevin S. Donnelly, Richard Crisp:
A 2.6-GByte/s multipurpose chip-to-chip interface. 1617-1626 - Daniel W. Bailey, Bradley J. Benschneider:
Clocking design and analysis for a 600-MHz Alpha microprocessor. 1627-1633 - Vincent R. von Kaenel:
A high-speed, low-power clock generator for a microprocessor application. 1634-1639 - Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai:
A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. 1640-1648 - Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma:
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. 1650-1658 - Kenneth W. Mai
Low-power SRAM design using half-swing pulse-mode techniques. 1659-1671 - Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada:
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. 1672-1681 - Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino:
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. 1682-1689 - Farhad Shafai, Kenneth J. Schultz, G. F. Randall Gibson, Armin G. Bluschke, David E. Somppi:
Fully parallel 30-MHz, 2.5-Mb CAM. 1690-1696 - Satoshi Eto, Masato Matsumiya, Masato Takita, Yuki Ishii, Toshikazu Nakamura, Kuninori Kawabata, Hideki Kano, Ayako Kitamoto, Toshimi Ikeda, Toru Koga, Mitsuhiro Higashiho, Yuji Serizawa, Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Masao Taguchi:
A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line. 1697-1702 - Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. 1703-1710 - Toshiaki Kirihata, Martin Gall, Kohji Hosokawa
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. 1711-1719 - Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama, Hisakatsu Araki, Tsz-Shing Cheung, Kohtaroh Gotoh, Tadao Aikawa, Takaaki Suzuki, Masao Taguchi, Takeshi Imamura:
500-Mb/s nonprecharged data bus for high-speed DRAM's. 1720-1730 - Jeffrey H. Dreibelbis, John Barth, Howard L. Kalter, Rex Kho:
Processor-based built-in self-test for embedded DRAM. 1731-1740 - Matthew M. Griffin, Jared Zerbe, Grace Tsang, Michael Ching, Clemenz L. Portmann:
A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation. 1741-1751 - Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata:
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. 1752-1757 - Kyu-Hyoun Kim
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS). 1758-1762 - Eiji Ogura, Masatoshi Takashima, Daisuke Hiranaka, Toshiro Ishikawa, Yukio Yanagita, Shuji Suzuki, Tokuya Fukuda, Toshiyuki Ishii:
A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H±288, V: ±96) motion estimation and 81-MOPS controller. 1765-1771 - Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama:
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. 1772-1780 - Christophe Del Toso, Pierre Combelles, Jacques Galbrun, Ludovic Lauer, Pierre Penard, Patrick Robertson, Fabio Scalise, Patrice Senn, Laurent Soyer:
0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard. 1781-1792 - Jos A. Huisken
A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcasting. 1793-1798 - James Goodman, Abram P. Dancy, Anantha P. Chandrakasan:
An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter. 1799-1809 - Luca Bolcioni, Michele Borgatti, Marco Felici, Roberto Rambaldi, Roberto Guerrieri:
A low-power, voice-controlled, H.263 video decoder for portable applications. 1810-1819 - Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. 1820-1828 - Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen:
A low-cost, 300-MHz, RISC CPU with attached media processor. 1829-1839 - Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato:
A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. 1840-1850 - G. Diwakar Vishakhadatta, Russell Croman, Marius Goldenberg, Jerrell P. Hein, Pradeep Katikaneni, Diana Kuai, Cathy Lee, Ion Constatin Tesu, Richard Trujillo, Ligang Zhang, Kent Anderson, Richard Behrens, William Bliss, Li Du, Trent Dudley, German Feyh, William Foland, Michael Kastner, Qingfen Li, Jeff Mitchem, David Reed, Sian She, Mark Spurbeck, Lisa Sundell, Hoai Tran, Maoxin Wei, Christopher Zook:
An EPR4 read/write channel with digital timing recovery. 1851-1857
Volume 33, Number 12, December 1998
- Ichiro Fujimori, Tetsuro Sugimoto:
A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter. 1863-1870 - Robert Adams, Khiem Nguyen, Karl Sweetland:
A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling. 1871-1878 - Akira Yasuda, Hiroshi Tanimoto, Tetsuya Iida:
A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching. 1879-1886 - Vincenzo Peluso, Peter J. Vancorenland, Augusto Manuel Marques, Michel S. J. Steyaert
A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range. 1887-1897 - Ion E. Opris, Laurence D. Lewicki, Bill C. Wong:
A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter. 1898-1903 - Daihong Fu, Kenneth C. Dyer, Stephen H. Lewis, Paul J. Hurst:
A digital background calibration technique for time-interleaved analog-to-digital converters. 1904-1911 - Kenneth C. Dyer, Daihong Fu, Stephen H. Lewis, Paul J. Hurst:
An analog background calibration technique for time-interleaved analog-to-digital converters. 1912-1919 - Joseph M. Ingino, Bruce A. Wooley:
A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter. 1920-1931 - Michael P. Flynn, Ben Sheahan:
A 400-Msample/s, 6-b CMOS folding and interpolating ADC. 1932-1938 - Sanroku Tsukamoto, William G. Schofield, Toshiaki Endo:
A CMOS 6-b, 400-MSample/s ADC with error correction. 1939-1947 - Chi-Hung Lin, Klaas Bult:
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. 1948-1958 - José Bastos
A 12-bit intrinsic accuracy high-speed CMOS DAC. 1959-1969 - Jan-Michael Stevenson, Edgar Sánchez-Sinencio:
An accurate quality factor tuning scheme for IF and high-Q continuous-time filters. 1970-1978 - Mohammad Hossein Shakiba, Tirdad Sowlati:
Automatic swing control in relaxation oscillators. 1979-1986 - Markus Zannoth, Bernd Kolb, Joseph Fenk, Robert Weigel:
A fully integrated VCO at 2 GHz. 1987-1991 - Bram Nauta
Analog line driver with adaptive impedance matching. 1992-1998 - Paul C. de Jong, Gerard C. M. Meijer, Arthur H. M. van Roermund:
A 300°C dynamic-feedback instrumentation amplifier. 1999-2009 - Kush Gulati, Hae-Seung Lee:
A high-swing CMOS telescopic operational amplifier. 2010-2019 - Jianjun Zhou
Monolithic transformers and their application in a differential CMOS RF low-noise amplifier. 2020-2027 - Joachim N. Burghartz, Daniel C. Edelstein, Mehmet Soyuer, Herschel A. Ainspan, Keith A. Jenkins:
RF circuit design aspects of spiral inductors on silicon. 2028-2034 - Hirad Samavati, Ali Hajimiri
Fractal capacitors. 2035-2041 - Ian Galton, William Huff, Paolo Carbone
A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal. 2042-2053 - Jan Craninckx
A fully integrated CMOS DCS-1800 frequency synthesizer. 2054-2065 - Yo-Chuol Ho, Kihong Kim, Brian A. Floyd
4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates. 2066-2073 - Peter G. M. Baltus, Anthony G. Wagemans, Ronald Dekker, Anton Hoogstraate, H. Maas, A. Tombeur, Jan van Sinderen:
A 3.5-mW, 2.5-GHz diversity receiver and a 1.2-mW, 3.6-GHz VCO in silicon on anything. 2074-2079 - Steven Decker, R. Daniel McGrath, Kevin Brehmer, Charles G. Sodini:
A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output. 2081-2091 - Marc J. Loinaz, Kanwar Jit Singh, Andrew J. Blanksby, David A. Inglis, Kamran Azadet, Bryan D. Ackland:
A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s. 2092-2103 - Stewart G. Smith, J. E. D. Hurwitz, Mairi J. Torrie, Donald J. Baxter, Andrew A. Murray, Paul Likoudis, Andrew J. Holmes, Mark J. Panaghiston, Robert K. Henderson
A single-chip CMOS 306×244-pixel NTSC video camera and a descendant coprocessor device. 2104-2111 - Tim Cummins, Eamonn Byrne, Dara Brannick, Dennis A. Dempsey:
An IEEE 1451 standard transducer interface chip with 12-b ADC, two 12-b DAC's, 10-kB flash EEPROM, and 8-b microcontroller. 2112-2120 - Bertram Rodgers, Sofjan Goenawan, Mohammad Yunus, Yoshikazu Kaneko, Junichi Yoshiike:
A 16-μA interface circuit for a capacitive flow sensor. 2121-2133 - Brian Schiffer, Amit Burstein, William J. Kaiser:
An active charge cancellation system for switched-capacitor sensor interface circuits. 2134-2138 - Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi:
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. 2139-2147 - Akira Tanabe, Masaaki Soda, Yasushi Nakahara, Takao Tamura, Kazuyoshi Yoshida, Akio Furukawa:
A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier. 2148-2153 - Tod Paulus, Shyam S. Somayajula, Thad A. Miller, Brian Trotter, Kyong Choi, Donald A. Kerth:
A CMOS IF transceiver with reduced analog complexity. 2154-2159 - Sergio A. Sanielevici, Kenneth R. Cioffi, Bahman Ahrari, Paul S. Stephenson, David L. Skoglund, Masoud Zargari:
A 900-MHz transceiver chipset for two-way paging applications. 2160-2168 - James Everitt, James F. Parker, Paul Hurst, Dave Nack, Kishan Rao Konda:
A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet. 2169-2177 - Stephen Wu, Behzad Razavi:
A 900-MHz/1.8-GHz CMOS receiver for dual-band applications. 2178-2185 - Patrick Favre, Norbert Joehl, Alexandre Vouilloz, Philippe Deval, Catherine Dehollain, Michel J. Declercq:
A 2-V 600-μA 1-GHz BiCMOS super-regenerative receiver for ISM applications. 2186-2196 - Jungwook Yang, Joongho Choi, Daniel M. Kuchta, Kevin G. Stawiasz, Petar K. Pepeljugoski, Herschel A. Ainspan:
A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology. 2197-2204 - Loke Kun Tan, Jeffrey Putnam, Fang Lu, Lionel J. D'Luna, Dean W. Mueller, Kenneth R. Kindsfater, Kelly B. Cameron, Robindra B. Joshi, Robert A. Hawley, Henry Samueli:
A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder. 2205-2218 - Derek K. Shaeffer, Arvin Shahani, Sunderarajan S. Mohan, Hirad Samavati, Hamid R. Rategh, Maria del Mar Hershenson, Min Xu, C. Patrick Yue, Daniel J. Eddleman, Thomas H. Lee:
A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters. 2219-2231 - Arvin Shahani, Derek K. Shaeffer, Sunderarajan S. Mohan, Hirad Samavati, Hamid R. Rategh, Maria del Mar Hershenson, Min Xu, C. Patrick Yue, Daniel J. Eddleman, Mark A. Horowitz, Thomas H. Lee:
Low-power dividerless frequency synthesis using aperture phase detection. 2232-2239 - Takafumi Yamaji, Hiroshi Tanimoto, Hideyuki Kokatsu:
An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter. 2240-2246 - Jürgen Hauenschild, Dirk Friedrich, Jürgen Herrle, Joachim Krug:
PIN-preamp module and CDR-DMUX constituting a receiver for short-haul links up to 3.5 Gb/s. 2247-2251 - David K. Su, William J. McFarland:
An IC for linearizing RF power amplifiers using envelope elimination and restoration. 2252-2258 - Stephen L. Wong, Sifen Luo:
A 2.7-5.5 V, 0.2-1 W BiCMOS RF driver amplifier IC with closed-loop power control and biasing functions. 2259-2264 - Hong Mo Wang:
A 1-V multigigahertz RF mixer core in 0.5-μm CMOS. 2265-2267
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