default search action
Yogesh Singh Chauhan
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j28]Mohammad Zaid, Purnima Kumari, Ahtisham Pampori
, Mohammad Sajid Nazir, Umakant Goyal, Meena Mishra, Yogesh Singh Chauhan:
Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability. IEEE Access 12: 53475-53484 (2024) - [j27]Shubham Kumar
Thermal Effects on Monolithic 3D Ferroelectric Transistors for Deep Neural Networks Performance. Adv. Intell. Syst. 6(8) (2024) - [j26]Mohammad Zaid, Ahtisham Pampori, Mohammad Sajid Nazir, Yogesh Singh Chauhan:
GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance. Microelectron. J. 145: 106129 (2024) - [j25]Mohammad Zaid, Mohammad Sajid Nazir, Raghavendra Dangi, Yogesh Singh Chauhan:
Design and experimental validation of class-F-1 GaN power amplifier using a compact harmonic control unit. Microelectron. J. 149: 106218 (2024) - [c39]Anirban Kar, Florian Klemme, Yogesh Singh Chauhan, Hussam Amrouch:
On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor. IRPS 2024: 1-6 - [c38]Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch:
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction. IRPS 2024: 1-7 - [c37]Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille:
Technology Mapping for Cryogenic CMOS Circuits. ISVLSI 2024: 272-277 - [c36]Ateeb Naseer
Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies. MLCAD 2024: 5:1-5:7 - 2023
- [j24]Shivendra Singh Parihar
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs. IEEE Open J. Circuits Syst. 4: 258-270 (2023) - [j23]Girish Pahwa
Robust Compact Model of High-Voltage MOSFET's Drift Region. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 337-340 (2023) - [j22]Amol D. Gaidhane
A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1634-1642 (2023) - [j21]Neha Bajpai
An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1006-1016 (2023) - [j20]Shubham Kumar
Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2891-2903 (2023) - [j19]Shivendra Singh Parihar
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3089-3102 (2023) - [j18]Swetaki Chatterjee
FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator. IEEE Trans. Emerg. Top. Comput. 11(2): 541-547 (2023) - [j17]Dinesh Rajasekharan
SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks. IEEE Trans. Neural Networks Learn. Syst. 34(9): 5693-5707 (2023) - [c35]Victor M. van Santen, Marcel Walter
Design Automation for Cryogenic CMOS Circuits. DAC 2023: 1-6 - [c34]Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch:
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing. DRC 2023: 1-2 - [c33]Shubham Kumar, Yogesh Singh Chauhan, Hussam Amrouch:
Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration. ICCAD 2023: 1-6 - [c32]Shubham Kumar, Paul R. Genssler, Somaya Mansour, Yogesh Singh Chauhan, Hussam Amrouch:
Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration. VLSI-SoC 2023: 1-6 - [i3]Liu Liu, Shubham Kumar
Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs. CoRR abs/2304.03868 (2023) - [i2]Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni:
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. CoRR abs/2305.01484 (2023) - 2022
- [j16]Wajid Manzoor
Analytical approximation of surface potential and analysis of C-V characteristics of bulk MOSFETs at cryogenic temperatures. Microelectron. J. 129: 105586 (2022) - [j15]Sami Salamin
Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU. IEEE Trans. Computers 71(4): 906-918 (2022) - [j14]Dinesh Rajasekharan
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2107-2114 (2022) - [c31]Raghvendra Dangi
A width-scalable SPICE compact model for GaN HEMTs including self-heating effect. DRC 2022: 1-2 - [c30]Anirban Kar, Swapna Sarker, Avirup Dasgupta, Yogesh Singh Chauhan:
Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes. DRC 2022: 1-2 - [c29]Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan:
Self-Heating characterization and modeling of 5nm technology node FinFETs. DRC 2022: 1-2 - [c28]Shubham Kumar
Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing. ISCAS 2022: 3373-3377 - [c27]Shubham Kumar
A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology. NEWCAS 2022: 504-508 - [c26]Neha Bajpai
A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier. VDAT 2022: 212-221 - [c25]Shubham Kumar
Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing. VLSI-SoC 2022: 1-6 - [c24]Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. VLSI Technology and Circuits 2022: 395-396 - 2021
- [j13]Georgios Zervakis
Impact of NCFET on Neural Network Accelerators. IEEE Access 9: 43748-43758 (2021) - [j12]Neha Bajpai
A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules. IEEE Access 9: 124900-124909 (2021) - [j11]Ravi Goel
Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation. Microelectron. J. 110: 105020 (2021) - [j10]Amol D. Gaidhane
Study of multi-domain switching dynamics in negative capacitance FET using SPICE model. Microelectron. J. 115: 105186 (2021) - [j9]Guilherme Paim
On the Resiliency of NCFET Circuits Against Voltage Over-Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1481-1492 (2021) - [j8]Sami Salamin
PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4299-4309 (2021) - [c23]Om Prakash, Chetan K. Dabhi, Yogesh Singh Chauhan
Transistor Self-Heating: The Rising Challenge for Semiconductor Testing. VTS 2021: 1-7 - 2020
- [j7]Johann Knechtel, Satwik Patnaik
Power Side-Channel Attacks in Negative Capacitance Transistor. IEEE Micro 40(6): 74-84 (2020) - [j6]Dinesh Rajasekharan, Pragya Kushwaha, Yogesh Singh Chauhan
Associative processing using negative capacitance FDSOI transistor for pattern recognition. Microelectron. J. 104: 104877 (2020) - [j5]Hussam Amrouch
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3127-3137 (2020) - [c22]Hussam Amrouch
NCFET to Rescue Technology Scaling: Opportunities and Challenges. ASP-DAC 2020: 637-644 - [c21]Florian Klemme
Cell Library Characterization using Machine Learning for Design Technology Co-Optimization. ICCAD 2020: 162:1-162:9 - [c20]Govind Bajpai, Aniket Gupta, Om Prakash, Girish Pahwa
Impact of Radiation on Negative Capacitance FinFET. IRPS 2020: 1-5 - [i1]Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch:
Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). CoRR abs/2007.03987 (2020)
2010 – 2019
- 2019
- [c19]Chetan Gupta, Ravi Goel, Harshit Agarwal, Chenming Hu, Yogesh Singh Chauhan
BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design. CICC 2019: 1-8 - [c18]Martin Rapp, Sami Salamin, Hussam Amrouch
Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores. DAC 2019: 41 - [c17]Sami Salamin, Martin Rapp, Hussam Amrouch
NCFET-Aware Voltage Scaling. ISLPED 2019: 1-6 - [c16]Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh Chauhan
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications. VLSID 2019: 504-505 - 2018
- [j4]Hussam Amrouch
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance. IEEE Access 6: 52754-52765 (2018) - [c15]Sourabh Khandelwal
Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited). BCICTS 2018: 93-97 - 2017
- [c14]Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs. VLSID 2017: 381-384 - 2016
- [j3]Pragya Kushwaha, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG. Microelectron. J. 56: 171-176 (2016) - [c13]Girish Pahwa
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. ESSCIRC 2016: 49-54 - [c12]Chandan Yadav, Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Yogesh Singh Chauhan
Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence. VLSID 2016: 328-333 - [c11]Chandan Yadav, Amit Agarwal, Yogesh Singh Chauhan
Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor. VLSID 2016: 571-572 - 2015
- [j2]Sourabh Khandelwal
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(8): 1291-1294 (2015) - [c10]Juan Pablo Duarte, Sourabh Khandelwal
BSIM-CMG: Standard FinFET compact model for advanced circuit design. ESSCIRC 2015: 196-201 - 2014
- [c9]Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Harshit Agarwal, Yogesh Singh Chauhan
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications. VLSID 2014: 421-426 - 2013
- [j1]Navid Paydavosi, Sriramkumar Venugopalan, Yogesh Singh Chauhan
BSIM - SPICE Models Enable FinFET and UTB IC Designs. IEEE Access 1: 201-215 (2013) - [c8]Yogesh Singh Chauhan, Sriramkumar Venugopalan, Navid Paydavosi, Pragya Kushwaha, Srivatsava Jandhyala, Juan Pablo Duarte, Shantanu Agnihotri, Chandan Yadav, Harshit Agarwal, Ali M. Niknejad, Chenming Calvin Hu:
BSIM compact MOSFET models for SPICE simulation. MIXDES 2013: 23-28 - 2012
- [c7]Yogesh Singh Chauhan
BSIM - Industry standard compact MOSFET models. ESSCIRC 2012: 30-33 - [c6]Maria-Anna Chalkiadaki, Anurag Mangla, Christian C. Enz, Yogesh Singh Chauhan
Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology. ESSCIRC 2012: 34-37 - 2010
- [c5]Shyam Parthasarathy, Amit Ranjan Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh Singh Chauhan
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications. VLSI Design 2010: 194-199
2000 – 2009
- 2008
- [c4]Yogesh Singh Chauhan
Compact Modeling of Suspended Gate FET. VLSI Design 2008: 119-124 - 2007
- [c3]Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann, Adrian Mihai Ionescu:
Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications. Nano-Net 2007: 8 - [c2]Yogesh Singh Chauhan
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. VLSI Design 2007: 177-182 - 2006
- [c1]Yogesh Singh Chauhan
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. ISQED 2006: 109-114
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 21:23 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: