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ICCAD 2020: San Diego, CA, USA
- IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020. IEEE 2020
- Zhiyuan Chen, Yufei Ma, Zhongfeng Wang:
Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks. 90:1-90:7 - Nitthilan Kanappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande:
SETGAN: Scale and Energy Trade-off GANs for Image Applications on Mobile Platforms. 23:1-23:9 - Xiaotian Dai
, Shuai Zhao, Yu Jiang, Xun Jiao, Xiaobo Sharon Hu
Fixed-Priority Scheduling and Controller Co-Design for Time-Sensitive Networks. 99:1-99:9 - Kunal Agrawal, Sanjoy K. Baruah, Zhishan Guo
The Safe and Effective Application of Probabilistic Techniques in Safety-Critical Systems. 24:1-24:9 - Jinjun Xiong
Challenges for Building a Cloud Native Scalable and Trustable Multi-tenant AIoT Platform. 26:1-26:8 - Florian Klemme
Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities. 15:1-15:9 - Bing Li, Ying Wang, Yiran Chen:
HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural Networks. 105:1-105:7 - Gyuyoung Park, Myoungsoo Jung:
Automatic-SSD: Full Hardware Automation over New Memory for High Performance and Energy Efficient PCIe Storage Cards. 57:1-57:9 - Ying Zhu, Grace Li Zhang
Countering Variations and Thermal Effects for Accurate Optical Neural Networks. 152:1-152:7 - Yibo Lin:
GPU Acceleration in VLSI Back-end Design: Overview and Case Studies. 168:1-168:4 - Sheng-Chun Kao, Tushar Krishna:
GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic Algorithm. 44:1-44:9 - Hari Govind V. K.
Word Level Property Directed Reachability. 107:1-107:9 - Sheng-Hao Wang, Yen-Jong Chen, Ting-Chi Wang, Oscar Chen:
An Algorithm for Rule-based Layout Pattern Matching. 33:1-33:8 - Yi-Chen Chang, Hongjia Li, Olivia Chen
ASAP: An Analytical Strategy for AQFP Placement. 134:1-134:7 - Qi Sun
Counteracting Adversarial Attacks in Autonomous Driving. 83:1-83:7 - Duy Thanh Nguyen, Changhong Min, Nhut-Minh Ho
DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System. 47:1-47:8 - Mark Po-Hung Lin
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. 55:1-55:8 - Xuanxiang Huang, Haipeng Che, Liangda Fang, Qingliang Chen, Quanlong Guan
Dynamic Minimization of Bi-Kronecker Functional Decision Diagrams. 131:1-131:9 - Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi:
Modeling Techniques for Logic Locking. 80:1-80:9 - Adam Issa, Valeriy Sukharev, Farid N. Najm
Electromigration Checking Using a Stochastic Effective Current Model. 5:1-5:8 - Chengmo Yang, Patrick Cronin, Agamyrat Agambayev, Sule Ozev, A. Enis Çetin, Alex Orailoglu:
A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration. 8:1-8:9 - Stefanos Laskaridis, Stylianos I. Venieris, Hyeji Kim, Nicholas D. Lane:
HAPI: Hardware-Aware Progressive Inference. 91:1-91:9 - Ecenur Ustun, Chenhui Deng, Debjit Pal
Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. 87:1-87:9 - Debapriya Basu Roy, Tim Fritzmann, Georg Sigl:
Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers. 35:1-35:9 - Nayoung Choi, Jaeha Kim:
Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations. 52:1-52:8 - Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration. 102:1-102:9 - Yukui Luo, Xiaolin Xu:
A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA. 64:1-64:9 - Mohamed Baker Alawieh, Wei Ye, David Z. Pan:
Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk). 12:1-12:8 - Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu
CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. 142:1-142:9 - Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo:
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. 68:1-68:4 - Xing Huang, Youlin Pan, Grace Li Zhang
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips. 29:1-29:8 - Ilias Giechaskiel, Jakub Szefer:
Information Leakage from FPGA Routing and Logic Elements. 63:1-63:9 - Chao Zhang, Khaled Abdelaal, Angel Chen, Xinhui Zhao, Wujie Wen, Xiaochen Guo:
ECC Cache: A Lightweight Error Detection for Phase-Change Memory Stuck-At Faults. 59:1-59:9 - Xiao Shi, Hao Yan, Chuwen Li, Jianli Chen, Longxing Shi, Lei He:
A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis. 7:1-7:8 - Han Zhou, Wentian Jin, Sheldon X.-D. Tan:
GridNet: Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid Networks. 160:1-160:9 - Mahabubul Alam, Abdullah Ash-Saki, Junde Li, Anupam Chattopadhyay, Swaroop Ghosh:
Noise Resilient Compilation Policies for Quantum Approximate Optimization Algorithm. 155:1-155:7 - Seyed Milad Ebrahimipour, Behnam Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, Lesley Shannon:
Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network. 31:1-31:9 - Supratik Chakraborty
On Uniformly Sampling Traces of a Transition System. 108:1-108:9 - Haeyoung Kim
RIMI: Instruction-level Memory Isolation for Embedded Systems on RISC-V. 34:1-34:9 - Saransh Gupta, Justin Morris
THRIFTY: Training with Hyperdimensional Computing across Flash Hierarchy. 27:1-27:9 - Tonmoy Dhar, Kishor Kunal
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). 54:1-54:2 - Sujit Kumar Muduli, Gourav Takhar, Pramod Subramanyan:
HyperFuzzing for SoC Security Validation. 106:1-106:9 - Kai-Chuan Yang, Tao-Chun Yu, Shao-Yun Fang, Teng-Yuan Cheng, Yang-Chun Liu, Cindy Chin-Fang Shen:
Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation. 149:1-149:8 - Xiaopeng Zhang, James P. Shiely, Evangeline F. Y. Young:
Layout Pattern Generation and Legalization with Generative Learning Models. 32:1-32:9 - Yeonhong Park, Seung Yul Lee, Hoon Shin, Jun Heo, Tae Jun Ham, Jae W. Lee:
Unlocking Wordline-level Parallelism for Fast Inference on RRAM-based DNN Accelerator. 103:1-103:9 - Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. 127:1-127:8 - Elbruz Ozen
Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression. 75:1-75:9 - Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
GPU-Accelerated Static Timing Analysis. 147:1-147:9 - Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim
A Fast Learning-Driven Signoff Power Optimization Framework. 161:1-161:9 - Francesco Regazzoni
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-. 141:1-141:6 - Xiaoxuan Yang
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration. 92:1-92:9 - Yu-Chou Lin, Jie-Hong R. Jiang:
Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning. 86:1-86:9 - Yanqing Zhang, Haoxing Ren, Brucek Khailany:
Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk). 166:1-166:5 - Parnian Mokri, Mark Hempstead:
Early-stage Automated Accelerator Identification Tool for Embedded Systems with Limited Area. 115:1-115:8 - Qiaochu Zhang
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. 118:1-118:9 - Haowen Fang, Zaidao Mei, Amar Shrestha, Ziyi Zhao, Yilan Li, Qinru Qiu:
Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs. 62:1-62:9 - Cunxi Yu
FlowTune: Practical Multi-armed Bandits in Boolean Optimization. 130:1-130:9 - Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan:
InterLock: An Intercorrelated Logic and Routing Locking. 78:1-78:9 - Mateus Fogaça, Eder Monteiro, Marcelo Danigno
Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper. 113:1-113:8 - Shengwen Liang, Cheng Liu
DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. 72:1-72:9 - Wen-Hsiang Chang, Li-Yi Lin, Yu-Guang Chen, Mango C.-T. Chao:
Power Distribution Network Generation for Optimizing IR-Drop Aware Timing. 146:1-146:9 - Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim:
Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. 94:1-94:9 - Weiguang Liu, Jinhua Cui
MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDs. 58:1-58:9 - Selma Saidi, Dirk Ziegenbein, Jyotirmoy V. Deshmukh, Rolf Ernst:
EDA for Autonomous Behavior Assurance. 81:1-81:3 - Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. 71:1-71:6 - Hao Chen, Keren Zhu
Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. 18:1-18:8 - Hao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng, Bei Yu:
Hotspot Detection via Attention-based Deep Layout Metric Learning. 16:1-16:8 - Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera:
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. 157:1-157:8 - Mahmood Azhar Qureshi, Arslan Munir
NeuroMAX: A High Throughput, Multi-Threaded, Log-Based Accelerator for Convolutional Neural Networks. 45:1-45:9 - Qi Liu, Wujie Wen, Yanzhi Wang:
Concurrent Weight Encoding-based Detection for Bit-Flip Attack on Neural Network Accelerators. 37:1-37:8 - Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young:
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. 17:1-17:8 - Saurabh Dash, Saibal Mukhopadhyay:
Hessian-Driven Unequal Protection of DNN Parameters for Robust Inference. 76:1-76:9 - Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park:
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. 158:1-158:8 - Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, Cheng-Hong Tsai:
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. 156:1-156:9 - Fan Zhang
CCCS: Customized SPICE-level Crossbar-array Circuit Simulator for In-Memory Computing. 136:1-136:8 - Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. 73:1-73:9 - Tirthak Patel
DisQ: A Novel Quantum Output State Classification Method on IBM Quantum Computers using OpenPulse. 139:1-139:9 - Sarah Amir, Domenic Forte
Adaptable and Divergent Synthetic Benchmark Generation for Hardware Security. 49:1-49:9 - Ting-Ru Lin, Massoud Pedram:
Retiming for High-performance Superconductive Circuits with Register Energy Minimization. 85:1-85:9 - Bentian Jiang, Lixin Liu
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. 20:1-20:9 - Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. 77:1-77:6 - Feng Wang, Liren Zhu
Dual-Output LUT Merging during FPGA Technology Mapping. 132:1-132:9 - Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. 119:1-119:9 - Navyata Gattu, Mohammad Nasim Imtiaz Khan, Asmit De, Swaroop Ghosh:
Power Side Channel Attack Analysis and Detection. 65:1-65:7 - Tyler Sorensen
A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration. 97:1-97:9 - Yen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets:
Symbolic Uniform Sampling with XOR Circuits. 129:1-129:9 - Yinhe Han, Yuxin Yang
DaDu Series - Fast and Efficient Robot Accelerators. 165:1-165:8 - Sumit K. Mandal, Anish Krishnakumar, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras
Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion. 42:1-42:9 - Yuan Xie:
Foreword. 5 - Mahdi Nazemi, Amirhossein Esmaili, Arash Fayyazi, Massoud Pedram:
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning. 89:1-89:9 - Tsung-Wei Huang:
A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD. 169:1-169:2 - Mohamed Shalan, Tim Edwards:
Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper. 110:1-110:6 - Chuangtao Chen
Optimally Approximated and Unbiased Floating-Point Multiplier with Runtime Configurability. 121:1-121:9 - Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany:
Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk). 70:1-70:4 - Qilin Zheng, Xingchen Li
MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block. 104:1-104:9 - Hengyi Liang, Zhilu Wang, Ruochen Jiao, Qi Zhu:
Leveraging Weakly-hard Constraints for Improving System Fault Tolerance with Functional and Timing Guarantees. 101:1-101:9 - Alberto Marchisio
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. 114:1-114:9 - Thomas Grurl, Jürgen Fuß
Considering Decoherence Errors in the Simulation of Quantum Circuits Using Decision Diagrams. 140:1-140:7 - Jorge Castro-Godínez
AxHLS: Design Space Exploration and High-Level Synthesis of Approximate Accelerators using Approximate Functional Units and Analytical Models. 117:1-117:9 - Kai-Shun Hu, Ming-Jen Yang, Tao-Chun Yu, Guan-Chuen Chen:
ICCAD-2020 CAD contest in Routing with Cell Movement : Invited Talk. 69:1-69:4 - Wenqin Huangfu, Krishna T. Malladi, Shuangchen Li, Peng Gu, Yuan Xie:
NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting. 28:1-28:9 - Debdeep Mukhopadhyay:
Faultless to a Fault? The Case of Threshold Implementations of Crypto-systems vs Fault Template Attacks. 66:1-66:9 - Alexandre Truppel, Tsun-Ming Tseng
PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction. 43:1-43:9 - Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li
A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. 46:1-46:7 - Florian Klemme
Cell Library Characterization using Machine Learning for Design Technology Co-Optimization. 162:1-162:9 - Tianyu Wang
ABACUS: Address-partitioned Bloom filter on Address Checking for UniquenesS in IoT Blockchain. 10:1-10:7 - Sujan K. Gonugondla, Ameya D. Patil, Naresh R. Shanbhag:
SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing. 93:1-93:9 - Jinwoo Kim, Gauthaman Murali
RTL-to-GDS Design Tools for Monolithic 3D ICs. 126:1-126:8 - Dewen Zeng, Weiwen Jiang, Tianchen Wang, Xiaowei Xu, Haiyun Yuan, Meiping Huang, Jian Zhuang, Jingtong Hu, Yiyu Shi:
Towards Cardiac Intervention Assistance: Hardware-aware Neural Architecture Exploration for Real-Time 3D Cardiac Cine MRI Segmentation. 40:1-40:8 - An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu:
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. 21:1-21:6 - Kecheng Yang, Ashikahmed Bhuiyan, Zhishan Guo
F2VD: Fluid Rates to Virtual Deadlines for Precise Mixed-Criticality Scheduling on a Varying-Speed Processor. 100:1-100:9 - Timothy J. Baker, John P. Hayes:
Bayesian Accuracy Analysis of Stochastic Circuits. 124:1-124:9 - Marco Siracusa
A CAD-based methodology to optimize HLS code via the Roofline model. 116:1-116:9 - Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu:
DAMO: Deep Agile Mask Optimization for Full Chip Scale. 19:1-19:9 - Yanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar
Hardware Acceleration of Robot Scene Perception Algorithms. 164:1-164:8 - Anup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad, Sri Harsha Gade, Zheng Xu:
Automated Synthesis of Custom Networks-on-Chip for Real World Applications. 41:1-41:9 - Marco Minutoli
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators. 98:1-98:7 - Austin Rovinski, Tutu Ajayi, Minsoo Kim, Guanru Wang, Mehdi Saligane:
Bridging Academic Open-Source EDA to Real-World Usability. 111:1-111:7 - Bochen Tan
Optimal Layout Synthesis for Quantum Computing. 137:1-137:9 - Zhaodong Chen, Mingyu Yan, Maohua Zhu, Lei Deng
fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU. 60:1-60:9 - Rozhin Yasaei, Felix Hernandez, Mohammad Abdullah Al Faruque:
IoT-CAD: Context-Aware Adaptive Anomaly Detection in IoT Systems Through Sensor Association. 9:1-9:9 - Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. 74:1-74:8 - Xiangzhen Zhou
A Monte Carlo Tree Search Framework for Quantum Circuit Transformation. 138:1-138:7 - Cheng Gongye, Hongjia Li, Xiang Zhang, Majid Sabbagh, Geng Yuan, Xue Lin, Thomas Wahl, Yunsi Fei:
New Passive and Active Attacks on Deep Neural Networks in Medical Applications. 39:1-39:9 - S. Rasoul Faraji, Kia Bazargan:
Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs. 123:1-123:9 - Keren Zhu
Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. 133:1-133:9 - Yun-Jhe Jiang, Shao-Yun Fang:
COALA: Concurrently Assigning Wire Segments to Layers for 2D Global Routing. 1:1-1:8 - Debjyoti Bhattacharjee
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. 150:1-150:9 - Wentian Jin, Sheriff Sadiqbatcha, Jinwei Zhang, Sheldon X.-D. Tan:
Full-Chip Thermal Map Estimation for Commercial Multi-Core CPUs with Generative Adversarial Learning. 14:1-14:9 - Qi Zhu, Wenchao Li, Hyoseung Kim
Know the Unknowns: Addressing Disturbances and Uncertainties in Autonomous Systems : Invited Paper. 82:1-82:9 - Yixuan Wang
Energy-Efficient Control Adaptation with Safety Guarantees for Learning-Enabled Cyber-Physical Systems. 22:1-22:9 - Zhenge Jia
Personalized Deep Learning for Ventricular Arrhythmias Detection on Medical loT Systems. 38:1-38:9 - Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. 125:1-125:7 - Jiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan:
DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints. 143:1-143:9 - Run-Yi Wang, Yao-Wen Chang:
Routability-Aware Pin Access Optimization for Monolithic 3D Designs. 2:1-2:6 - Michael Bedford Taylor:
Your Agile Open Source HW Stinks (Because It Is Not a System). 95:1-95:6 - Robert Wille, Stefan Hillmich
JKQ: JKU Tools for Quantum Computing. 154:1-154:5 - Mohammadamir Kavousi, Liang Chen, Sheldon X.-D. Tan:
Electromigration Immortality Check considering Joule Heating Effect for Multisegment Wires. 6:1-6:8 - Steven Beland, Isaac Chang, Alexander Chen, Matthew Moser, James L. Paunicka, Douglas Stuart, John Vian, Christina Westover, Huafeng Yu:
Towards Assurance Evaluation of Autonomous Systems. 84:1-84:6 - Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin
Overview of 2020 CAD Contest at ICCAD. 67:1-67:3 - Rongjian Liang
Routing-Free Crosstalk Prediction. 163:1-163:9 - Ali Heydari Gorji, Siavash Rezaei, Mahdi Torabzadehkashi, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
HyperTune: Dynamic Hyperparameter Tuning for Efficient Distribution of DNN Training Over Heterogeneous Systems. 88:1-88:8 - Ann Franchesca Laguna
Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping. 56:1-56:9 - Chen Wang, Weihua Xiao, John P. Hayes, Weikang Qian:
Exploring Target Function Approximation for Stochastic Circuit Minimization. 122:1-122:9 - Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li:
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. 159:1-159:8 - Necati Uysal
DP-MAP: Towards Resistive Dot-Product Engines with Improved Precision. 151:1-151:9 - Kangjun Bai, Lingjia Liu, Zhou Zhou, Yang Yi:
Detection Through Deep Neural Networks: A Reservoir Computing Approach for MIMO-OFDM Symbol Detection. 30:1-30:7 - Han Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Houman Homayoun:
Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks. 36:1-36:9 - Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu:
A Customized Graph Neural Network Model for Guiding Analog IC Placement. 135:1-135:9 - Durba Chatterjee
PUF-G: A CAD Framework for Automated Assessment of Provable Learnability from Formal PUF Representations. 48:1-48:9 - Ying Zhang, Zhiqiang Zhao, Zhuo Feng:
SF-GRASS: Solver-Free Graph Spectral Sparsification. 148:1-148:8 - Anuj Dubey, Rosario Cammarota, Aydin Aysu:
BoMaNet: Boolean Masking of an Entire Neural Network. 51:1-51:9 - Burin Amornpaisannon, Andreas Diavastos
Laser Attack Benchmark Suite. 50:1-50:9 - Wen Wen
Accelerating 3D Vertical Resistive Memories with Opportunistic Write Latency Reduction. 25:1-25:8 - Inga Abel, Helmut Graeb:
Structural Synthesis of Operational Amplifiers Based on Functional Block Modeling. 53:1-53:6 - Zhixin Pan, Jennifer Sheldon, Prabhat Mishra
Test Generation using Reinforcement Learning for Delay-based Side-Channel Analysis. 109:1-109:7 - Yihang Yang, Jiayuan He, Rajit Manohar:
Dali: A Gridded Cell Placement Flow. 145:1-145:9 - M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design. 3:1-3:8 - Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag:
Fundamental Limits on the Precision of In-memory Architectures. 128:1-128:9 - Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen:
Fast IR Drop Estimation with Machine Learning : Invited Paper. 13:1-13:8 - Nikita Acharya, Samah Mohamed Saeed:
A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers. 153:1-153:9 - Sai Surya Kiran Pentapati, Kyungwook Chang, Vassilios Gerousis, Rwik Sengupta, Sung Kyu Lim
Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs. 4:1-4:9 - Kimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures. 79:1-79:9 - Mojan Javaheripi, Mohammad Samragh, Gregory Fields, Tara Javidi
CleaNN: Accelerated Trojan Shield for Embedded Neural Networks. 11:1-11:9 - Kishor Kunal, Jitesh Poojary
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. 120:1-120:8 - Xiaofan Zhang, Hanchen Ye
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator. 61:1-61:9 - Anthony Agnesina, Kyungwook Chang, Sung Kyu Lim
VLSI Placement Parameter Optimization using Deep Reinforcement Learning. 144:1-144:9 - Chen Zhao, Zhenya Zhou, Dake Wu:
Empyrean ALPS-GT: GPU-accelerated Analog Circuit Simulation. 167:1-167:3 - Tim Ansell
The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : lnvited Paper. 112:1-112:8 - Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
Agile SoC Development with Open ESP : Invited Paper. 96:1-96:9
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