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Himanshu Thapliyal
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- affiliation: University of Tennessee, Knoxville, TE, USA
- affiliation (former): University of South Florida, Tampa, FL, USA
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2020 – today
- 2024
- [j64]Tyler Cultice
, Himanshu Thapliyal
Vulnerabilities and Attacks on CAN-Based 3D Printing/Additive Manufacturing. IEEE Consumer Electron. Mag. 13(1): 54-61 (2024) - [j63]Md. Saif Hassan Onim
A Review of Context-Aware Machine Learning for Stress Detection. IEEE Consumer Electron. Mag. 13(4): 10-16 (2024) - [j62]Jun-Cheng Chin
CAN Bus: The Future of Additive Manufacturing (3D Printing). IEEE Consumer Electron. Mag. 13(5): 23-29 (2024) - [j61]Md. Saif Hassan Onim
Utilizing Machine Learning for Context-Aware Digital Biomarker of Stress in Older Adults. Inf. 15(5): 274 (2024) - [j60]Bhaskar Gaur
Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1759-1763 (2024) - [c108]Joseph Clark, Himanshu Thapliyal:
Peephole Optimization for Quantum Approximate Synthesis. ISQED 2024: 1-8 - [c107]Md. Saif Hassan Onim, Himanshu Thapliyal:
Predicting Stress in Older Adults with RNN and LSTM from Time Series Sensor Data and Cortisol. ISVLSI 2024: 300-306 - [c106]Milad Tanavardi Nasab, Wu Yang, Himanshu Thapliyal:
Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB. ISVLSI 2024: 469-474 - [c105]Tamonash Bhattacharyya, Akanksha Lohia, Prasun Ghosal, Himanshu Thapliyal:
WAFER: Wearable, Ambient-Aware Adversarial Fall Event Detection System Using a RISC-V SoC Architecture. ISVLSI 2024: 527-532 - [c104]Sounak Bhowmik, Himanshu Thapliyal:
Quantum Machine Learning for Anomaly Detection in Consumer Electronics. ISVLSI 2024: 544-550 - [c103]Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal:
Residue Number System (RNS) Based Distributed Quantum Addition. ISVLSI 2024: 595-600 - [c102]Tyler Cultice, Md. Saif Hassan Onim, Annarita Giani, Himanshu Thapliyal:
Anomaly Detection for Real-World Cyber-Physical Security Using Quantum Hybrid Support Vector Machines. ISVLSI 2024: 619-624 - [c101]Sounak Bhowmik, Himanshu Thapliyal:
Transfer Learning Based Hybrid Quantum Neural Network Model for Surface Anomaly Detection. ISVLSI 2024: 634-639 - [c100]Joseph Clark, Elijah Raffel, Himanshu Thapliyal:
Automated Generation of Dual Rail Adiabatic Gates from Binary Decision Diagrams. ISVLSI 2024: 809-811 - [c99]Himanshu Thapliyal, Jürgen Becker:
Message from the General Chairs; ISVLSI 2024. ISVLSI 2024: xxvi-xxvii - [c98]Travis S. Humble, Himanshu Thapliyal:
Message from the Quantum Computing Workshop Chairs; ISVLSI 2024. ISVLSI 2024: xxx - [i41]Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal:
Residue Number System (RNS) based Distributed Quantum Addition. CoRR abs/2406.05294 (2024) - [i40]Bhaskar Gaur, Himanshu Thapliyal:
Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing. CoRR abs/2406.07486 (2024) - [i39]Bhaskar Gaur, Travis S. Humble, Himanshu Thapliyal:
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing. CoRR abs/2408.00927 (2024) - [i38]Bhaskar Gaur, Edgard Muñoz-Coreas, Himanshu Thapliyal:
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n-1) Adder. CoRR abs/2408.01002 (2024) - [i37]Sounak Bhowmik, Himanshu Thapliyal:
Quantum Machine Learning for Anomaly Detection in Consumer Electronics. CoRR abs/2409.00294 (2024) - [i36]Tyler Cultice, Md. Saif Hassan Onim, Annarita Giani, Himanshu Thapliyal:
Anomaly Detection for Real-World Cyber-Physical Security using Quantum Hybrid Support Vector Machines. CoRR abs/2409.04935 (2024) - [i35]Joseph Clark, Himanshu Thapliyal:
Peephole Optimization for Quantum Approximate Synthesis. CoRR abs/2409.06020 (2024) - [i34]Joseph Clark, Travis S. Humble, Himanshu Thapliyal:
GTQCP: Greedy Topology-Aware Quantum Circuit Partitioning. CoRR abs/2410.02901 (2024) - [i33]Bhaskar Gaur, Himanshu Thapliyal:
Crosstalk Attack Resilient RNS Quantum Addition. CoRR abs/2410.23217 (2024) - 2023
- [j59]Faruk Lawal Ibrahim Dutsinma, Debajyoti Pal
Personality is to a Conversational Agent What Perfume is to a Flower. IEEE Consumer Electron. Mag. 12(6): 20-26 (2023) - [j58]Debajyoti Pal
What affects the usage of artificial conversational agents? An agent personality and love theory perspective. Comput. Hum. Behav. 145: 107788 (2023) - [j57]Tyler Cultice
A Novel Hierarchical Security Solution for Controller-Area-Network-Based 3D Printing in a Post-Quantum World. Sensors 23(24): 9886 (2023) - [j56]Zachary Kahleifeh, Himanshu Thapliyal
Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security. IEEE Trans. Consumer Electron. 69(1): 1-8 (2023) - [c97]Md. Saif Hassan Onim
CASD-OA: Context-Aware Stress Detection for Older Adults with Machine Learning and Cortisol Biomarker. ACM Great Lakes Symposium on VLSI 2023: 103-108 - [c96]Bhaskar Gaur
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder. ACM Great Lakes Symposium on VLSI 2023: 125-130 - [c95]Tyler Cultice, Joseph Clark, Himanshu Thapliyal
Lightweight Hierarchical Root-of-Trust Framework for CAN-based 3D Printing Security. ACM Great Lakes Symposium on VLSI 2023: 215-216 - [c94]Bhaskar Gaur
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing. ACM Great Lakes Symposium on VLSI 2023: 427-431 - [c93]Joseph Clark
TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits. ACM Great Lakes Symposium on VLSI 2023: 587-592 - [c92]Joseph Clark, Travis S. Humble, Himanshu Thapliyal:
GTQCP: Greedy Topology-Aware Quantum Circuit Partitioning. QCE 2023: 739-744 - [e3]Himanshu Thapliyal, Ronald F. DeMara, Inna Partin-Vaisband, Srinivas Katkoori:
Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023. ACM 2023 [contents] - [i32]Tyler Cultice, Himanshu Thapliyal
Vulnerabilities and Attacks on CAN-Based 3D Printing/Additive Manufacturing. CoRR abs/2301.12235 (2023) - 2022
- [j55]Zachary Kahleifeh, Himanshu Thapliyal
Adiabatic Logic Based Energy-Efficient Security for Smart Consumer Electronics. IEEE Consumer Electron. Mag. 11(1): 57-64 (2022) - [j54]Wu Yang, Himanshu Thapliyal
Approximate Adiabatic Logic for Low-Power and Secure Edge Computing. IEEE Consumer Electron. Mag. 11(1): 88-94 (2022) - [j53]Rohani Rohan
Humans in the Loop: Cybersecurity Aspects in the Consumer IoT Context. IEEE Consumer Electron. Mag. 11(4): 78-84 (2022) - [j52]Tyler Cultice
PUF-Based Post-Quantum CAN-FD Framework for Vehicular Security. Inf. 13(8): 382 (2022) - [j51]Carson Labrado, Himanshu Thapliyal
Fortifying Vehicular Security through Low Overhead Physically Unclonable Functions. ACM J. Emerg. Technol. Comput. Syst. 18(1): 8:1-8:18 (2022) - [j50]Amit Degada
2-Phase Adiabatic Logic for Low-Energy and CPA-Resistant Implantable Medical Devices. IEEE Trans. Consumer Electron. 68(1): 47-56 (2022) - [j49]Alberto Cannavò, Fabrizio Lamberti
Guest Editorial Introduction to the Special Section on Immersive Virtual Reality Simulation for Vehicular Technology. IEEE Trans. Veh. Technol. 71(4): 3397-3398 (2022) - [j48]Rajdeep Kumar Nath, Himanshu Thapliyal
Machine Learning Based Stress Monitoring in Older Adults Using Wearable Sensors and Cortisol as Stress Biomarker. J. Signal Process. Syst. 94(6): 513-525 (2022) - [c91]Joseph Clark, Himanshu Thapliyal
Edge Device Based Stress Detection For Older Adults With Cortisol Biomarker. ICCE 2022: 1-4 - [c90]Wu Yang, Amit Degada, Himanshu Thapliyal
Adiabatic Logic-based STT-MRAM Design for IoT. ISVLSI 2022: 235-240 - [c89]Joseph Clark, Himanshu Thapliyal
A Novel Approach to Quantum Circuit Partitioning. ISVLSI 2022: 450-451 - [e2]Ioannis Savidis, Avesta Sasan, Himanshu Thapliyal, Ronald F. DeMara:
GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022. ACM 2022, ISBN 978-1-4503-9322-5 [contents] - [i31]Jun-Cheng Chin, Tyler Cultice, Himanshu Thapliyal
CAN Bus: The Future of Additive Manufacturing (3D Printing). CoRR abs/2211.03506 (2022) - 2021
- [j47]Himanshu Thapliyal
Consumer Technology-Based Solutions for COVID-19. IEEE Consumer Electron. Mag. 10(2): 64-65 (2021) - [j46]Himanshu Thapliyal
Physical Unclonable Function (PUF)-Based Sustainable Cybersecurity. IEEE Consumer Electron. Mag. 10(4): 79-80 (2021) - [j45]Amit Degada, Himanshu Thapliyal
An Integrated TRNG-PUF Architecture Based on Photovoltaic Solar Cells. IEEE Consumer Electron. Mag. 10(4): 99-105 (2021) - [j44]Zachary Kahleifeh, Himanshu Thapliyal
EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices. Sensors 21(22): 7651 (2021) - [j43]S. Dinesh Kumar, Zachary Kahleifeh, Himanshu Thapliyal
Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design. SN Comput. Sci. 2(2): 92 (2021) - [j42]Rajdeep Kumar Nath, Himanshu Thapliyal
Machine Learning-Based Anxiety Detection in Older Adults Using Wristband Sensors and Context Feature. SN Comput. Sci. 2(5): 359 (2021) - [j41]Rajdeep Kumar Nath, Himanshu Thapliyal
A Review of Machine Learning Classification Using Quantum Annealing for Real-World Applications. SN Comput. Sci. 2(5): 365 (2021) - [j40]Himanshu Thapliyal
Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits. Sustain. Comput. Informatics Syst. 29(Part): 100457 (2021) - [j39]Rajdeep Kumar Nath, Himanshu Thapliyal
Smart Wristband-Based Stress Detection Framework for Older Adults With Cortisol as Stress Biomarker. IEEE Trans. Consumer Electron. 67(1): 30-39 (2021) - [j38]Debajyoti Pal
Exploring the Antecedents of Consumer Electronics IoT Devices Purchase Decision: A Mixed Methods Study. IEEE Trans. Consumer Electron. 67(4): 305-318 (2021) - [j37]Himanshu Thapliyal
Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth. IEEE Trans. Emerg. Top. Comput. 9(2): 1045-1056 (2021) - [c88]Amit Degada, Himanshu Thapliyal
2-SPGAL: 2-Phase Symmetric Pass Gate Adiabatic Logic for Energy-Efficient Secure Consumer IoT. ICCE 2021: 1-6 - [c87]Saraju P. Mohanty, Himanshu Thapliyal, Rajnish Bajpai:
Consumer Technologies for Smart Cities to Smart Villages. ICCE 2021: 1 - [c86]Zachary Kahleifeh, Himanshu Thapliyal
Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices. ISVLSI 2021: 314-319 - [c85]Rajdeep Kumar Nath, Himanshu Thapliyal
Wearable Health Monitoring System for Older Adults in a Smart Home Environment. ISVLSI 2021: 390-395 - [c84]Rajdeep Kumar Nath, Himanshu Thapliyal
Quantum Annealing for Automated Feature Selection in Stress Detection. ISVLSI 2021: 453-457 - [c83]Joseph Clark, Rajdeep Kumar Nath, Himanshu Thapliyal
Machine Learning Based Prediction of Future Stress Events in a Driving Scenario. WF-IoT 2021: 455-458 - [c82]Amit Degada, Himanshu Thapliyal
Smart Village: An IoT Based Digital Transformation. WF-IoT 2021: 459-463 - [i30]Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble:
A Review of Machine Learning Classification Using Quantum Annealing for Real-world Applications. CoRR abs/2106.02964 (2021) - [i29]Carson Labrado, Himanshu Thapliyal, Saraju P. Mohanty:
Fortifying Vehicular Security Through Low Overhead Physically Unclonable Functions. CoRR abs/2106.02976 (2021) - [i28]Rajdeep Kumar Nath, Himanshu Thapliyal:
Machine Learning Based Anxiety Detection in Older Adults using Wristband Sensors and Context Feature. CoRR abs/2106.03019 (2021) - [i27]Amit Degada, Himanshu Thapliyal, Saraju P. Mohanty:
Smart Village: An IoT Based Digital Transformation. CoRR abs/2106.03750 (2021) - [i26]Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus:
Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing. CoRR abs/2106.04758 (2021) - [i25]Rajdeep Kumar Nath, Himanshu Thapliyal, Travis S. Humble:
Quantum Annealing for Automated Feature Selection in Stress Detection. CoRR abs/2106.05134 (2021) - [i24]Joseph Clark, Rajdeep Kumar Nath, Himanshu Thapliyal:
Machine Learning Based Prediction of Future Stress Events in a Driving Scenario. CoRR abs/2106.07542 (2021) - [i23]Zachary Kahleifeh, Himanshu Thapliyal:
Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices. CoRR abs/2106.07855 (2021) - [i22]Rajdeep Kumar Nath, Himanshu Thapliyal:
Wearable Health Monitoring System for Older Adults in a Smart Home Environment. CoRR abs/2107.09509 (2021) - 2020
- [j36]Rajdeep Kumar Nath, Himanshu Thapliyal
Machine Learning Based Solutions for Real-Time Stress Monitoring. IEEE Consumer Electron. Mag. 9(5): 34-41 (2020) - [j35]S. Dinesh Kumar, Himanshu Thapliyal
Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices. ACM J. Emerg. Technol. Comput. Syst. 16(3): 34:1-34:18 (2020) - [j34]Yasuhiro Takahashi
Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function. SN Comput. Sci. 1(5): 237 (2020) - [j33]Carson Labrado, S. Dinesh Kumar, Riasad Badhan, Himanshu Thapliyal
Exploration of Solar Cell Materials for Developing Novel PUFs in Cyber-Physical Systems. SN Comput. Sci. 1(6): 313 (2020) - [c81]Himanshu Thapliyal
Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing. ICCD 2020: 5-8 - [c80]Himanshu Thapliyal
Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ. ICCD 2020: 25-28 - [c79]Amit Degada, Himanshu Thapliyal
Harnessing Uncertainty in Photoresistor Sensor for True Random Number Generation in IoT Devices. ICCE 2020: 1-5 - [c78]Rajdeep Kumar Nath, Himanshu Thapliyal
Validating Physiological Stress Detection Model Using Cortisol as Stress Bio Marker. ICCE 2020: 1-5 - [c77]Cole Terrell, Himanshu Thapliyal
Approximate Adder Circuits Using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications. ICCE 2020: 1-4 - [c76]Tyler Cultice, Dan Ionel, Himanshu Thapliyal
Smart Home Sensor Anomaly Detection Using Convolutional Autoencoder Neural Network. iSES 2020: 67-70 - [c75]Himanshu Thapliyal, Saraju P. Mohanty, Rajnish Bajpai:
Technology Innovations for Smart Cities and Smart Villages. iSES 2020: xxiii-xxiv - [c74]Wu Yang, Himanshu Thapliyal
Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing. ISVLSI 2020: 312-315 - [c73]Tyler Cultice, Carson Labrado, Himanshu Thapliyal
A PUF Based CAN Security Framework. ISVLSI 2020: 602-603 - [c72]Zachary Kahleifeh, Himanshu Thapliyal
2-Phase Energy-Efficient Secure Positive Feedback Adiabatic Logic for CPA-Resistant IoT Devices. WF-IoT 2020: 1-5 - [c71]Rajdeep Kumar Nath, Himanshu Thapliyal
PPG Based Continuous Blood Pressure Monitoring Framework for Smart Home Environment. WF-IoT 2020: 1-6 - [i21]Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus:
T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder. CoRR abs/2004.01826 (2020)
2010 – 2019
- 2019
- [j32]Himanshu Thapliyal
Emerging Paradigms in Vehicular Cybersecurity. IEEE Consumer Electron. Mag. 8(6): 81-83 (2019) - [j31]Carson Labrado, Himanshu Thapliyal
Hardware Security Primitives for Vehicles. IEEE Consumer Electron. Mag. 8(6): 99-103 (2019) - [j30]Travis S. Humble
Quantum Computing Circuits and Devices. IEEE Des. Test 36(3): 69-94 (2019) - [j29]Carson Labrado, Himanshu Thapliyal
Design of a Piezoelectric-Based Physically Unclonable Function for IoT Security. IEEE Internet Things J. 6(2): 2770-2777 (2019) - [j28]Himanshu Thapliyal
Design of Quantum Computing Circuits. IT Prof. 21(6): 22-26 (2019) - [j27]Carson Labrado, Himanshu Thapliyal
Use of Thermistor Temperature Sensors for Cyber-Physical System Security. Sensors 19(18): 3905 (2019) - [j26]Edgard Muñoz-Coreas, Himanshu Thapliyal
Quantum Circuit Design of a T-count Optimized Integer Multiplier. IEEE Trans. Computers 68(5): 729-739 (2019) - [j25]S. Dinesh Kumar, Himanshu Thapliyal
EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card. IEEE Trans. Emerg. Top. Comput. 7(2): 281-293 (2019) - [c70]Himanshu Thapliyal
Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery Computing. ACM Great Lakes Symposium on VLSI 2019: 525-530 - [c69]Edgard Muñoz-Coreas, Himanshu Thapliyal
Design of Quantum Circuits for Cryptanalysis and Image Processing Applications. ISVLSI 2019: 360-365 - [c68]Himanshu Thapliyal
Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications. ISVLSI 2019: 414-418 - [c67]Yasuhiro Takahashi
Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function. ISVLSI 2019: 443-446 - 2018
- [j24]Himanshu Thapliyal
Internet of Things-Based Consumer Electronics: Reviewing Existing Consumer Electronic Devices, Systems, and Platforms and Exploring New Research Paradigms. IEEE Consumer Electron. Mag. 7(1): 66-67 (2018) - [j23]Himanshu Thapliyal
Smart Home Environment for Mild Cognitive Impairment Population: Solutions to Improve Care and Quality of Life. IEEE Consumer Electron. Mag. 7(1): 68-76 (2018) - [j22]Edgard Muñoz-Coreas, Himanshu Thapliyal
T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm. ACM J. Emerg. Technol. Comput. Syst. 14(3): 36:1-36:15 (2018) - [j21]S. Dinesh Kumar, Himanshu Thapliyal
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 110-122 (2018) - [c66]Edgard Muñoz-Coreas, Himanshu Thapliyal
T-count Optimized Quantum Circuits for Bilinear Interpolation. IGSC 2018: 1-6 - [c65]Rajdeep Kumar Nath, Rajnish Bajpai, Himanshu Thapliyal
IoT based indoor location detection system for smart home environment. ICCE 2018: 1-3 - [c64]Himanshu Thapliyal:
Panel theme: Energy and cybersecurity constraints on consumer electronics. ICCE 2018: 1 - [c63]Himanshu Thapliyal
Energy-recovery based hardware security primitives for low-power embedded devices. ICCE 2018: 1-6 - [c62]Zach Kahleifeh, S. Dinesh Kumar, Himanshu Thapliyal
Hardware Trojan Detection in Implantable Medical Devices Using Adiabatic Computing. ICRC 2018: 1-6 - [c61]Himanshu Thapliyal
Amazon Echo Enabled IoT Home Security System for Smart Home Environment. iSES 2018: 31-36 - [c60]Rajdeep Kumar Nath, Himanshu Thapliyal
Towards Photoplethysmogram Based Non-Invasive Blood Pressure Classification. iSES 2018: 37-39 - [c59]S. Dinesh Kumar, Carson Labrado, Riasad Badhan, Himanshu Thapliyal
Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices. ISVLSI 2018: 697-702 - [i20]Edgard Muñoz-Coreas, Himanshu Thapliyal:
T-count Optimized Quantum Circuits for Bilinear Interpolation. CoRR abs/1809.09249 (2018) - [i19]Himanshu Thapliyal, Edgard Muñoz-Coreas, T. S. S. Varun, Travis S. Humble:
Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth. CoRR abs/1809.09732 (2018) - 2017
- [j20]Himanshu Thapliyal
Stress Detection and Management: A Survey of Wearable Smart Health Devices. IEEE Consumer Electron. Mag. 6(4): 64-69 (2017) - [j19]S. Dinesh Kumar, Himanshu Thapliyal
Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware. Integr. 58: 369-377 (2017) - [j18]Himanshu Thapliyal
Energy-efficient magnetic 4-2 compressor. Microelectron. J. 67: 1-9 (2017) - [j17]H. V. Jayashree, Himanshu Thapliyal
Efficient Circuit Design of Reversible Square. Trans. Comput. Sci. 29: 33-46 (2017) - [j16]Mozammel H. A. Khan
Automatic synthesis of quaternary quantum circuits. J. Supercomput. 73(5): 1733-1759 (2017) - [c58]Himanshu Thapliyal
UTB-SOI based adiabatic computing for low-power and secure IoT devices. CISRC 2017: 16:1-16:4 - [c57]Himanshu Thapliyal
Low-Power and Secure Lightweight Cryptography Via TFET-Based Energy Recovery Circuits. ICRC 2017: 1-4 - [c56]Carson Labrado, Himanshu Thapliyal
Design of majority logic based approximate arithmetic circuits. ISCAS 2017: 1-4 - [c55]Fazel Sharifi, Himanshu Thapliyal
Energy-efficient magnetic circuits based on nanoelectronic devices. ISCAS 2017: 1-4 - [c54]S. Dinesh Kumar, Himanshu Thapliyal
Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks. iNIS 2017: 117-122 - [c53]Himanshu Thapliyal
Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth. iNIS 2017: 123-128 - [c52]Edgard Muñoz-Coreas, Himanshu Thapliyal
Design of Quantum Circuits for Galois Field Squaring and Exponentiation. ISVLSI 2017: 68-73 - [c51]Himanshu Thapliyal
Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices. ISVLSI 2017: 621-626 - [c50]Vipul Kumar Mishra
Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies. VLSID 2017: 295-300 - [i18]Edgard Muñoz-Coreas, Himanshu Thapliyal:
T-count Optimized Design of Quantum Integer Multiplication. CoRR abs/1706.05113 (2017) - [i17]Edgard Muñoz-Coreas, Himanshu Thapliyal:
Design of Quantum Circuits for Galois Field Squaring and Exponentiation. CoRR abs/1706.05114 (2017) - [i16]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. CoRR abs/1712.02630 (2017) - [i15]Edgard Muñoz-Coreas, Himanshu Thapliyal:
T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm. CoRR abs/1712.08254 (2017) - 2016
- [j15]Fazel Sharifi, Atiyeh Panahi, Hojjat Sharifi, Keivan Navi, Nader Bagherzadeh
Design of quaternary 4-2 and 5-2 compressors for nanotechnology. Comput. Electr. Eng. 56: 64-74 (2016) - [j14]Shalom Greene, Himanshu Thapliyal
A Survey of Affective Computing for Stress Detection: Evaluating technologies in stress detection for better health. IEEE Consumer Electron. Mag. 5(4): 44-56 (2016) - [j13]Saurabh Kotiyal
Design Methodologies for Reversible Logic Based Barrel Shifters. J. Circuits Syst. Comput. 25(2): 1650003:1-1650003:34 (2016) - [j12]Himanshu Thapliyal
Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates. Trans. Comput. Sci. 27: 10-34 (2016) - [j11]Himanshu Thapliyal
Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines. J. Supercomput. 72(3): 1092-1124 (2016) - [j10]Himanshu Thapliyal
Erratum to: Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines. J. Supercomput. 72(3): 1125 (2016) - [j9]H. V. Jayashree, Himanshu Thapliyal
Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier. J. Supercomput. 72(4): 1477-1493 (2016) - [c49]S. Dinesh Kumar, Himanshu Thapliyal
QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function. CISRC 2016: 24:1-24:4 - [c48]S. Dinesh Kumar, Himanshu Thapliyal
FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices. ICRC 2016: 1-8 - [c47]Prabha Sundaravadivel, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka, Himanshu Thapliyal
Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems. iNIS 2016: 17-22 - [c46]Shalom Greene, Himanshu Thapliyal
IoT-Based Fall Detection for Smart Home Environments. iNIS 2016: 23-28 - [c45]S. Dinesh Kumar, Himanshu Thapliyal
Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic. ISVLSI 2016: 308-313 - [i14]H. V. Jayashree, Himanshu Thapliyal, Hamid R. Arabnia, Vinod Kumar Agrawal:
Ancilla-Input and Garbage-Output Optimized Design of a Reversible Quantum Integer Multiplier. CoRR abs/1608.01228 (2016) - 2015
- [j8]Saurabh Kotiyal
Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomput. 71(7): 2668-2693 (2015) - [c44]Carson Labrado, Himanshu Thapliyal
Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing. iNIS 2015: 107-111 - [c43]Mozammel H. A. Khan
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression. ISVLSI 2015: 297-302 - 2014
- [j7]Saurabh Kotiyal
Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. 45(6): 825-834 (2014) - [j6]Saurabh Kotiyal
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. Trans. Comput. Sci. 24: 37-55 (2014) - [c42]Saurabh Kotiyal
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. VLSID 2014: 545-550 - [c41]H. V. Jayashree, Himanshu Thapliyal
Design of Dedicated Reversible Quantum Circuitry for Square Computation. VLSID 2014: 551-556 - [p1]Himanshu Thapliyal
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. Field-Coupled Nanocomputing 2014: 133-172 - [e1]Marina L. Gavrilova, C. J. Kenneth Tan, Himanshu Thapliyal, Nagarajan Ranganathan:
Transactions on Computational Science XXIV - Special Issue on Reversible Computing. Lecture Notes in Computer Science 8911, Springer 2014, ISBN 978-3-662-45710-8 [contents] - 2013
- [j5]Himanshu Thapliyal
Design of efficient reversible logic-based binary and BCD adder circuits. ACM J. Emerg. Technol. Comput. Syst. 9(3): 17:1-17:31 (2013) - [j4]Himanshu Thapliyal
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. Trans. Comput. Sci. 17: 73-97 (2013) - [j3]Himanshu Thapliyal
Design of Testable Reversible Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1201-1209 (2013) - [c40]Himanshu Thapliyal
A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. MWSCAS 2013: 1067-1070 - 2012
- [c39]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE 2012: 721-726 - [c38]Himanshu Thapliyal
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. ISVLSI 2012: 5-6 - [c37]Saurabh Kotiyal
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI 2012: 207-212 - [c36]Himanshu Thapliyal, Nagarajan Ranganathan:
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. VLSI Design 2012: 13-15 - 2011
- [b1]Himanshu Thapliyal:
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. University of South Florida, Tampa, USA, 2011 - [c35]Himanshu Thapliyal, N. Ranganathan:
A new reversible design of BCD adder. DATE 2011: 1180-1183 - [i13]Himanshu Thapliyal, Nagarajan Ranganathan:
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits. CoRR abs/1101.4222 (2011) - 2010
- [j2]Himanshu Thapliyal
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. 6(4): 14:1-14:31 (2010) - [c34]Himanshu Thapliyal
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. VLSI Design 2010: 235-240
2000 – 2009
- 2009
- [j1]Himanshu Thapliyal
Efficient Reversible Logic Design of BCD Subtractors. Trans. Comput. Sci. 3: 99-121 (2009) - [c33]Himanshu Thapliyal
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. ISCAS 2009: 1815-1818 - [c32]Himanshu Thapliyal
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. ISVLSI 2009: 229-234 - [c31]Himanshu Thapliyal
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516 - 2007
- [c30]Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma:
Partial Reversible Gates(PRG) for Reversible BCD Arithmetic. CDES 2007: 90-94 - [c29]Himanshu Thapliyal
Design of Reversible Sequential Elements With Feasibility of Transistor Implementation. ISCAS 2007: 625-628 - [c28]Himanshu Thapliyal
Designing Efficient Online Testable Reversible Adders With New Reversible Gate. ISCAS 2007: 1085-1088 - [c27]Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma:
Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. PDPTA 2007: 449-452 - [i12]Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma:
Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. CoRR abs/0711.2671 (2007) - [i11]Himanshu Thapliyal, Hamid R. Arabnia, Rajnish Bajpai, Kamal K. Sharma:
Partial Reversible Gates(PRG) for Reversible BCD Arithmetic. CoRR abs/0711.2674 (2007) - 2006
- [c26]Himanshu Thapliyal
The New BCD Subtractor and Its Reversible Logic Implementation. Asia-Pacific Computer Systems Architecture Conference 2006: 466-472 - [c25]Himanshu Thapliyal
Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. AICCSA 2006: 88-92 - [c24]Himanshu Thapliyal
Novel Reversible Multiplier Architecture Using Reversible TSG Gate. AICCSA 2006: 100-103 - [c23]Himanshu Thapliyal
Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures. APCCAS 2006: 418-421 - [c22]Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia:
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. CDES 2006: 36-38 - [c21]Himanshu Thapliyal, Hamid R. Arabnia:
Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. CDES 2006: 64-69 - [c20]Himanshu Thapliyal, Hamid R. Arabnia:
A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications. CDES 2006: 70-76 - [c19]Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia:
Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. CDES 2006: 130-134 - [c18]Himanshu Thapliyal
Design of Novel Reversible Carry Look-Ahead BCD Subtractor. ICIT 2006: 253-258 - [c17]Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. ESA 2006: 160-168 - [c16]Himanshu Thapliyal
Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder. DELTA 2006: 414-417 - [c15]Himanshu Thapliyal
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. VLSI Design 2006: 387-392 - [i10]Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas:
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. CoRR abs/cs/0603088 (2006) - [i9]Himanshu Thapliyal, M. B. Srinivas:
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits. CoRR abs/cs/0603091 (2006) - [i8]Himanshu Thapliyal, M. B. Srinivas:
An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates. CoRR abs/cs/0603092 (2006) - [i7]Himanshu Thapliyal, M. B. Srinivas:
Novel Reversible Multiplier Architecture Using Reversible TSG Gate. CoRR abs/cs/0605004 (2006) - [i6]Himanshu Thapliyal, M. B. Srinivas:
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU. CoRR abs/cs/0609023 (2006) - [i5]Himanshu Thapliyal, M. B. Srinivas:
VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics. CoRR abs/cs/0609028 (2006) - [i4]Himanshu Thapliyal, Hamid R. Arabnia:
Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications. CoRR abs/cs/0609029 (2006) - [i3]Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas:
Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format. CoRR abs/cs/0609036 (2006) - [i2]Himanshu Thapliyal, Mark Zwolinski:
Reversible Logic to Cryptographic Hardware: A New Paradigm. CoRR abs/cs/0610089 (2006) - [i1]Himanshu Thapliyal, Hamid R. Arabnia, A. Prasad Vinod:
Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation. CoRR abs/cs/0610090 (2006) - 2005
- [c14]Himanshu Thapliyal
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Asia-Pacific Computer Systems Architecture Conference 2005: 805-817 - [c13]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture. AMCS 2005: 72-76 - [c12]Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia:
Verilog Coding Style for Efficient Synthesis In FPGA. CDES 2005: 85-90 - [c11]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Design for A Fast And Low Power 2's Complement Multiplier. CDES 2005: 165-167 - [c10]Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison. CSC 2005: 74-77 - [c9]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor. ESA 2005: 60-68 - [c8]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs. ESA 2005: 106-116 - [c7]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Reversible Logic Synthesis of Half, Full and Parallel Subtractors. ESA 2005: 165-181 - [c6]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier. Security and Management 2005: 40-44 - [c5]Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia:
Implementation of A Fast Square In RSA Encryption/Decryption Architecture. Security and Management 2005: 371-374 - 2004
- [c4]Himanshu Thapliyal, Hamid R. Arabnia:
High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 413-416 - [c3]Himanshu Thapliyal, Hamid R. Arabnia:
A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 434-439 - [c2]Himanshu Thapliyal, Hamid R. Arabnia:
A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics. ESA/VLSI 2004: 440-446 - 2003
- [c1]Vishal Verma, Himanshu Thapliyal:
A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics. VLSI 2003: 361-365
Coauthor Index
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