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Improved diagnosis of realistic interconnect shorts

Authors:

J. T. de Sousa,

P. Y. K. CheungAuthors Info & Claims

EDTC '97: Proceedings of the 1997 European conference on Design and Test

Page 501

Published: 17 March 1997 Publication History

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Abstract

Original diagnostic schemes for wire interconnect shorts are proposed. The idea is to use layout extracted realistic shorts and a broader range of short behaviour assumptions to derive the schemes. Results on real examples clearly show the superiority of the new schemes, both in terms of test size and diagnostic resolution.

References

[1]

[1] William H. Kautz. "Testing for Faults in Wiring Networks". IEEE Transactions on Computers, C-23(4):358-353, April 1974.

Digital Library

Google Scholar

[2]

[2] P. Goel and M.T. McMahon. "Electronic Chip in Place Test". In Proc. Int. Test Conference (ITC), pages 83-90, 1982.

Google Scholar

[3]

[3] P.T. Wagner. "Interconect Testing with Boundary Scan". In Proc. Int. Test Conference (ITC), pages 52-57, 1987.

Google Scholar

[4]

[4] A. Hassan, J. Rajski, and V.K. Agarwal. "Testing and Diagnosis of Interconnects using Boundary Scan Architecture". In Proc. Int. Test Conference (ITC), pages 126-137, 1988.

Crossref

Google Scholar

[5]

[5] N. Jarwala and C.W. Yau. "A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects". In Proc. Int. Test Conference (ITC), pages 63-70, 1989.

Crossref

Google Scholar

[6]

[6] C.W. Yau and N. Jarwala. "A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects". In Proc. Int. Test Conference (ITC), pages 71-77, 1989.

Crossref

Google Scholar

[7]

[7] W.T. Cheng, J.L. Lewandowski, and E. Wu. "Diagnosis for Wiring Interconnects". In Proc. Int. Test Conference (ITC), pages 565-571, 1990.

Crossref

Google Scholar

[8]

[8] M.R. Garey, D.S. Stifler, and H.C. So. "An Application of Graph Coloring to Printed Circuit Testing". IEEE Trans. on Circuits and Systems, CAS-23(10):591-599, Oct. 1976.

Google Scholar

[9]

[9] J.L. Lewandowski and V.J. Velasco. "Short Circuit Testing". Technical Report CC8559, AT&T, October 1986.

Google Scholar

[10]

[10] J.T. Sousa, T. Shen, and P.Y.K. Cheung. "Realistic Fault Extraction for Boards". In Proc. European Design and Test Conference (ED&TC), 1996.

Digital Library

Google Scholar

[11]

[11] D. McBean and W.R. Moore. "Testing Interconnects: A Pin Adjacency Approach". In Proc. European Test Conference (ETC), pages 484-490, 1993.

Crossref

Google Scholar

[12]

[12] Mick M.V. Tegethoff. "Defects, Fault Coverage, Yield and Cost in Board Manufacturing". In Proc. Int. Test Conference (ITC), pages 539-547, 1994.

Digital Library

Google Scholar

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Published In

EDTC '97: Proceedings of the 1997 European conference on Design and Test

March 1997

596 pages

ISBN:0818677864

Publisher

IEEE Computer Society

United States

Publication History

Published: 17 March 1997

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EDTC96

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SIGDA

EDTC96: European Design and Test Conference

March 17 - 20, 1997

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