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Clustered speculative multithreaded processors

Published: 01 May 1999 Publication History
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References

[1]
H. Akkary and M.A. Driscoll, "A Dynamic Multithreading Processor", in Pr. 31st. int. Syrup. on Microarchitecture, 1998
[2]
G.Z. Chrysos and J.S. Emer, "Memory Dependence prediction Using Store Sets", in Prec. of the Int. Syrup. on Computer Architecture, pp. 142-153, 1998.
[3]
M.N. Dorojevets and V.G. Oklobdzija, "Multithreaded Decoupled Architecture", Int. J. of High Speed Computing, 7(3), pp. 465-480, 1995.
[4]
P.K. Dubcy, K. O'Brien, K.M. O'Brien and C. Barton, "Single-Program Speculative Multithreading (SPSM) Architecture: Compiler-Assisted Fine-Grained Multithreading", in Prec. of the Int. Conf on Parallel Architectures and Compilation Techniques, pp. 109-121, 1995.
[5]
K. Farkas, P. Chow, N. Jouppi and Z. Vranesic, "The Multicluster Architecture: Reducing Cycle Time Through Partitioning'', in Prec. of the 30th Int. Conf. on Microarchitecture, pp. 149-159, 1997.
[6]
M. Frankiin and G. $ohi, "The Expandable Split Window Paradigm for Exploiting Fine Grain parallelism", in Prec. of the Int. Syrup. on Computer Architecture, pp. 58-67, 1992.
[7]
J. Gonzfilez and A. Gonzfilez, "Memory Address Prediction for Data Speculation", in Prec. of EURO-PAR 97 Workshop on ILl), pp. 1084-1091, 1997
[8]
J. Gonz~dez and A. Gonzfilez, "The Potential of Data Value Speculation to Boost ILP", in Prec. of the 12th Int. Conf on Supercomputing, pp. 21-28, 1998.
[9]
J. GonzbJez and A. Gonzfilez, "Limits of Instruction Level Parallelism with Data Speculation", in Prec. of the VECPAR Conf., pp. 585-598, 1998.
[10]
L. Gwennap, "Digital 21264 Sets New Standard", Microprocessor Report, 10(14), Oct. 1996.
[11]
L. Hammond, M. Willey and K. Olukotun, "Data Speculation Support for a Chip Multiprocessor", in Proc. of Int. Conf. on Architectural Support for Programming Languages and Operating Systems, 1998
[12]
Q. Jacobsen, E. Rotenberg and J.E. Smith, "Path-Based Next Trace Prediction", in Prec. of the 30th Int. Syrup. on Microarchitecture, pp. 14-23, 1997.
[13]
G. A. Kemp and M. Franklin, "PEWs: A Decentralized Dynamic Scheduler for ILP Processing", in Proc. of the Int. Conf. on Parallel Processing, pp. 239-246, 1996.
[14]
I.H. Kazi and D.J. Lilja, "Coarse-Grained Speculative Execution in Shared-Memory Multiprocessors", in Proc. of the 12th Int. Conf. on Supercomputing, pp. 93-100, 1998
[15]
A. Klauser, A. Paithankar and D. Grunwald, "Selective Eager Execution on the PolyPath Architecture", in Proc of the Int. Symp. on Computer Architecture, pp. 250-261,1998.
[16]
V. Krishnan and J. Torrellas, "Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-Multiprocessor", in Proc. of 12th Int. Conf on Supercomputing, pp. 85-92, 1998
[17]
H.M. Lipasti and J.P. Shen, "Exceeding the Dataflow Limit via Value Prediction", in Proc of Int. Syrup. on Microarchitecture, pp. 226-237, 1996.
[18]
S. McFarling, "Combining Branch Predictors", Technical Report #TN-36, Digital Western Research Laboratory, 1993.
[19]
P. Marcuello and A. Gonzfilez, "Control and Data Dependence Speculation in Multithreaded Processors", in Proc. of the Workshop on Multithreaded Execution Anzhitecture and Compilation held in conjuction with HPCA-4, 1998
[20]
P. Marcuello, A. Gonzfilez and J. Tubella, "Speculative Multithreaded Processors", in Proc. of the 12th int. Conf. on Supercomputing, pp., 1998.
[21]
A.Moshovos, S.E. Breach, T.N. Vijaykumar and G.S. Sohi, "Dynamic Speculation and Synchronization of Data Dependences'', in Proc. of Int. Syrup. on Computer Architecture, pp. 181-193, 1997.
[22]
S. Palacharla, N.E Jouppi and J.E. Smith, "Complexity-Effective Superscalar Processor", in Proc. of Int. Syrup. on Computer Architecture, pp. 206-218, 1997.
[23]
E. Rotenberg, Q. Jacobson, Y. Sazeides and J.E. Smith, "Trace Processors", in Proc. of the 30th. Int. Syrup. on Microarchitecture, pp. 138-148, 1997.
[24]
E. Rotenberg, S. Bennet and J.E. Smith, "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching", in Proc. of 29th Int. Syrup. on Microarchitecture, 1996.
[25]
Y. Sazeides, S. Vassiliadis and j.E. Smith, "The Performance Potential of Data Dependence Speculation & Collapsing", in Proc. of the 29th. Int. Syrup. on Microarchitecture, Dec. 1996.
[26]
Y. Sazeides and J.E. Smith, "The Predictability of Data Values'', in Proc. of 3Oth Int. Syrup. on Microarchitecture, 1997.
[27]
G. Sohi, S.E. Breach and T.N. Vijaykumar, "Multiscalar Processors'', in Proc. of the Int. Syrup. on Computer Architecture, pp. 414-425,1995.
[28]
J. Steffan and T Mowry, "The Potential of Using Thread- Level Data Speculation to Facilitate Automatic Parallelization", in Proc. 4th Int. Syrup. on High-Performance Computer Architecture, pp. 2-13, 1998
[29]
J.Y. Tsai and P-C. Yew, "The Superthreaded Architecture: Thread Pipelining with Run-Time Data Dependence Checking and Control Speculation", in Proc. Int. Conf. on Parallel Architectures and Compilation Techniques, pp. 35-46, 1996.
[30]
J. TubeUa and A. Gonzfilez, "Control Speculation in Multithreaded Processors through Dynamic Loop Detection", in Proc. of 4th. Int. Syrup. on High-Performance Computer Architecture (HPCA-4), pp. 14-23, 1998.
[31]
D.M. Tullsen, S.J. Eggers and H.M. Levy, "Simultaneous Muttithreading: Maximizing On-Chip Parallelism", in Proc. of Int. Syrup. on Computer Architecture, pp. 392-403, 1995.
[32]
K. Uht and V. Sindagi, "Disjoint Eager Execution. An Optimal Form of Speculative Execution", in Proc. of the 28th Int. Syrup. on Microarchitecture, 1995.
[33]
S. Vajapeyam and T. Mitra, "Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences", in Proc. of the Int. Syrup. on Computer Architecture, pp. 1-12, 1997.
[34]
S. Wallace, B. Calder and D.M. Tullsen, "Threaded Multiple Path Execution", in Proc. of the Int. Syrup. on Computer Architecture, pp. 238-249, 1998
[35]
K. Wang and M. Franklin, "Highly Accurate Data Value Prediction Using Hybrid Predictors", in Proc of the 30th Int. Syrup. on Microarchitecture, pp. 281-190, 1997.

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                          ICS '99: Proceedings of the 13th international conference on Supercomputing
                          June 1999
                          509 pages
                          ISBN:158113164X
                          DOI:10.1145/305138
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                          Published: 01 May 1999

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                          1. clustered processors
                          2. control-flow speculation
                          3. data dependance speculation
                          4. data value speculation
                          5. dynamically scheduled processors
                          6. simultaneous multithreaded processors

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                          ICS '99 Paper Acceptance Rate 57 of 180 submissions, 32%;
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                          • (2023)Performance Evaluation on Parallel Speculation-Based Construction of a Binary Search TreeInternational Journal of Networked and Distributed Computing10.1007/s44227-023-00013-w11:2(88-111)Online publication date: 8-Nov-2023
                          • (2022)Parallel Binary Search Tree Construction Inspired by Thread-Level Speculation2022 23rd ACIS International Summer Virtual Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD-Summer)10.1109/SNPD-Summer57817.2022.00021(74-81)Online publication date: Jul-2022
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                          • (2019)Shelving a Code Block for Thread-Level Speculation2019 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD)10.1109/SNPD.2019.8935751(427-434)Online publication date: Jul-2019
                          • (2018)Design Space Exploration for Implementing a Software-Based Speculative Memory SystemInternational Journal of Software Innovation10.4018/IJSI.20180401046:2(37-49)Online publication date: 1-Apr-2018
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