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Elbrus-8S

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Elbrus-8S
Performance
Max. CPU clock rate1.3 GHz
Architecture and classification
Instruction setElbrus 2000
Physical specifications
Cores
  • 8
History
PredecessorElbrus-4S
SuccessorElbrus-16S
Elbrus-8SV[1][2]
Performance
Max. CPU clock rate1.5 GHz
Architecture and classification
Instruction setElbrus 2000
Physical specifications
Cores
  • 8
History
PredecessorElbrus-4S
SuccessorElbrus-16S
Elbrus-8S

The Elbrus-8S (Template:Lang-ru) is a Russian 28 nanometer 8-core microprocessor developed by Moscow Center of SPARC Technologies (MCST). The first prototypes were produced by the end of 2014 and serial production started in 2016.[3] The Elbrus-8S is to be used in servers and workstations.[4] The processor's architecture allows support of up to 32 processors on a single server motherboard.[5][6]

In 2018 MCST announced plans to produce the Elbrus-8SV, an upgraded version of the 8C with doubled performance. The CPU can process 576 Gflops and has a frequency of 1.5 GHz, as well as DDR4 support instead of DDR3.[1][2] Engineering samples were already completed in Q3 2017.[7] Development was completed in 2019[8] and its fabrication started in 2020.

In 2021 the processor was offered to Sberbank, Russia's largest bank, for evaluation in light of a potential use for some of the company's hardware needs. The evaluation had a negative outcome, as the functional requirements were not met.[9]

Supported operating systems

The Elbrus-8S and -SV processors support binary compatibility with Intel x86 and x86-64 processors via runtime binary translation.[2] The documentation suggests that the processors can run Windows XP and Windows 7.[2] The processors can also run a Linux kernel based OS compiled for Elbrus.

Elbrus Elbrus-8S information

Production start 2014 (samples), 2015 (for data-servers)
Cores 8
Computer architecture VLIW, Elbrus (proprietary, closed) version 4, 64-bit
Tech. node 28 nm, TSMC process
Clock rate 1.3 GHz
Cache
  • L1 caches per core: 128 KB for instructions (1 port) + 64 KB for data (4 ports)
  • L2 cache per core: 512 KB, 1 port
  • L3 cache, shared across cores: 16 MB, 4 banks 1 port each
Integrated memory controller DDR3-1600, 4 72-bit channels (with ECC)
Peak performance per CPU, Gflops 125 for DP or 250 for SP
Supported programming platforms C, C++, Java, Fortran 77, Fortran 90
Performance 250 Gflops

Elbrus Elbrus-8SV information

Production start 2018 Q4[10]
Cores 8
Computer architecture VLIW, Elbrus (proprietary, closed) version 5, 64-bit
Tech. node 28 nm, TSMC process
Clock rate 1.5 GHz
Cache
  • L1 caches per core: 64KB data + 128KB instructions
  • L2 cache 512 KB in each core, 4 MB total
  • L3 cache, 16 MB per processor
Integrated memory controller 4 channel DDR4-2400 registered as ECC, to 68.3 GB/s

64 GB per processor, 1 TB address space

Peak performance per CPU, Gflops 288 for DP or 576 for SP
Operating conditions −60...+85 °C, −40...+90 °C
Performance 576 Gflops

References

  1. ^ a b "Руководство по эффективному программированию на платформе «Эльбрус» — Документация Руководство по эффективному программированию на платформе «Эльбрус» 1.0". ftp.altlinux.org. Retrieved 1 June 2020.
  2. ^ a b c d Cutress, Ian (1 June 2020). "Russia's Elbrus 8CB Microarchitecture: 8-core VLIW on TSMC 28nm". www.anandtech.com. Retrieved 1 June 2020.
  3. ^ "The Central processor "Elbrus-8S" (TUGI.431281.016)". Retrieved 16 May 2018.
  4. ^ "Elbrus 8C mit acht Kernen soll 250 GFlops erreichen" [Elbrus 8S with eight cores should reach 250 GFlops] (in German). Golem.de. 14 July 2014. Retrieved 16 May 2018.
  5. ^ A pilot batch of 8-core processors Elbrus-8S started in manufacture Archived 23 May 2015 at the Wayback Machine
  6. ^ New Elbrus-8C processor could usher in a new level of computing speed
  7. ^ "Elbrus 8SV data". Retrieved 16 May 2018.
  8. ^ В Минпроторге заявили о создании российского процессора "Эльбрус-8СВ"
  9. ^ Shilov, Anton (24 December 2021). "Russian-Made Elbrus CPUs Fail Trials, 'A Completely Unacceptable Platform'". Tom's Hardware. Retrieved 13 March 2023.
  10. ^ "Russian Microprocessors of the Elbrus Architecture Series for Servers and Supercomputers" (PDF). Retrieved 16 May 2018.