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FDRA Framework for a hybrid system with RISC-V and CGRA, including:

1. CGRA-MG: SoC modeling

2. App-Compiler: LLVM-based DFG generator (Another choice is MLIR based ADORA-Compiler)

3. CGRA-Compiler: CGRA mapper. (Has been integrated in ADORA-Compiler)

4. Bechmarks: C programs with target loop kernel annotated

1. copy this repo to the chipyard/generators/ directory

2. Add the following configuration in the chipyard/build.sbt file

lazy val chipyard = (project in file("generators/chipyard"))
  .dependsOn(
    ...
    fdra
)

lazy val fdra = (project in file("generators/fdra/cgra-mg"))
  .dependsOn(testchipip, rocketchip)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(chiselTestSettings)
  .settings(commonSettings)

3. copy config file to chipyard

cd chipyard/generators/fdra
./scripts/setup-paths.sh

1. build verilog

source env.sh
cd generators/fdra
./scripts/build-verilog.sh

2. build simulator based on Verilator

./scripts/build-verilator.sh

Download LLVM-10.0.0 and build

Set LLVM env

Using the script build.sh in this app-compiler directory. The internal path should be changed.

./build.sh

Using the script build.sh

cd cgra-compiler
./build.sh

Using the script run.sh

./run.sh

Change the benchmark file path as you need. The generated result files are in the same directory as the benchmark.

Automatically generate with CGRA Compiler, or

Manually replace the target loop kernel with CGRA call function and binding codes generated by CGRA Mapper

1. copy the application file to generators/fdra/software/tests

2. add the application in the Makefile

3. compile with the build.sh file.

cd generators/fdra
./scripts/run-verilator.sh app-name