Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

EPFL logic synthesis benchmarks

OpenMPW run repository. Technology: SG13CMOS Testfield: T594

Tiny QERV Risc-V SoC for TinyTapeout

Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project

Collection of different communication methods for chip mulitprocessors

For contributions of Chisel IP to the chisel community.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Home of the open-source EDA course.

This repository contains all code, scripts, diagrams, and notes from the RISC-V tutorial series on the YouTube Channel

A FABulous FPGA utilizing the Panamax padframe

Parametrized RTL benchmark suite

Agile Hardware Design Course

TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)

A 32-bit RISC-V soft processor

CV32E40P Integration for Amaranth

This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop

Experimental 4x8 configuration for Tiny Tapeout IHP

Snitch RISC‑V (RV32) integer core implemented with LibreLane on IHP SG13G2 (130 nm)

Universal Memory Interface (UMI)

Coplanar Antenna with height-adjustabke off chip reflector!

mWATTBAT: The open source Radar Chip

An electromagnetic field computation program