Tags: Digilent/vivado-boards
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Update copyright years for 2025 release to XilinxBoardStore
Files from this commit were released to XilinxBoardStore master branc… …h on 3/8/2022
gzu-5ev: fixing DDR4 dynamic init property causing silent FSBL boot f… …ailure Setting PSU__DDRC__DDR4_ADDR_MAPPING to 1 will cause the FSBL to enter a code segment with a memory violation bug and undefined behavior. Incremented board file minor rev to 1.1 and it superseeds 1.0.