VHDL 2008/93/87 simulator

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

SpiceBind – spice inside HDL simulator

Python script to generate AXI Lite VHDL slave code with customizable register count. Includes OSVVM testbench for basic functionality simulation.

Ada-to-VHDL compiler

The new Windows Terminal and the original Windows console host, all in the same place!

Network Development Kit (NDK) for FPGA cards with example application

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

A tiny Open POWER ISA softcore written in VHDL 2008

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VHDL compiler and simulator

OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break er…

OSVVM submodule for Co-simulation features

The Tcl Core. (Mirror of core.tcl-lang.org)

A interactive showcase of all the projects waiting for your contribution at Hacktoberfest 2022. You want to publish your projects to the contributors of Hacktoberfest? Contributions to this reposit…

Packages that implement OSVVM's model independent transactions and other shared verification component support packages. Required for all OSVVM verification components. AddressBusTransactionPkg - A…

OSVVM Documentation

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

A translation of the Xilinx XPM library to VHDL for simulation purposes

Turn Junit XML reports into self contained HTML reports

Code generation tool for control and status registers

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Various projects for the Nexys4DDR board from Digilent

Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.

Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.

A huge VHDL library for FPGA and digital ASIC development

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation

A JSON library implemented in VHDL.