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11 stars written in Verilog
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3-stage RV32IMACZb* processor with debug

Verilog 936 68 Updated Oct 9, 2025

Verilog I2C interface for FPGA implementation

Verilog 646 188 Updated Feb 27, 2025

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilog 585 78 Updated Oct 7, 2025

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Verilog 325 52 Updated Jan 23, 2022

An attempt to recreate the RP2040 PIO in an FPGA

Verilog 303 32 Updated Jun 6, 2024

FPGA display controller with support for VGA, DVI, and HDMI.

Verilog 240 33 Updated Mar 9, 2020

SystemVerilog synthesis tool

Verilog 213 28 Updated Mar 10, 2025

OpenHT FPGA design

Verilog 35 6 Updated Jun 24, 2024

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Verilog 34 5 Updated Oct 15, 2018

Repository of Verilog code for Make:FPGA book Chapters 2 & 3.

Verilog 30 10 Updated Apr 1, 2016

Conway's Game of Life in FPGA

Verilog 30 Updated Apr 30, 2020