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11
stars
written in Verilog
Clear filter
Verilog I2C interface for FPGA implementation
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
An attempt to recreate the RP2040 PIO in an FPGA
FPGA display controller with support for VGA, DVI, and HDMI.
Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm
Repository of Verilog code for Make:FPGA book Chapters 2 & 3.