RTLMeter benchmark suite

CRCat: Complex Rational Catalog of all Possible RLC Networks of up to and Including Five Elements

Manage headless displays with Xvfb (X virtual framebuffer)

RTL logic synthesis

Universal Memory Interface (UMI)

TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)

A SystemVerilog language server based on the Slang parser and library.

TensorZero is an open-source stack for industrial-grade LLM applications. It unifies an LLM gateway, observability, optimization, evaluation, and experimentation.

An open-source resistive random access memory (RRAM) compiler based on OpenRAM.

Evaluating accuracy on quantized DNNs using RRAM as weight storage

A 28-page detailed study guide for the Princeton course "Networks: Friends, Money, and Bytes" (ELE 381/COS 381). Also useful for "Networked Life: 20 Questions and Answers" textbook by Mung Chiang

Measurements and simulations of nMOS test device for EE312 at Stanford University

A 28-page detailed study guide for the Princeton course "Computer Architecture" (ELE 475/COS 475). Covers most topics in H&P5 as well.

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

GPU-based logic synthesis tool

Scots Army Knife for electronics

Python wrapper to interact with TCL command line interfaces

Kythe is a pluggable, (mostly) language-agnostic ecosystem for building tools that work with code.

ADC Performance Survey (ISSCC & VLSI Circuit Symposium)

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

An open source CPU design and verification platform for academia

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Copilot Chat extension for VS Code

UNSUPPORTED INTERNAL toolchain builds

Functional verification project for the CORE-V family of RISC-V cores.

wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.