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goatgate/README.md
  • 👋 Hi, I’m sriram
  • 👀 I’m interested in Eda tools, Circuit Design and Compilers
  • 🌱 I’m currently learning python,tcl and verilog
  • 💞️ I’m looking to collaborate on creating better opensource eda tools
  • 📫 How to reach me sriram.nimmala@icloud.com
  • 😄 Pronouns: He/Him
  • ⚡ Fun fact: Verilog was made opensource in 1991

Pinned Loading

  1. MSDAP MSDAP Public

    A low power dsp processor

  2. serdes serdes Public

    RTL implementation of SerDes

    C 2

  3. formal-verification-zipcpu formal-verification-zipcpu Public

    a series of formal verification exercises done based on the resources provided in zipcpu courseware

    Verilog

  4. sta-automation sta-automation Public

    automation of sdc generation and yosys synthesis using python and makefile

    Verilog

  5. fifo-verilog fifo-verilog Public

    Python

  6. uart uart Public

    Makefile