GitHub - tednological/FPGANNinVHDL: Creating a neural network for synthesis in VHDL

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
Sig_ROM.vhdl		Sig_ROM.vhdl
Weight_Memory.vhdl		Weight_Memory.vhdl
config_pkg.vhdl		config_pkg.vhdl
math_helpers.vhdl		math_helpers.vhdl
neuron.vhdl		neuron.vhdl
relu.vhdl		relu.vhdl

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Creating a neural network for synthesis in VHDL

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VHDL 100.0%