ROUTER is a device that connects two or more networks (or computer LANs) and forwards data packets between computer networks (or from Source Server Network to Destination Client Network). It is an OSI layer 3 routing device. Router 1x3 has one ingress and three egress . As the definition suggests, the packet from a source network is routed to one of the destination networks.

The Packet consists of 3 parts i.e. Header, Payload and Parity such that each ID of 8 bits width and the length of the payload can be extended between 1 byte to 63 bytes.

The packet header contains two fields Destination Address and Payload Length.

• Destination Address: The destination address of the packet is of 2 bits. The router drives the packets to respective ports based on the destination address of the packets. Each output port has 2-bit unique port address. If the destination address of the packet matches the port address, then the router drives the packet to the output port. The address "3" is invalid.
  
• Payload Length: The length of the data is 6 bits. It specifies the number of data bytes. A packet can have a minimum data size of 1 byte and a maximum size of 63 bytes.
  
  • If Length = 1, it means the data length is 1 byte.
    
  • If Length = 63, it means the data length is 63 bytes.
    

Payload is the data information. Data should be in terms of bytes.

This field contains the security check of the packet. It is calculated as bitwise parity over the header and payload bytes of the packet.

Characteristics:

• TestBench Note:
  • All input signals are active high except active low reset and are synchronized to the falling edge of the clock. This is because the DUT router is sensitive to the rising edge of the clock. Therefore, in the testbench, driving input signals on the falling edge ensure adequate setup and hold time. But in the SystemVerilog/UVM-based testbench, the clocking block can be used to drive the signals on the positive edge of the clock itself and thus avoids metastability.
    
  • The packet_valid signal is asserted on the same clock edge when the header byte is driven onto the input data bus.
    
  • Since the header byte contains the address, this tells the router to which output channel the packet should be routed (data_out_0, data_out_1, data_out_2).
    
  • Each subsequent byte of the payload after the header byte should be driven on the input data bus for every new falling edge of clock.
    
  • After the last payload byte has been driven, on the next falling clock, the packet_valid signal must be de-asserted, and the packet parity byte should be driven. This signals the completion of the packet.
    
  • The testbench shouldn't drive any bytes when a busy signal is detected instead it should hold the last driven value.
    
  • The busy signal when asserted drops any incoming byte of data.
    
  • The err signal is asserted when a packet parity mismatch is detected.
    

Characteristics:

• TestBench Note:
  • All output signals are active high and are synchronized to the rising edge of the clock.
    
  • Each output port data_out_x (data_out_0, data_out_1, data_out_2) is internally buffered by a FIFO of size 16x9.
    
  • The router asserts the vld_out_x (vld_out_0, vld_out_1, vld_out_2) signal when valid data appears on the data_out_x (data_out_0, data_out_1, data_out_2) output bus. This is a signal to the receiver's client which indicates that data is available on a particular output data bus.
    
  • The packet receiver will then wait until it has enough space to hold the bytes of the packet and then respond with the assertion of the read_enb_x ( read_enb_0, read_enb_1, read_enb_2) signal.
    
  • The read_enb_x (read_enb_0, read_enb_1, read_enb_2) input signal can be asserted on the falling clock edge in which data are read from the data_out_x (data_out_0, data_out_1, data_out_2) bus.
    
  • The read_enb_x (read_enb_0, read_enb_1, read_enb_2) must be asserted within 30 clock cycles of vld_out_x (vld_out_0, vld_out_1, vld_out_2) being asserted else time-out occurs, which resets the FIFO.
    
  • The data_out_x bus will be tri-ststed during a scenario when a packet's byte is lost due to time-out condition.