北京邮电大学 2023-2024 春季学期《计算机组成原理》课程实验集合

UVM Verification - 4 instances of Dual Port RAM 4096*64 chips are instantiated

SRAM Collection – Parameterized Verilog Modules for Single Port SRAM (sync/async read), Pseudo Dual Port SRAM (sync read), and True Dual Port SRAM – all parameterized, fully synthesizable, and demo’d with testbenches and waveforms.

Synthesizable FPGA IP core: synchronous 64×8 dual-port RAM supporting concurrent read access and single-port write.