Verilog UART

Minimalistic H264/SVC encoder single header library

A complete set of functions to read and write H.264 video bitstreams, in particular to examine or modify headers.

H264视频解码verilog实现

Python implementation of H264

Proof of Concept to learn Amaranth as an entry effort for Supercon's RTL design competition

Sound Open Firmware

Master programming by recreating your favorite technologies from scratch.

List of artists and hackers using homegrown time-tracking tools

Scots Army Knife for electronics

CHO is a benchmark suite for OpenCL FPGA Accelerators

Easy-to-use programming language made for the game Else Heart.Break()

OZ: a sandboxing system targeting everyday workstation applications

Subgraph OS Handbook

Brainfuck microprocessor

A Property Graph Model Interface (no longer active - see Apache TinkerPop)

UNIX-like reverse engineering framework and command-line toolset

🌊 Digital timing diagram rendering engine

Utilities written in Python to ease the work dealing with Xilinx files

An optimizing decompiler

Personal development branch for pcbre (probably not what you want)

Automated analysis tools for turning gate-level netlists from FPGA bitstreams, machine vision tools, etc into high-level RTL netlists.

public domain tools for FPGAs

ReconOS operating system version 3

Fast http dead file finder.