Introduction & Context In the previous posts, we designed an entire custom ITCH parser, going all the way from raw ethernet parsing to having a market state. The overall functional block diag...

Introduction & Context During the past few months, I’ve been working on my power electronics skills through a project that felt easy on paper, but turned out to be a bit more complicated than ...

A practical setup guide for MATLAB/Vivado HDL cosimulation on Linux. Covers version compatibility, FTD2XX and Digilent Adept driver installation, library path fixes and timescale configuration to get SystemVerilog modules running inside Simulink.

Reducing BRAM address collisions in an FPGA order book using XOR folding to hash 64-bit NASDAQ order references into a 17-bit address space. Benchmarked against real ITCH market data on high and low volume stocks.

Building an FPGA price ladder as an AXI4 Lite slave for a NASDAQ ITCH order book. Covers BRAM based bid/ask quantity tracking, a 2 stage pipeline datapath, cocotb verification and full system integration with real 2019 market data.

Implementing an FPGA order book in BRAM for a NASDAQ ITCH 5.0 trading system. Covers order reference hashing to fit 64-bit refs into a 17-bit address space, datapath design and cocotb integration testing with real market data.

Verifying a NASDAQ ITCH 5.0 parser on FPGA using cocotb, cocotbext-eth and real market data binary files. Covers testbench architecture, itchfeed integration and filtering live order flow for targeted RTL debugging.

Designing a NASDAQ ITCH 5.0 message parser in SystemVerilog for an FPGA order book. Covers FSM architecture for on-the-fly message decoding, state commit logic and AXI Stream backpressure questions at high fabric frequencies.

Building an FPGA MoldUDP64 parser in SystemVerilog as the first stage of a low latency NASDAQ ITCH order book. Covers AXI Stream pipeline design, FSM based header stripping and cocotb verification with real packet data.

Honest thoughts on my early Youtube journey, covering deeply technical subjects, with a touch of humour.

Building a Gigabit Ethernet MAC in SystemVerilog on the KC705. Covers RGMII interface, IDDR clock capture, AXI Stream datapaths, clock domain crossing and bare-metal DMA firmware on a RISC-V softcore.

Programming a custom MSPM0 PCB with an STLINK V2 using OpenOCD and GDB. Covers KiCad PCB design, SWD debugging setup (GDB) and bare-metal firmware for I2C accelerometer readout over UART.

Running DOOM on a homemade RISC-V CPU implemented on FPGA. A deep dive into cache optimizations, hardware multiplication with DSPs and SPI display integration on the HOLY CORE softcore.

Thoughts on building HOLY CORE, an open source RV32IM RISC-V softcore on FPGA — the design process, what it felt like to go from simulation to real hardware, and why this project matters beyond the technical.

Cocotb project setup, testbench patterns and AXI interface verification using cocotbext-axi. A practical walkthrough with Verilator, SystemVerilog interfaces and AxiRam slave simulation.

Experiment: Applying real-time scheduling theory from embedded systems to production line planning.

Learn how to run PyTorch neural network inference on FPGA manually using FINN, Vivado and Vitis. Covers AXI Stream glue logic design, DMA integration and bare-metal C firmware on Zynq.

Deploy a PyTorch neural network on FPGA using FINN and Brevitas. Full workflow from quantization aware training and ONNX export to hardware generation on Zynq with Vivado and Vitis.

Learn how to implement AXI DMA on Zynq FPGA with a hands-on FFT example. Full Vivado & Vitis walkthrough: hardware design, bare-metal firmware, and AXI Stream interfacing.

Learn how to build a custom AXI LED IP on Zynq from scratch. Full Vivado and Vitis walkthrough covering AXI Lite interface design, block diagrams, and bare-metal software on the Zynq PS.