AU2003270392A1 - Assemblies having stacked semiconductor chips - Google Patents
Assemblies having stacked semiconductor chipsInfo
- Publication number
- AU2003270392A1 AU2003270392A1 AU2003270392A AU2003270392A AU2003270392A1 AU 2003270392 A1 AU2003270392 A1 AU 2003270392A1 AU 2003270392 A AU2003270392 A AU 2003270392A AU 2003270392 A AU2003270392 A AU 2003270392A AU 2003270392 A1 AU2003270392 A1 AU 2003270392A1
- Authority
- AU
- Australia
- Prior art keywords
- assemblies
- semiconductor chips
- stacked semiconductor
- stacked
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US9888002P | 2002-09-11 | 2002-09-11 | |
| US60/4098,880 | 2002-09-11 | ||
| PCT/US2003/028041 WO2004025699A2 (en) | 2002-09-11 | 2003-09-08 | Assemblies having stacked semiconductor chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU2003270392A1 true AU2003270392A1 (en) | 2004-04-30 |
| AU2003270392A8 AU2003270392A8 (en) | 2004-04-30 |
Family
ID=31990051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2003270392A Abandoned AU2003270392A1 (en) | 2002-09-11 | 2003-09-08 | Assemblies having stacked semiconductor chips |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU2003270392A1 (en) |
| WO (1) | WO2004025699A2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6856007B2 (en) | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
| US6972480B2 (en) | 2003-06-16 | 2005-12-06 | Shellcase Ltd. | Methods and apparatus for packaging integrated circuit devices |
| JP2007528120A (en) | 2003-07-03 | 2007-10-04 | テッセラ テクノロジーズ ハンガリー コルラートルト フェレロェセーギュー タールシャシャーグ | Method and apparatus for packaging integrated circuit devices |
| WO2005031862A1 (en) | 2003-09-26 | 2005-04-07 | Tessera, Inc. | Structure and method of making sealed capped chips |
| US7157309B2 (en) | 2004-04-09 | 2007-01-02 | Tessera, Inc. | Manufacture of microelectronic fold packages |
| US8143095B2 (en) | 2005-03-22 | 2012-03-27 | Tessera, Inc. | Sequential fabrication of vertical conductive interconnects in capped chips |
| US7755457B2 (en) | 2006-02-07 | 2010-07-13 | Harris Corporation | Stacked stripline circuits |
| US8604605B2 (en) | 2007-01-05 | 2013-12-10 | Invensas Corp. | Microelectronic assembly with multi-layer support structure |
| JP7141877B2 (en) * | 2018-07-18 | 2022-09-26 | キオクシア株式会社 | semiconductor storage device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5117282A (en) * | 1990-10-29 | 1992-05-26 | Harris Corporation | Stacked configuration for integrated circuit devices |
| US5448511A (en) * | 1994-06-01 | 1995-09-05 | Storage Technology Corporation | Memory stack with an integrated interconnect and mounting structure |
| US5646446A (en) * | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
| US6225688B1 (en) * | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
| US6351029B1 (en) * | 1999-05-05 | 2002-02-26 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
-
2003
- 2003-09-08 AU AU2003270392A patent/AU2003270392A1/en not_active Abandoned
- 2003-09-08 WO PCT/US2003/028041 patent/WO2004025699A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| AU2003270392A8 (en) | 2004-04-30 |
| WO2004025699A3 (en) | 2004-06-17 |
| WO2004025699A2 (en) | 2004-03-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |