KR20030021124A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Provided is a semiconductor device which prevents the sense speed of an individual sense amplifier from being lowered due to the driving of a plurality of sense amplifiers. Inside the main surface of the epitaxial layer 3, a P-type well layer 6 containing P-type impurities is selectively disposed, and an N-type bottom layer containing N-type impurities so as to contact the bottom of the P-type well layer 6 ( 7) is arranged. The P type well layer 2 is arranged to have a thickness in contact with the N type bottom layer 7, and a PN junction is formed between the N type bottom layer 7 and the P type well layer 2. In addition, inside the main surface of the epitaxial layer 3, an N-type well layer 4 including N-type impurities and a P-type well layer 5 including P-type impurities are formed to sandwich the P-type well layer 6 therebetween. It is optionally arranged.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a sense amplifier such as DRAM (Dynamic Random Access Memory) and a method for manufacturing the same.

<Configuration of Memory Cells>

As an example of a DRAM, FIG. 17 shows a configuration of a memory cell portion of the DRAM 90 of a one transistor cell system having one N-channel MOS transistor (NMOS transistor) in one memory cell.

In Fig. 17, in the four portions in which two data lines DL0 and DL1 arranged in parallel and two word lines WL0 and WL1 arranged in parallel intersect, the NM0S transistors M0, M1, M2, respectively. And memory cells MC0, MC1, MC2, and MC3 having M3.

The gate electrode and the drain electrode of the MOS transistor M0 are connected to the word line WL0 and the data line DL0, and the gate electrode and the drain electrode of the NMOS transistor M1 are connected to the word line WL0 and the data line DL1, and the gate electrode of the NMOS transistor M2. And the drain electrode are connected to the word line WL1 and the data line DL0, and the gate electrode and the drain electrode of the NM0S transistor M3 are connected to the word line WL1 and the data line DL1.

The capacitor CS is connected between the source electrode of each of the NM0S transistors M0, M1, M2, and M3 and the ground potential.

A sense amplifier SA is connected to the data lines DL0 and DL1, respectively, and one end of the data lines DL0 and DL1 is connected to and disconnected from the data input / output line IO by the column select switches CW0 and CW1, respectively. It is. At this time, the sense amplifier SA has switches SW0 and SW1 whose operation is controlled by the sense amplifier drive signal.

The other ends of the data lines DL0 and DL1 have a configuration in which connection and disconnection with the precharge voltage supply line PL are controlled by the precharge switches PW0 and PW1. The capacitor CD is parasitic on the data lines DL0 and DL1.

Next, the operation of the DRAM 90 will be described with reference to FIG. 17.

<Precharge Action>

In DRAM, the precharge operation is performed prior to the operation of the memory cell. The precharge operation is an operation in which the data lines DL0 and DL1 are set to a predetermined precharge voltage VP. The precharge voltage VP is generally half of the write voltage VDD (VP = VDD / 2).

By setting the precharge voltage VP to an intermediate value between the write voltage VDD and 0V to the capacitor, power consumption and noise due to charging and discharging of the data line can be reduced.

The precharge operation is started by turning on the precharge clock, and when the precharge clock is off, the precharge voltage VP is maintained in the floating state on the parasitic capacitance CD of the data line.

<Read operation>

An operation of reading data of a specific memory cell, for example, memory cell M0, will be described.

First, the word line WL0 to which the memory cell M0 is connected is selected, and a pulse voltage (word pulse) is applied. As a result, the signal voltage VS corresponding to the information voltage (VDD or 0V) of the capacitor CS in the memory cell M0 is superimposed on the precharge voltage VP and output to the data line DL0 as a positive or negative signal. Here, the operation in which the information of the capacitor is output to the data line is sometimes referred to as "calling data". The signal voltage VS is represented by the following formula (1).

[1]

In general, the capacitance of the capacitor CS is much smaller than that of the parasitic capacitance CD, and in recent years, in order to reduce the area of the semiconductor chip, the memory cell is miniaturized, and as many data cells as possible can be connected to one data line. Since the capacitor CS is smaller, the parasitic capacitance CD tends to be larger.

The signal voltage VS, which is a small positive and negative signal, is detected and amplified by the sense amplifier SA connected to the data lines DL0 and DL1.

The sense amplifier SA operates by using the precharge voltage VP (VDD / 2) as a reference voltage. If the signal voltage VS is greater than VDD / 2, the output voltage of the sense amplifier SA becomes VDD. It becomes zero.

The amplification voltage corresponding to the information of the capacitor CS is output to the outside by turning on the column select switches CW0 and CW1, and the read operation is completed. At this time, the information of all unselected memory cells (here, memory cell M1) on the selected word line (here word line WL0) is also called in data line DL1 and amplified by sense amplifier SA.

When a word pulse is applied, the information of all the memory cells on that word line is destroyed. That is, since the capacity of the capacitor CS is sufficiently small compared to the parasitic capacitance CD, the storage node of the capacitor CS, which was VDD or 0 V, is charged with the precharge voltage regardless of its information voltage.

More specifically, the storage node voltage corresponding to the two-value information changes from VDD to (VDD / 2) + VS or from 0V to (VDD / 2) -VS when a word pulse is applied. In short, the voltage margin of the binary information of the storage node decreases from VDD to 2VS, resulting in a state in which the information is destroyed.

Therefore, sense amplifiers must be provided on all data lines, and these signal amplifiers must simultaneously amplify the signal voltage VS to VDD or 0V and rewrite the respective memory cells.

Therefore, in the read operation, a series of operations such as call, amplification, and rewriting of the small signal voltage VS are performed in parallel to all the memory cells on the selected word line, and only the information of the data line to which the selected memory cell is connected is performed. This is extracted outside as read information.

<Recording action>

The write operation to the selected memory cell, for example, memory cell M0, is executed by applying a word pulse to word line WL0 and providing one of two information voltages (VDD or 0V) to data line DL0. do.

However, as described above, since the information destruction of the unselected cells by applying the word pulse must be prevented, the read operation is performed before the write operation.

That is, the above-described read operation is performed on all the memory cells on word line WL0, and the amplification voltage corresponding to the information of the memory cells is temporarily held in each data line.

Thereafter, the column select switch CW0 is turned on to forcibly replace the amplification voltage on the selected data line DL0 with the write information voltage from the external (data input / output line IO) to input the write information voltage to the capacitor CS of the selected memory cell MC0. do.

At this time, the amplification voltages of all unselected data lines (here, data lines DL1) on the selected word line (here, word line WL0) are rewritten to the unselected cells (here, memory cell MC1).

By the above operation, regardless of the read or write operation of the selected cell, a series of operations such as calling, amplifying and rewriting the small signal voltage VS is performed in the non-selected memory cell on the selected word line.

At this time, to output a sufficient signal voltage to the data line, or to write the voltage VDD to the capacitor CS, the word pulse voltage is given as a voltage equal to or more than the sum of the voltage VDD and the threshold voltage Vth of the cell transistor.

<Refresh operation>

The refresh operation inherent in DRAM can be realized by sequentially performing the read operation described above for all word lines.

That is, the refresh operation is performed on a word line basis, and all memory cells on the word line are refreshed at the same time. As a result, the storage node voltage of the capacitor Cs in the memory cell is regenerated to an initial value even if the voltage is reduced due to a current leak. By performing the refresh operation on all word lines as described above, the information of all the memory cells is reproduced, and the storage information is held as the entire semiconductor chip.

<Overall Configuration of DRAM>

18 shows the overall configuration of the DRAM. FIG. 18 is a diagram schematically showing a planar configuration example of a general DRAM. The memory cell portion of the DRAM 90 described with reference to FIG. 17 is included in the memory array block MAB.

A plurality of memory array block MABs are arranged in two rows, and a power source is disposed in the center of the array to form a central power source CPW.

In this case, although not shown in FIG. 18, the central power supply CPW includes a pad for connecting and grounding an external power supply, a voltage down converter VDC for stepping down the external power supply voltage to an internal power supply voltage, an internal power supply voltage, and a ground voltage. Wiring for transmission is arranged. In the memory array block MAB, a plurality of memory cells are arranged to form a memory array, and peripheral circuits such as sense amplifiers and the like are arranged.

FIG. 19 schematically shows the configuration of the memory array block MAB shown in FIG. 18 and shows a state in which the memory array block MAB is composed of a plurality of memory array MAs.

Here, the configuration of one memory array MA in the memory array block MAB is shown in FIG.

As shown in Fig. 20, a plurality of memory cells MC are arranged in a matrix form at predetermined intervals to form a memory cell array. The memory cells MC in the same column direction are connected to a common bit line BL, which is a data line, and the bit line BL is connected to a sense amplifier SA. Two bit lines BL are connected to one sense amplifier to form a pair of bit lines.

A plurality of word lines WL are arranged so as to be orthogonal to the plurality of bit lines BL arranged in parallel, and each word line WL is commonly connected to the memory cells MC in the same row direction.

In FIG. 20, the memory cell MC is shown as the contour shape of the active region of the MOS transistor, the bit line BL is connected to the source / drain layer of the MOS transistor, and the word line WL is shown as the gate electrode of the MOS transistor.

At this time, the sense amplifier SA uses one voltage among two bit lines BL to be connected as a reference voltage.

Next, the configuration around the sense amplifier SA in the configuration of FIG. 20 will be described with reference to FIG. 21.

As shown in FIG. 21, sense amplifier SA has PMOS transistor P2 and NMOS transistor N2 connected in series similarly to P-channel MOS transistor (PMOS transistor) P1 and NMOS transistor N1 connected in series, and PMOS transistor P1. And the gate electrode of the NM0S transistor N1 is commonly connected to the connection node of the PMOS transistor P2 and the NMOS transistor N2, and the gate electrodes of the PMOS transistor P2 and the NMOS transistor N2 are commonly connected to the connection node of the PMOS transistor P1 and the NM0S transistor N1. Connected.

The connection node of the PM0S transistor P1 and the NMOS transistor N1 is connected to the bit line BL, and the connection node of the PM0S transistor P2 and the NMOS transistor N2 is connected to the bit line / BL.

The bit line BL and the bit line / BL constitute a pair of bit line pairs, and the bit lines BL and / BL are connected to the data input / output lines IO and / IO by an NMOS transistor MSW controlled by a signal of the column select line CSL. In this case, the non-connection is controlled.

The power supply wirings WR1 and WR2 and the sense enable wirings SEp and SEn are arranged so as to be orthogonal to the plurality of bit line pairs.

The power supply wiring WR1 is a wiring supplied with the internal voltage VDD and is paired with the sense enable wiring SEp, and both are electrically connected through the PM0S transistor MP1 which is a driver transistor.

The power supply wiring WR2 is a wiring supplied with the ground voltage GND, and is paired with the sense enable wiring SEn, and both are electrically connected to each other via the NM0S transistor MN1 as the driver transistor.

The source electrodes of the PM0S transistors P1 and P2 constituting the sense amplifier SA are connected to the sense enable wiring SEp, and the source electrodes of the NMOS transistors N1 and N2 are connected to the sense enable wiring SEn.

In such a configuration, only when the sense amplifier drive signals / SAE and SAE are applied to the PMOS transistors MP1 and the NMOS transistor MN1, the source electrodes of the PM0S transistors P1 and P2 constituting the sense amplifier SA, and the NMOS transistors N1 and N2 The internal voltage VDD and the ground voltage GND are applied to the source electrode, and in other cases, the source electrode is floating. This operation is performed to reduce the standby current of the sense amplifier.

FIG. 22 schematically shows a wiring diagram for supplying power to the sense amplifier SA arranged in the memory array MA.

As described with reference to FIG. 21, the sense amplifier SA is supplied with the internal voltage VDD through the power supply wiring WR1 and the sense enable wiring SEp, and the ground voltage GND through the power supply wiring WR2 and the sense enable wiring SEn. As shown in Fig. 22, WR1 and WR2 have a configuration in which the voltage is fixed through the mesh power lines MPL1 and MPL2 connected to the central power supply CPW.

A plurality of power supply wirings are connected to one mesh power line. That is, the mesh power line MPL1 is a wiring for supplying the internal voltage VDD and is connected to the power supply wiring WR1 arranged in each memory array MA. The mesh power line MPL2 is a wiring for supplying the ground voltage GND, and is connected to the power supply wiring WR2 disposed in each memory array MA.

At this time, a plurality of mesh power lines MPL1 and MPL2 are alternately arranged, and a plurality of mesh power lines MPL1 are connected to the output line OL1 of the step-down VDC for stepping down the external power supply voltage Vdd to the internal voltage VDD. At this time, the external power supply voltage Vdd is supplied from the outside of the semiconductor chip through the external voltage pad PD2.

The plurality of mesh power lines MPL2 are connected to the ground line OL2 connected to the ground pad PD1.

Here, with reference to FIG. 21, the problem at the time of reading data from a memory cell is demonstrated using the timing chart shown in FIG.

Fig. 23 shows the voltage change of the sense enable wirings SEp and SEn and the bit lines BL and / BL. The waveform shown by the solid line represents a problem, and the waveform shown by the dotted line is an ideal waveform.

When the sense amplifier drive signals SAE and / SAE are given at the timing indicated by the arrows in FIG. 23, the internal voltage VDD is supplied to the source electrodes of the PM0S transistors P1 and P2 constituting the sense amplifier SA through the sense enable wiring SEp. The ground voltage GNP is supplied to the source electrodes of the NMOS transistors N1 and N2 through the sense enable wiring SEn.

At this time, ideally, the bit line BL rapidly rises as indicated by the dotted line at the timing at which the sense amplifier drive signal SAE is given, and the bit line BL rapidly drops at the timing at which the sense amplifier drive signal / SAE is given.

However, when a plurality of sense amplifiers SA are turned on all at once, as shown in Fig. 23, the potentials of the sense enable SEp and SEn fluctuate by ΔVDD and ΔGND, respectively.

Since a plurality of sense amplifiers are connected to the sense enable wirings SEp and SEn, the wiring length is long, the wiring capacity is large, and a voltage drop caused by the wiring capacity is generated at the sense enable wiring SEp, and the voltage rise is sensed. This is because it occurs in the enable wiring SEn. The time integration values of the electron current and the hall current causing this voltage change are equal by the charge storage law.

As described above, if the internal voltage VDD or ground voltage GND for driving the sense amplifier is changed, the driving capability of the transistors constituting the sense amplifier is reduced. Thus, word pulses are applied to the word lines, and reading is started. The delay time tRCD until sensing and discriminating information becomes long. As a result, there arises a problem that the sense operation of the sense amplifier becomes slow.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device which prevents the sense speed of individual sense amplifiers from lowering due to driving of a plurality of sense amplifiers.

1 is a cross-sectional view showing the configuration of features of a semiconductor device of Embodiment 1 according to the present invention.

Fig. 2 is a diagram showing the circuit configuration of the semiconductor device according to the first embodiment of the present invention.

3 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment of the present invention.

4 is a diagram showing the results of operation simulation of the semiconductor device according to the first embodiment of the present invention.

5 is a diagram showing the results of the operation simulation of the semiconductor device of Example 1 of the present invention.

6 is a diagram showing the results of operation simulation of the semiconductor device according to the first embodiment of the present invention.

7 is a diagram showing simulation results of impurity distribution in the semiconductor device of Example 1 of the present invention.

8 is a diagram showing a simulation result of impurity distribution in the semiconductor device of Example 1 of the present invention.

9 is a diagram showing simulation results of changes in junction capacitance of the semiconductor device according to the first embodiment of the present invention.

10 is a diagram showing simulation results of changes in specific resistance of the semiconductor device according to the first embodiment of the present invention.

11 is a cross-sectional view showing the configuration of a modification of the semiconductor device of Embodiment 1 of the present invention.

12 is a cross-sectional view showing the configuration of a modification of the semiconductor device of Embodiment 1 of the present invention.

Fig. 13 is a sectional view showing a structure for fixing potential of an N-type well layer in the semiconductor device according to the first embodiment of the present invention.

Fig. 14 is a sectional view showing a structure for fixing potential of an N-type well layer in the semiconductor device of Example 1 of the present invention.

Fig. 15 is a diagram showing the circuit configuration of the semiconductor device of Example 2 of the present invention.

Fig. 16 is a sectional view showing the structure of features of the semiconductor device of Embodiment 2 of the present invention.

Fig. 17 is a diagram showing the circuit configuration of a DRAM of a general one transistor cell system.

18 is a diagram showing the overall configuration of a general DRAM.

19 is a diagram showing the overall configuration of a memory array block of a general DRAM.

20 is a diagram showing the configuration of a memory array of a general DRAM.

Fig. 21 is a diagram showing a configuration around a sense amplifier of a general DRAM.

Fig. 22 is a diagram for explaining wiring for supplying power to a sense amplifier of a general DRAM.

Fig. 23 is a diagram for explaining the operation of a general DRAM.

Explanation of symbols on the main parts of the drawings

1: semiconductor substrate 2, 5, 6: P-type well layer

3: epitaxial layer 4: N-type well layer

7: N type bottom layer WR1, WR2: power supply wiring

A semiconductor device according to one aspect of the present invention is a main semiconductor layer of a first conductivity type in which a plurality of wiring layers are disposed on an entire main surface of a semiconductor substrate, and a plurality of wiring layers are disposed thereon, and a first main surface of the main semiconductor layer. A first semiconductor layer of a first conductivity type selectively disposed therein, and selectively inside the first main surface of the main semiconductor layer adjacent to the first semiconductor layer so as to sandwich the first semiconductor layer therebetween A second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type, and selectively inside the main semiconductor layer below the first semiconductor layer so as to be in contact with at least a bottom surface of the first semiconductor layer. And a fourth semiconductor layer of the second conductivity type disposed, and a fifth semiconductor layer of the first conductivity type disposed on the entire inner surface of the second main surface of the main semiconductor layer, wherein the fifth semiconductor layer is the first semiconductor layer. 4 Two forming the PN junction with the semiconductor layer And a bonding capacitance between the fifth semiconductor layer and the fourth semiconductor layer, wherein the plurality of wiring layers are provided with a first power supply wiring to which a first voltage is supplied, and a second voltage lower than the first voltage. It has a 2nd power supply wiring, The said 3rd semiconductor layer is electrically connected to the said 1st power supply wiring, The said 2nd semiconductor layer is electrically connected to the said 2nd power supply wiring.

In a semiconductor device according to another aspect of the present invention, the main semiconductor layer corresponds to an epitaxial layer of an epitaxial substrate, and the fifth semiconductor layer is disposed so as to cover the entire main surface of the semiconductor substrate.

In a semiconductor device according to another aspect of the present invention, the main semiconductor layer corresponds to a S0I layer of a S0I substrate, and the fifth semiconductor layer covers an entire main surface of a buried insulating film disposed under the SOI layer. It is arranged to be.

In a semiconductor device according to another aspect of the present invention, the thicknesses of the first and third semiconductor layers are the same, and the fourth semiconductor layer is disposed to contact the bottom surface of the third semiconductor layer.

In a semiconductor device according to another aspect of the present invention, the fifth semiconductor layer is divided into a first region corresponding to a lower portion of the first semiconductor layer and a second region corresponding to a lower portion of the second semiconductor layer. The thickness of the second region is thicker than the thickness of the first region, and the second region is disposed to protrude in the direction of the second semiconductor layer.

A semiconductor device according to another aspect of the present invention includes a first conductive layer penetrating through the second semiconductor layer and the main semiconductor layer to reach an interface between the first region and the second region of the fifth semiconductor layer. And a second plug layer, wherein the second voltage is applied to the fifth semiconductor layer through the plug layer.

In a semiconductor device according to another aspect of the present invention, the first and second power supply wirings are wirings for supplying driving power for a sense amplifier.

In a semiconductor device according to another aspect of the present invention, the first and second power supply wirings are wirings for supplying driving power to an inverter.

A semiconductor device manufacturing method according to one aspect of the present invention includes a first conductive main semiconductor layer having a plurality of wiring layers disposed on an entire main surface of a semiconductor substrate, and a plurality of wiring layers disposed thereon, and a first semiconductor layer Inside the first major surface of the main semiconductor layer adjacent to the first semiconductor layer so as to sandwich the first semiconductor layer of the first conductivity type selectively disposed inside the first major surface and the first semiconductor layer therebetween. A second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type selectively disposed on the substrate, and inside the main semiconductor layer below the first semiconductor layer to be in contact with at least a bottom surface of the first semiconductor layer. In the manufacturing method of a semiconductor device, comprising a fourth semiconductor layer of the second conductivity type selectively disposed in the first semiconductor layer, and a fifth semiconductor layer of the first conductivity type disposed on the entire inner surface of the second main surface of the main semiconductor layer. To the semiconductor substrate (A) preparing a substrate having a relatively high concentration of impurities of a first conductivity type, and after forming the main semiconductor layer on the entire main surface of the semiconductor substrate, the first to fourth semiconductor layers are formed. Before the step, the step (b) of heating the semiconductor substrate in a temperature range of 900 ° C. to 1200 ° C. for 30 minutes or more to diffuse the first conductivity type impurities in the semiconductor substrate to form the fifth semiconductor layer. Equipped.

In the method for manufacturing a semiconductor device according to another aspect of the present invention, the step (b) also combines a step of selectively forming an element isolation insulating film inside the first main surface of the main semiconductor layer.

In the method of manufacturing a semiconductor device according to another aspect of the present invention, the heating time of the semiconductor substrate is 150 to 400 minutes.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a main semiconductor layer of a first conductivity type disposed on an entire main surface of a semiconductor substrate and having a plurality of wiring layers disposed thereon; and the main semiconductor layer The first main layer of the main semiconductor layer adjacent to the first semiconductor layer so as to sandwich the first semiconductor layer of the first conductivity type selectively disposed within the first main surface of the first semiconductor layer; A second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type selectively disposed inside the surface, and the main semiconductor under the first semiconductor layer so as to be in contact with at least a bottom surface of the first semiconductor layer. A method for manufacturing a semiconductor device, comprising a fourth semiconductor layer of a second conductivity type selectively disposed in a layer and a fifth semiconductor layer of a first conductivity type disposed on the entire surface of the second main surface of the main semiconductor layer. In the semiconductor substrate After forming the main semiconductor layer on the entire main surface, and before forming the first to fourth semiconductor layers, the first conductive type impurities are ion-implanted over the entire surface of the main semiconductor layer, and the fifth The process of forming a semiconductor layer is provided.

(Example of the invention)

<A. Example 1

<A-1.Device Configuration>

As a semiconductor device of Embodiment 1 according to the present invention, a cross-sectional structure of a feature portion of the DRAM 100 is shown in FIG.

As shown in FIG. 1, the DRAM 100 includes a P-type impurity containing the P-type impurity on the entire main surface of the semiconductor substrate 1 (for example, a silicon substrate) containing P-type impurities at a relatively high concentration (P +). The well layer 2 is disposed, and the epitaxial layer 3 containing the P-type impurities at a relatively low concentration (P−) is disposed on the P-type well layer 2.

Inside the main surface of the epitaxial layer 3, a P-type well layer 6 containing P-type impurities is selectively disposed, and an N-type bottom layer containing N-type impurities so as to contact the bottom of the P-type well layer 6 ( 7) is arranged. The P-type well layer 2 is arranged to have a thickness in contact with the N-type bottom layer 7, and a PN junction is formed between the N-type bottom layer 7 and the P-type well layer 2.

In addition, inside the main surface of the epitaxial layer 3, an N-type well layer 4 including N-type impurities and a P-type well layer 5 including P-type impurities are formed to sandwich the P-type well layer 6 therebetween. It is optionally arranged.

At this time, although the ratio which the epitaxial layer 3 occupies is small in FIG. 1, in fact, the epitaxial substrate is comprised by the semiconductor substrate 1 and the epitaxial layer 3 about 6 micrometers in thickness, and P The type well layer 2 is disposed inside the main surface of the epitaxial layer 3 simultaneously with the N type well layers 4 and the P type well layers 5 and 6.

In the main surfaces of the N-type well layer 4 and the P-type well layer 5, an element isolation insulating film 8 referred to as STI (Shallow Trench Isolation) is selectively disposed to define a region for forming the M0S transistor. .

At this time, the region of the P-type well layer 6 is defined by the element isolation insulating film 8, and since the memory cell is disposed inside the region, the P-type well layer 6 is called a memory cell region.

Here, the P-type well layer 2 is a P-type impurity, for example, from the semiconductor substrate 1 containing a relatively high concentration of P-type impurity in the high temperature heat treatment when forming the device isolation insulating film 8. For example, it is formed by thermally diffusing boron (B).

In the N type well layer 4, a pair of source / drain layers 41 containing a relatively high concentration of P-type impurities are disposed in a region defined by the device isolation insulating film 8, and a pair of source / drain layers 41 is disposed. The gate insulating film 42 is disposed on the N-type well layer 4 between the edges of the opposing edges and between the pair of source / drain layers 41, and the gate electrode 43 is disposed on the gate insulating film 42. It is arranged. The sidewall insulating film 44 is disposed on the side surfaces of the gate insulating film 42 and the gate electrode 43 to form the PMOS transistor MP1. The gate electrode 43 of the PMOS transistor MP1 is provided with a sense amplifier driving signal / SAE.

In the P-type well layer 5, a pair of source / drain layers 51 containing N-type impurities at a relatively high concentration (N +) are arranged in a region defined by the element isolation insulating film 8, and a pair of sources A gate insulating film 52 is disposed on the P-type well layer 5 between the opposite end edges of the drain layer 51 and between the pair of source / drain layers 51, and a gate is formed on the gate insulating film 52. The electrode 53 is arranged. The sidewall insulating film 54 is disposed on the side surfaces of the gate insulating film 52 and the gate electrode 53 to form the NM0S transistor MN1. The gate electrode 53 of the NMOS transistor MN1 is provided with a sense amplifier driving signal SAE.

Here, a region where the PM0S transistor MP1 is formed is referred to as a PMOS formation region, and a PM0S transistor constituting a peripheral circuit of the memory cell is formed. In addition, a region where the NM0S transistor MN1 is formed is referred to as an NM0S formation region, and an NM0S transistor constituting a peripheral circuit of the memory cell is formed.

At this time, an interlayer insulating film (not shown) is disposed to cover the upper portion of the semiconductor substrate 1 including the upper portions of the PMOS transistor MP1 and the NMOS transistor MN1, and various wirings are disposed inside the interlayer insulating film.

That is, one of the pair of source and drain layers 41 is electrically connected to the power supply wiring WR1 through the contact hole CH1 provided in the interlayer insulating film, and the other of the pair of source and drain layers 41 is in the interlayer insulating film. It is electrically connected to the sense enable wiring SEp via the contact hole CH3 provided.

In addition, one of the pair of source and drain layers 51 is electrically connected to the power supply wiring WR2 through the contact hole CH2 provided in the interlayer insulating film, and the other of the pair of source and drain layers 51 is in the interlayer insulating film. It is electrically connected to the sense enable wiring SEn via the contact hole CH4 provided.

In addition, an N-type impurity layer 45 including N-type impurities at a relatively high concentration is selectively provided in the N-type well layer 4, and the power supply line WR1 is electrically connected to the N-type impurity layer 45 through the contact hole CH11. Is connected.

Similarly, a P-type impurity layer 55 containing a relatively high concentration of P-type impurities is selectively provided in the P-type well layer 5, and the power supply wiring WR2 is electrically connected to the P-type impurity layer 55 through the contact hole CH21. Is connected.

In this case, various capacitive components and resistive components are schematically described in FIG. 1. That is, the junction capacitance between the P-type well layer 2 and the N-type bottom layer 7 is C1, the wiring parasitic capacitance of the sense enable wiring SEp is C3, and the wiring parasitic capacitance of the sense enable wiring SEn is C4, and the N well layer The resistance of (4) is represented by R1, the resistance of the P-type well layer 5 is represented by R2, and the resistance of the semiconductor substrate 1 is represented by R3. At this time, the N-type bottom layer 7 extends to the lower part of the N-type well layer formed in the surface of the epitaxial layer 3 in a portion not shown in the direction perpendicular to FIG. It is connected to the internal voltage VDD through, and the junction capacitor C1 can accumulate charge corresponding to the internal voltage VDD.

Next, the electrical connection relationship between the sense amplifier of the DRAM 100 and its surrounding configuration will be described using FIG. 2. At this time, the equivalent circuit shown in FIG. 2 is basically the same as the equivalent circuit shown in FIG.

As shown in FIG. 2, the sense amplifier SA has the PMOS transistors P1 and NMOS transistor N1 connected in series, and the PM0S transistors P2 and NMOS transistor N2 connected in series, and the gates of the PMOS transistors P1 and NMOS transistor N1. The electrode is commonly connected to the connection node of the PMOS transistor P2 and the NM0S transistor N2, and the gate electrodes of the PMOS transistor P2 and the NMOS transistor N2 are commonly connected to the connection node of the PMOS transistor P1 and the NM0S transistor N1.

The connection node of PMOS transistor P1 and NM0S transistor N1 is connected to bit line BL0, and the connection node of PMOS transistor P2 and NM0S transistor N2 is connected to bit line / BL0.

A pair of bit line pairs is formed by bit lines BL0 and / BL0, and drain electrodes of the NMOS transistors N21 and N22 are connected to the bit lines / BL01 and BL0, respectively, between the source electrode and the ground electrode of the NMOS transistors N21 and N22. Capacitor CS is connected to constitute a memory cell.

The gate electrodes of the NM0S transistors N21 and N22 are connected to the word lines WL0 and WL1, respectively. At this time, the capacitor CD is parasitic on the bit lines BL0 and / BL0.

Further, the NMOS transistors N11 and N12 connected in series are arranged between the bit lines BL0 and / BL0, and the precharge voltage Vp is given to the connection nodes of both transistors. The gate electrodes of the NMOS transistors N11 and N12 are connected to an active signal line BLEQ which makes the bit line active.

At this time, the bit lines BL0 and / BL0 are connected to the data input / output lines, respectively, but are not shown.

Although the above configuration is provided for each of the plurality of sense amplifiers SA, in Fig. 2, only the configuration related to the bit lines BL1 and / BL1 adjacent to the bit lines BL0 and / BL0 is shown.

The source electrodes of the PMOS transistors P1 and P2 constituting the sense amplifier SA are connected to the sense enable wiring SEp, and the source electrodes of the NMOS transistors N1 and N2 are connected to the sense enable wiring SEn.

The sense enable wiring SEp is configured to be electrically connected to or disconnected from the power supply wiring WR1 supplied with the internal voltage VDD connected to the drain electrode of the PMOS transistor MP1 and to the source electrode of the PMOS transistor MP1. .

The sense enable wiring SEn is configured to be electrically connected to or disconnected from the power supply wiring WR2 supplied with the ground voltage GND connected to the drain electrode of the NM0S transistor MN1 and to the source electrode of the NM0S transistor MN1. .

At this time, each of the gate electrodes of the PMOS transistor MP1 and the NMOS transistor MN1 is provided with a sense amplifier driving signal / SAE and SAE.

The power supply wirings WR1 and WR2 are metal wirings, and the power supply wiring WR1 is supplied with the internal voltage VDD generated by the voltage conversion in the step-down voltage VDC installed in the central power supply CPW, as described with reference to FIG. The voltage drop occurs due to the presence of the wiring resistance Rmvdd, and the sense amplifier is given a voltage VDDS lower than the internal voltage VDD.

The problem here is that since the wiring parasitic capacitance C3 is present in the sense enable wiring SEp, by turning on the PMOS transistor MP1, the wiring parasitic capacitance C3 is applied to the power supply wiring WR1 via the PMOS transistor MP1, and the charge is applied to the wiring parasitic capacitance C3. Accumulation causes voltage VDDS to drop.

In addition, as described with reference to FIG. 22, the ground voltage GND is supplied to the power supply wiring WR2 from the ground pad PD provided in the central power supply CPW. However, since the wiring parasitic capacitance C4 is present in the sense enable wiring SEn, the NMOS transistor MN1 is connected to the power supply wiring WR2. By turning on, the wiring parasitic capacitance C4 is applied to the power supply wiring WR2 through the NM0S transistor MN1, and the charge accumulated in the wiring parasitic capacitance C4 is given to the power supply wiring WR2, and the ground voltage GND is raised. This fluctuating voltage is given to the sense amplifier as the voltage GNDS.

As described above, when the voltage VDDS or voltage GNDS for driving the sense amplifier changes, the driving capability of the transistor is reduced. Thus, word pulses are applied to the word line, and reading starts, until the information on the bit line is sensed and discriminated. Delay time tRCD becomes long.

In order to prevent this, the present inventors thought that the P-type well layer 2 and the N-type bottom layer 7 actively use the bonding capacitance C1.

That is, focusing on the charge / discharge path to the sense amplifier SA in Fig. 2, between the power supply wiring WR1 and the ground voltage GND, the resistors R1 (Rnwell) of the N-type well layer 4, the P-type well layer 2, and N The junction capacitance C1 (Cwell) and the resistance R3 (Rpsub) of the semiconductor substrate 1 exist with the type bottom layer, and the resistances R1 and P of the N type well layer 4 between the power supply wiring WR1 and the power supply wiring WR2. The junction capacitance C1 between the type well layer 2 and the N type bottom layer 7 and the resistance R2 (Rpwell) of the P type well layer 5 exist.

In such a configuration, the internal voltage VDD can be provided to the sense amplifier SA by the electric charges accumulated in the junction capacitance C1, and the ground voltage to the sense amplifier SA through the semiconductor substrate 1 and the P-type well layer 5. The technical idea that it is possible to provide GND has been reached.

More specifically, by increasing the junction capacitance C1 (Cwirell), the variation of the voltage VDDS applied to the sense amplifier SA is suppressed, and the sense amplifier SA is reduced by reducing the resistance R2 (Rpwel1) of the P-type well layer 5. It is to suppress the fluctuation of the voltage GNDS given to.

Hereinafter, while explaining the operation of the DRAM 100, the resistance R2 of the P-type well layer 5 is reduced, and the junction capacitance C1 between the P-type well layer 2 and the N-type bottom layer 7 is increased, thereby delaying. Explain that the time tRCD can be shortened.

<A-2. Device Behavior>

3 shows a timing chart for one time of a low address strobe (RAS) operation in the DRAM 100.

3 shows signals of the active signal line BLEQ for activating the bit line, the signal of the word line WL1, the signals of the sense amplifier drive signals SAE and / SAE, and the bit lines BL and / BL.

When the signal BLEQ of the active signal line BLEQ becomes Low (GND), and the word pulse (VWP: internal voltage VDD + cell transistor threshold voltage V _th ) is applied to the word line WL1 and becomes high, it is triggered by the rise of the word line WL1, In the bit line BL charged with the precharge voltage VP (VDDS / 2), the information of the capacitor CS of the memory cell is superimposed through the NMOS transistor N21. Therefore, a small potential difference occurs between the bit lines BL and / BL.

Next, when the sense amplifier drive signal SAE becomes High (VDD), it is triggered by the sense amplifier to drive it. Therefore, a small potential difference between the bit line pairs is amplified by the amplification operation of the sense amplifier, so that the potential of the bit line BL is increased. At High (VDDS), the potential of the bit line / BL is at Low (GNDS).

Then, the signal of the active signal line BLEQ is triggered by the rising to High (VDD), and the bit lines BL and / BL are again charged with the precharge voltage VP.

Here, assuming that the product of the resistance R2 and the junction capacitance C1 of the P-type well layer 5 shown in FIGS. 1 and 2 is constant, the case where the junction capacitance C1 is doubled and the resistance R2 is 1/2 times is assumed. The timing chart of the result of circuit simulation is shown in FIG. 4, and the timing chart of the result of circuit simulation is shown in FIG. 5, assuming that the junction capacitance C1 is 1/2 times and the resistance R2 is double.

4 and 5, the time (nsec) is indicated on the horizontal axis and the voltage (V) is displayed on the vertical axis to change the sense amplifier drive signals SAE and / SAE, and the voltage VDDS and voltage GNDS given to the sense amplifier. , The voltage change of the bit lines BL0 and / BL0, the voltage change of the bit lines BL1 and / BL1, the voltage change of the sense enable wiring SEp and the sense enable wiring SEn, and the precharge voltage VP.

4 and 5, when the sense amplifier drive signals SAE and / SAE are given, the attention is paid to the time from the time (120 nsec) at which the sense amplifier starts to drive until the bit line BL1 reaches 1.2 V of the discernible voltage of the bits. 4, it is about 7.1 nsec, whereas in FIG. 5, it is about 8.7 nsec.

This shows that the sense read time is shorter in FIG. 4 where the junction capacitance C1 is four times and the resistance R2 is 1/4 times, as compared with the case of FIG. 5.

Further, it is understood that the potential drop of the voltage VDDS and the potential rise of the voltage GNDS after the sense amplifier drive signal SAE becomes High are smaller than those in FIG. This means that by increasing the junction capacitance C1 and decreasing the resistance R2, the variation of the voltage VDDS can be suppressed to maintain a constant value, and the variation of the voltage GNDS can be suppressed to maintain a constant value.

This is also the reason why Fig. 4 becomes shorter at the time at which the bit can be identified, that is, the delay time tRCD until the information on the bit line is sensed and discriminated.

6 shows changes in the sense amplifier drive signal SAE, changes in the voltages of the bit lines BL1 and / BL1, changes in the voltage VDDS, and the voltage GNDS in FIG. 4 and FIG.

<A-3. Manufacturing Method>

As described above, the delay time tRCD can be shortened by reducing the resistance R2 of the P-type well layer 5 and increasing the junction capacitance C1 between the P-type well layer 2 and the N-type bottom layer 7. In the following, a specific method for increasing the junction capacitance C1 and reducing the resistance R2 will be described.

7 and 8 show simulation results of impurity concentration distribution (here impurity is boron) in the substrate depth direction of the P-type well layer 2 when the heat treatment temperature is fixed and the heat treatment time is changed.

In FIGS. 7 and 8, the depth (μm) is indicated on the horizontal axis and the impurity concentration (/ cm ³ ) is indicated on the vertical axis, and as the heat treatment temperature, for example, the heat treatment temperature at the time of forming the STI (element isolation insulating film 8). The impurity concentration distribution of the P-type well layer 2 in the case where phosphorus 1100 degreeC is used and heat processing time is made into 30 minutes, 150 minutes, 300 minutes, and 400 minutes is shown.

In FIG. 7, the impurity concentration distribution in the AA cross section in FIG. 1 is shown. In addition to the impurity concentration distribution of the P-type well layer 2 described above, the impurity concentration distribution of the N-type bottom layer 7 is shown. The longer the heat treatment time is, the higher the junction concentration between the P-type well layer 2 and the N-type bottom layer 7 is. And since the distribution of the thermally diffused boron forms a junction with the N type bottom layer 7, the junction capacitance C1 can be obtained.

At this time, as shown in FIG. 7, when the heat treatment time is 150 minutes, the P-type well layer 2 and the N-type bottom layer formed by boron of the semiconductor substrate 1 by thermal diffusion into the epitaxial layer 3 ( The junction concentration with 7) is slightly higher than 1x10 ¹⁵ / cm ^{3, which} is the impurity concentration of the epitaxial layer 4, but when the heat treatment time is 400 minutes, the junction concentration is about 3.5x10 ¹⁵ / cm ³ .

Here, when the depth at which the impurity of the P-type well layer 2 and the epitaxial layer 3 intersect is L1 and the depth at which the P-type well layer 2 and the semiconductor substrate 1 intersect is L2, the P-type well layer 2 ) Is defined as L 2 -L 1, for example, in the case where the heat treatment time is 300 minutes, L 1 is 2.3 μm and L 2 is 6 μm. When the thickness is 3.7 µm and the heat treatment time is 400 minutes, L1 is 1.8 µm and L2 is 6 µm, so that the thickness of the P-type well layer 2 is 4.2 µm.

In this case, the impurity concentration of the epitaxial layer 4 is 1x10 ¹⁵ / cm ³ , but the impurity concentration of the epitaxial layer 4 is 1x10 ¹⁵ to 1x10 ¹⁶ / cm ³ , and 1x10 ¹⁵ / cm ³ . It is not limited to ^three . In addition, although the thickness of the epitaxial layer 4 was 6 micrometers in the above, the range of the thickness of the epitaxial layer 4 is 1-10 micrometers, It is not limited to 6 micrometers.

In this case, in FIG. 7, the P-type well layer 2 and the N-type bottom layer 7 are reliably bonded when the heat treatment time is 300 or 400 minutes, but this is an example of heat treatment temperature conditions and the N-type bottom layer 7 P-type well layer 2 and N-type bottom layer 7 may be bonded even when the heat treatment time is 150 minutes depending on the thickness of the p-type well, and P-type well layer 2 and N-type may be bonded even if the heat treatment time is shorter. It is thought that the bottom layer 7 joins. Although it is difficult to understand in FIG. 7, even when the heat treatment time is 150 minutes, the impurity concentration of the P-type well layer 2 is epitaxial at the portion where the profile of the N-type bottom layer 7 and the profile of the P-type well layer 2 cross each other. It can be said that it is slightly higher than 1x10 <^15> / cm <^{3> which} is the impurity concentration of the tactic layer 4, and the junction concentration is higher than the epitaxial layer 4. As shown in FIG. Even at this degree, the bonding capacity can be dramatically increased as compared with the prior art. In other words, by prolonging the heat treatment time longer than 30 minutes, the diffusion of P-type impurities from the semiconductor substrate 1 can be promoted and the P-type well layer 2 can be thickened. At this time, the thermal diffusion of impurities is not limited to "temperature" and "time", but also "type of atmosphere gas (N ₂ gas, Ar gas, dry 0 ₂ gas, wet 0 ₂ gas, NO / 0 ₂ gas, etc.)", and "pressure." (Partial pressure of gas) ”is also affected.

8, the impurity concentration distribution in the BB cross section is shown in FIG. 1, and the impurity concentration distribution of the P-type well layer 5 is shown in addition to the impurity concentration distribution of the P-type well layer 2 described above. As the heat treatment time increases, the P-type well layer 2 becomes wider, and the distance between the P-type well layer 2 and the P-type well layer 5 becomes shorter.

Thus, the thickness of the P type well layer 2 shown in FIG. 1 can become thicker, so that the heat processing time is long.

At this time, the heat treatment time of 30 minutes shown in Figs. 7 and 8 is a region in which the impurity of the epitaxial layer 4 maintains the concentration distribution between the P-type well layer 2 and the N-type bottom layer 7. This is the time for obtaining a structure in which there is no PN junction due to the intersection of impurities between the P-type well layer 2 and the N-type bottom layer 7. That is, generally, in the formation process of the element isolation insulating film 8, heat treatment is performed for about 30 minutes, but at this time, the diffusion of impurities from the semiconductor substrate 1 is performed at a position corresponding to the P-type well layer 2. As a result, a P-type impurity layer is incidentally formed. Here, the resistance of the P-type well layer 2 decreases as the thickness thereof becomes thicker, and the bonding capacity with the N-type bottom layer 7 increases as the junction concentration increases, but in the heat treatment for about 30 minutes, P The type well layer 2 does not become thicker as it crosses the N type bottom layer 7, and the bonding capacity between the type well layer 2 and the N type bottom layer 7 is also smaller, thereby reducing the resistance value of the P type well layer 5. Did not have an effect.

Moreover, the simulation result about the junction capacitance of the P type well layer 2 and the N type bottom layer 7 according to heat processing time is shown in FIG. 9, and the P type well layer 2 and P type well layer 5 and The simulation result about the change of resistivity between and is shown in FIG.

That is, in FIG. 9, the change in the junction capacitance nF / cm ² with respect to the change in the reverse bias voltage V applied to the junction between the P-type well layer 2 and the N-type bottom layer 7 is shown. The characteristics when the heat treatment time is 30 minutes, 150 minutes, 300 minutes, and 400 minutes are indicated by black circles, circles, squares, and triangles, respectively.

Since the depletion layer near the junction increases as the reverse bias voltage increases, the junction capacitance decreases and the junction concentration increases as the time of thermal diffusion increases, so that the junction capacitance increases, and any reverse bias voltage In the case of 400 minutes, it is found that the bonding capacity is the largest, and in the case of 30 minutes, the bonding capacity is the smallest.

In Fig. 10, as a result of simulating a current when a bias voltage is applied to both the bottom of the P-type well layer 2 and the top of the P-type well layer 5, the bias voltage V to be applied is shown. The change in resistivity (Ωcm) against the change is represented by black circles, circles, squares and triangles when the heat treatment time is 30 minutes, 150 minutes, 300 minutes and 400 minutes, respectively. In addition, although the resistivity tends to increase, it can be seen that at any bias voltage, the resistivity is the smallest for 400 minutes and the largest for the 30 minutes.

As described above, when the heat treatment time is set to 150 minutes, 300 minutes, and 400 minutes, the impurity concentration distribution of the epitaxial layer 4 is maintained between the P-type well layer 2 and the N-type bottom layer 7. Although there is no area | region which exists, in other words, when the P type well layer 2 and the N type bottom layer 7 contact, and the impurity of the P type well layer 2 and the N type bottom layer 7 cross | intersects, A novel structure according to the present invention in which a PN junction is formed can be obtained.

At this time, after forming the P-type well layer in combination with the process of forming the element isolation insulating film 8, a conventional process may be performed. For example, the epitaxial layer divided by the element isolation insulating film 8 may be used. Into the inside of the main surface of (3), ion implantation is selectively performed to form N-type well layers 4 and P-type well layers 5 and 6, respectively, and ion implantation is then performed at the bottom of the P-type well layer 6 to form an N-type. The bottom layer 7 is formed. Furthermore, after that, a semiconductor device such as a PMOS transistor MP1 and an NMOS transistor MN1 is placed on the P-type well layer 6 on the N-type well layer 4 and the P-type well layer 5 by a conventional method, respectively. A semiconductor device constituting the memory cell is formed.

<A-4. Effect>

Hereinafter, the operation and effect of the DRAM 100 will be described with reference to FIGS. 1 and 2.

As described above, by thickening the P-type well layer 2, the junction capacitance C1 between the P-type well layer 2 and the N-type bottom layer 7 can be increased, and the power supply wiring in the operation of the sense amplifier can be increased. The voltage drop of WR1 can be reduced.

That is, in the operation of the sense amplifier SA (Fig. 1), by turning on the PM0S transistor MP1, the wiring parasitic capacitance C3 of the sense enable wiring SEp is applied to the power supply wiring WR1 through the PMOS transistor MP1, and temporarily the voltage VDDS (Fig. 2) is lowered.

However, the charge (corresponding to the internal voltage VDD) accumulated in the junction capacitor C1 is the N-type bottom layer 7, the epitaxial layer 3, the N-type well layer 4, the N-type impurity layer 45, and the contact hole. Since the power supply wiring WR1 is given through CH11, the voltage drop of the power supply wiring WR1 can be suppressed and the voltage VDDS can be maintained at a constant value. The current flowing at this time is the current I1 shown in FIG.

Further, by thickening the P-type well layer 2, the distance to the P-type well layer 5 can be shortened, and the resistance R2 of the P-type well layer 5 can be reduced, and the power supply wiring WR2 in the operation of the sense amplifier can be reduced. Voltage rise can be reduced.

That is, in the operation of the sense amplifier SA, by turning on the NMOS transistor MN1, the wiring parasitic capacitance C4 of the sense enable wiring SEn is applied to the power supply wiring WR2 through the NMOS transistor MN1, and the voltage GNDS (Fig. 2) temporarily rises. do.

However, since the resistance R2 of the P-type well layer 5 is smaller, the contact hole CH21, the P-type impurity layer 55, the P-type well layer 5, the epitaxial layer 3, and the N from the power source wiring WR2. A current flows into the semiconductor substrate 1 through the mold well layer 2, thereby suppressing a voltage increase in the power supply wiring WR2 and maintaining the voltage GNDS at a constant value. The current flowing at this time is the current I2 shown in FIG. 1. At this time, the semiconductor substrate 1 is connected to the ground voltage GND.

As described above, in the DRAM 100 according to the first embodiment, the voltage VDDS and the voltage GNDS given to the sense amplifier SA can be maintained at a constant value, so that the driving capability of the transistors constituting the sense amplifier SA can be maintained and the word line The delay time tRCD can be kept short until the word pulse is given to start reading, and then the information on the bit line is sensed and discriminated.

As a result, the operating speed of the sense amplifier SA can be maintained at a value close to the design value, and the degradation of the sense speed can be prevented.

Here, the shortening of the delay time tRCD can be effectively achieved under the conditions shown by the following formulas (2) to (4).

[Number 2]

Rpsub + Rpwell <Rmgnd… (2)

[Number 3]

Rnwell + Rpwell <Rmvdd + Rmgnd... (3)

[Number 4]

Cwell> CD (total)… (4)

In this case, in FIG. 1, although the memory cell is disposed in the region where the P-type well layer 6 is formed (the same as the region where the N-type well layer 2 is formed), the N-type well layer 2 is formed. Even if a circuit having a different function is formed, there is no problem, and the area is not limited to the memory cell area.

In addition, although the example in which the N type bottom layer 7 was arrange | positioned only in the lower part of the P type well layer 6 was shown in FIG. 1, you may arrange | position it below the N type well layer 4. In this case, the thickness of the N-type well layer 4 and the thickness of the p-type well layer 6 are the same, and the N-type bottom layer 7 at the bottom of both layers is configured to be continuous so that the bonding capacity C1 is greatly increased. can do.

In addition, the simulation result of impurity concentration distribution of the substrate depth direction demonstrated using FIG. 7 and FIG. 8 is an example, The film thickness, boron concentration, heat processing time, and heat processing temperature of the epitaxial layer 3 are limited to this example. It doesn't happen.

Although the heat treatment at the time of forming the element isolation insulating film 8 (STI) is used as the heat treatment of the N-type well layer 2, it is needless to say that other heat treatment processes may be used. It can be used as long as it is a step of performing a heat treatment at ° C.

In addition, the N-type well layer 2 may be formed using ion implantation. That is, after the epitaxial layer 3 is formed on the main surface of the semiconductor substrate 1, when the epitaxial layer 3 has a thickness of, for example, 6 mu m, boron is 1x10 at an energy of 4 MeV. ¹³ ~1x10 ¹⁴ / cm ² injected with the dose level and, an epitaxial layer 3 is the is, when the thickness of the boron in the 4㎛ 3MeV energy, ~1x10 ¹⁴ 1x10 ¹³ / cm ² dose level of Inject it with

At this time, the implantation of boron ions may be performed either before or after the formation of STI, but when boron ions are implanted before the formation of STI, fluorine injected mainly by heat treatment during formation of STI diffuses. Simultaneously with the diffusion of boron, the boron atoms which were electrically inert immediately after implantation are activated by moving to the lattice position of the silicon crystal.

In addition, when boron ions are implanted after the formation of the STI, the implanted boron is thermally diffused by the heat treatment performed at the time of formation of the MOSFET and is simultaneously activated. At this time, an example of heat treatment at the time of MOSFET formation includes heat treatment by RTA (RapidThermal Annealing) after source and drain ion implantation. In RTA, for example, in a temperature range of 900 to 1150 占 폚, 0.01 to 5 Second heat treatment is performed.

In this case, the type of substrate is not limited to the semiconductor substrate 1 containing P-type impurities at a relatively high concentration, and may be only an epitaxial layer or a semiconductor substrate containing P-type impurities at a relatively low concentration (P-). In addition, an epitaxial layer or a semiconductor substrate containing N-type impurities may be used.

At this time, a relatively low concentration of P-type impurity (P-) refers to, for example, boron concentration of 1 × 10 ¹⁶ / cm ³ or less, and a relatively high concentration of P-type impurity (P +) of, for example, boron concentration of 1 × 10 ¹⁸ / cm point to ³ or more, a ^{1x10 16 / cm 3 ~1x10 18 /} cm 3 will be briefly referred to as P-type or P ^0.

<A-5. Modification 1>

In the DRAM 100 of the first embodiment according to the present invention described above, as shown in FIG. 1, the thickness of the N-type well layer 2 is the same throughout the entire area, but the DRAM 100A shown in FIG. Similarly, in the formation region of the P-type well layer 5, that is, the NMOS formation region, the N-type well layer 2A whose thickness of the N-type well layer 2 is thicker than the formation region of the N-type well layer 4, that is, the PMOS formation region. ) Is arranged.

At this time, the thickness of the N-type well layer 2A in the memory cell region and the PMOS forming region is d1, and the region having the thickness d1 is referred to as the first region of the N-type well layer. The thickness of the N-type well layer 2A in the NMOS formation region is set to d2, and the region of the thickness d2 is referred to as the second region of the N-type well layer.

In addition, about the same structure as the DRAM 100 shown in FIG. 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

In this manner, by increasing the thickness of the N-type well layer 2A in the NMOS formation region and reducing the distance to the P-type well layer 5, the resistance R2 of the P-type well layer 5 can be further reduced, and the sense In the operation of the amplifier SA, the effect of suppressing the voltage rise of the power supply wiring WR2 is increased, and the voltage GNDS can be maintained at a constant value.

In order to increase the thickness of the N-type well layer 2A in the NMOS formation region, portions other than the NMOS formation region are covered with a resist mask or the like, and ion implantation is selectively performed at a position corresponding to the lower portion of the P-type well layer 5. This can be realized.

That is, as described in Example 1, in the high temperature heat treatment at the time of forming the element isolation insulating film 8, boron is thermally diffused from the semiconductor substrate 1 containing P-type impurities in a relatively high concentration to form NMOS. In portions other than the region, the N-type well layer 2A having a thickness d1 is formed. At this time, the ion implanted boron is also thermally diffused in the NMOS formation region, and two impurity layers are successively mixed with boron thermally diffusing from the semiconductor substrate 1 to form an N-type well layer 2A having a thickness d2.

At this time, the depth of ion implantation is provided in the depth which can mix with the boron thermally diffusing from the semiconductor substrate 1, when the implanted boron thermally diffuses.

Further, all of the N-type well layers 2A may be formed by ion implantation. In this case, it is not limited to the semiconductor substrate 1 which contained P-type impurity in comparatively high concentration, It may be an epitaxial layer or a semiconductor substrate which contains P-type impurity in comparatively low concentration (P-). In addition, an epitaxial layer or a semiconductor substrate containing N-type impurities may be used.

<A-6. Modification 2>

In Example 1 and its modification 1 described above, although the DRAM 100 and the DRAM 100A are formed on the semiconductor substrate 1 which is a bulk substrate, a silicon on insulator (SOI) substrate is used instead of the bulk substrate. The structure may be the same as the DRAM 100B shown in FIG.

That is, in FIG. 12, the N-type well layer 2A is disposed so as to cover the entire main surface of the buried insulating film 11 on the semiconductor substrate 10. In addition, about the same structure as the DRAM 100 shown in FIG. 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

The SOI substrate SO is configured with a buried insulating film 11 disposed on the semiconductor substrate 10 and an epitaxial layer 3 disposed as an SOI layer on the buried insulating film 11.

It goes without saying that the DRAM 100 shown in Fig. 1 may be formed on the SO substrate S0 at this time.

In this case, since the N type well layer 2A is electrically insulated from the semiconductor substrate 10, a configuration for dislocation fixing of the N type well layer 2A is required.

An example of its structure is shown in FIG. In this case, the configuration of the DRAM is omitted in FIG. 13, and only relevant portions are shown.

As shown in Fig. 13, a plug layer 31 having a relatively high concentration of P-type impurities, which penetrates the epitaxial layer 3 from the main surface of the epitaxial layer 3 and reaches the N-type well layer 2A, is provided. It is.

An interlayer insulating film ZL is provided on the epitaxial layer 3, and a contact hole CH10 is formed between the main surface of the interlayer insulating film ZL and penetrates the interlayer insulating film ZL to the plug layer 31. The contact hole CH10 is connected to the wiring WR disposed on the interlayer insulating film ZL. By such a configuration, the potential of the N-type well layer 2A can be reliably fixed.

At this time, the plug layer 31 for fixing the potential is arranged at the stepped portion in the N-type well layer 2A, that is, at the boundary portion between the first region and the second region of the N-type well layer, thereby forming the first region and the first region. The plug layer 31 can be shared by two areas, and compared with the case where the plug layer is provided separately in the first area and the second area, the occupying area can be reduced.

At this time, also in the DRAM 100A shown in FIG. 11, the above-described potential fixing method may be adopted. 14 shows an example thereof.

In FIG. 14, an N-type well layer 2A is provided on a semiconductor substrate 1 containing a relatively high concentration of P-type impurities, and the potential of the N-type well layer 2A is fixed through the semiconductor substrate 1. Although it is possible to do this, the potential fixation can be ensured by making the potential fixation possible even through the plug layer 31.

At this time, the arrangement unit of the plug layer 31 is not limited to the boundary portion between the first region and the second region of the N-type well layer, but may be provided so as to be in contact with the first region and the second region, respectively.

<B: Example 2>

<B-1. Device Configuration>

In Embodiment 1 of the present invention described above, a DRAM has been described as an example. However, the present invention can be applied to any semiconductor device requiring reliable potential fixing, and is limited to power wiring for driving a sense amplifier of a DRAM. It is not.

Thus, the semiconductor device of the second embodiment according to the present invention will be described taking the inverter 200 shown in FIG. 15 as an example.

FIG. 15 is a diagram showing the circuit configuration of the inverter 200, which has four inverters IV1, IV2, IV3 and IV4.

Inverter IV1 has PMOS transistor P31 and NM0S transistor N31, inverter IV2 has PMOS transistor P32 and NMOS transistor N32, inverter IV3 has PMOS transistor P33 and NMOS transistor N33, and inverter IV4 has PMOS transistor P34 and NMOS transistor I have N34.

Of the four inverters, among the inverters IV1 and IV3, the source electrodes of the PM0S transistors P31 and P33 are connected to the power supply wiring WR11, and the respective drain electrodes are connected to the inverter enable wiring VNL.

In one of four inverters, inverters IV2 and IV4 have respective source electrodes of the PM0S transistors P32 and P34 connected to the inverter enable wiring VPL, and each drain electrode connected to the power supply wiring WR12.

The inverters IV1 to IV4 are connected in series, and the signal input from the inverter IV1 is output from the inverter IV4.

Here, the power supply wiring WR11 is a wiring supplied with the internal voltage VDD, which is paired with the inverter enable wiring VPL, and both are electrically connected through the PM0S transistor MP1 which is a driver transistor. The gate electrode of the PMOS transistor MP1 is configured to receive an inverter drive signal / IE.

At this time, the resistor Rp exists between the power supply wiring WR11 and the inverter enable wiring VPL, and the inverter enable wiring VPL has the wiring parasitic capacitance C3.

The power supply wiring WR12 is a wiring to which the ground voltage GND is supplied. The power supply wiring WR12 is paired with the inverter enable wiring VNL, and both are electrically connected through the NMOS transistor MN1 which is a driver transistor. Inverter drive signal IE is provided to the gate electrode of NMOS transistor MN1.

In addition, a resistor Rd exists between the power supply wiring WR12 and the inverter enable wiring VNL, and the inverter enable wiring VNL has a wiring parasitic capacitance C4.

In the inverter 200 having such a configuration, when the input signal during standby is set to Low and the signals of Low and High are given as inverter drive signals IE and / IE during standby, respectively, the NMOS transistor MN1. And the PMOS transistor MP1 is turned off, the voltage of the inverter enable wiring VPL is lower than the internal voltage VDD, and the voltage of the inverter enable wiring VNL is higher than the ground voltage GND. In this state, source voltages of the transistors (here, NMOS transistor N31, PM0S transistor P32, NMOS transistor N33, and PMOS transistor P34) to which an off signal is given as a gate input among inverters IV1 to IV4 are present at high potentials in respective carriers. That is, the source voltage rises, the sub-threshold current decreases, and the standby current can be reduced. At this time, during operation of the inverter 200, the NM0S transistors MN1 and the PM0S transistor MP1 are turned on so that the voltage of the inverter enable wiring VPL and the internal voltage VDD are equal, so that the voltage of the inverter enable wiring VNL becomes the ground voltage GND. Becomes the same as

Here, the resistor Rp and the resistor Rd automatically raise the potential of the inverter enable wiring VPL and the inverter enable wiring VNL with respect to the internal voltage VDD or the ground voltage GND when the sub-threshold current flows in the standby state. It has a function of causing an operation (negative feedback operation) and reducing a standby current.

Next, the cross-sectional structure of the characteristic part of the inverter 200 is shown in FIG.

As shown in FIG. 16, in the inverter 200, a P-type well layer 2 including P-type impurities is disposed on the entire upper surface of the main surface of the semiconductor substrate 1 including P-type impurities at a relatively high concentration (P +). On the P-type well layer 2, an epitaxial layer 3 containing P-type impurities at a relatively low concentration (P-) is disposed.

At this time, although the ratio which the epitaxial layer 3 occupies is small in FIG. 16, in fact, the epitaxial substrate is comprised by the semiconductor substrate 1 and the epitaxial layer 3 about 6 micrometers in thickness, and P The type well layer 2 is disposed inside the main surface of the epitaxial layer 3 simultaneously with the N type well layers 4 and the P type well layers 5 and 6.

In the main surface of the epitaxial layer 3, a P-type well layer 6 containing P-type impurities is selectively disposed, and an N-type containing N-type impurities such that the P-type well layer 6 is interposed therebetween. The well layer 4 and the P type well layer 5 including the P type impurities are selectively disposed.

The thicknesses of the N-type well layer 4 and the P-type well layer 6 are about the same, and an N-type bottom layer containing N-type impurities in the lower portion of the N-type well layer 4 and the P-type well layer 6 so as to contact them. 7A is arrange | positioned. P type well layer 2 is arrange | positioned in the thickness which contact | connects N type bottom layer 7A, and PN junction is formed with N type bottom layer 7A and P type well layer 2.

In the main surfaces of the N-type well layer 4 and the P-type well layer 5, an element isolation insulating film 8 referred to as STI is selectively disposed to define a region for forming the M0S transistor.

At this time, the region of the P-type well layer 6 is also defined by the element isolation insulating film 8, and since the inverter is disposed in this region, it is called an inverter region.

Here, the P-type well layer 2 is a P-type impurity, for example, from the semiconductor substrate 1 containing a relatively high concentration of the P-type impurity in the high temperature heat treatment when forming the device isolation insulating film 8. For example, it is formed by thermally diffusing boron (B).

In the N type well layer 4, a pair of source / drain layers 41 containing a relatively high concentration of P-type impurities are disposed in a region defined by the device isolation insulating film 8, and a pair of source / drain layers 41 is disposed. The gate insulating film 42 is disposed on the N-type well layer 4 between the edges of the opposing edges and between the pair of source / drain layers 41, and the gate electrode 43 is disposed on the gate insulating film 42. It is arranged. The sidewall insulating film 44 is disposed on the side surfaces of the gate insulating film 42 and the gate electrode 43 to form the PMOS transistor MP1. The gate electrode 43 of the PMOS transistor MP1 is configured to receive an inverter drive signal / IE.

In the P-type well layer 5, a pair of source / drain layers 51 containing N-type impurities at a relatively high concentration (N +) are arranged in a region defined by the element isolation insulating film 8, and a pair of sources A gate insulating film 52 is disposed on the P-type well layer 5 between the opposing edge portions of the drain layer 51 and between the pair of source / drain layers 51, and a gate is formed on the gate insulating film 52. The electrode 53 is arranged. The sidewall insulating film 54 is disposed on the side surfaces of the gate insulating film 52 and the gate electrode 53 to form the NM0S transistor MN1. The gate electrode 53 of the NM0S transistor MN1 is configured to receive an inverter drive signal IE.

Here, the region where the PM0S transistor MP1 is formed is called a PMOS forming region, and the region where the NMOS transistor MN1 is formed is called an NMOS forming region.

At this time, an interlayer insulating film (not shown) is disposed to cover the upper portion of the semiconductor substrate 1 including the upper portions of the PMOS transistor MP1 and the NMOS transistor MN1, and various wirings are disposed inside the interlayer insulating film.

That is, one of the pair of source and drain layers 41 is electrically connected to the power supply wiring WR11 through the contact hole CH1 provided in the interlayer insulating film, and the other of the pair of source and drain layers 41 is formed in the interlayer insulating film. It is electrically connected to the inverter enable wiring VPL through the provided contact hole CH3.

In addition, one of the pair of source and drain layers 51 is electrically connected to the power supply wiring WR12 through the contact hole CH2 provided in the interlayer insulating film, and the other of the pair of source and drain layers 51 is in the interlayer insulating film. It is electrically connected to the inverter enable wiring VNL through the provided contact hole CH4.

In addition, an N-type impurity layer 45 containing N-type impurities at a relatively high concentration is selectively provided in the N-type well layer 4, and the power supply wiring WR11 is electrically connected to the N-type impurity layer 45 through the contact hole CH11. Is connected.

Similarly, a P-type impurity layer 55 containing a relatively high concentration of P-type impurities is selectively provided in the P-type well layer 5, and the power supply wiring WR12 is electrically connected to the P-type impurity layer 55 through the contact hole CH21. Is connected.

In this case, various capacitive components and resistive components are schematically described in FIG. 16. That is, the junction capacitance between the P-type well layer 2 and the N-type bottom layer 7 is C11, the wiring parasitic capacitance of the inverter enable wiring VPL is C13, and the wiring parasitic capacitance of the inverter enable wiring VNL is C14, and the N well layer The resistance of (4) is indicated by R11 and the resistance of the P-type well layer 5 as R12. At this time, the N-type bottom layer 7A is connected to the internal voltage VDD in a portion not shown in Fig. 16, and the junction capacitor C11 can accumulate charge corresponding to the internal voltage VDD.

<B-2. Device Behavior>

When the inverter 200 transitions from the standby state to the operating state, it is necessary to make the voltage of the inverter enable wiring VPL equal to the internal voltage VDD and to make the voltage of the inverter enable wiring VNL equal to the ground voltage GND. Since the wiring parasitic capacitance C13 exists in the enable wiring VPL, by turning on the PMOS transistor MP1, the wiring parasitic capacitance C13 is applied to the power supply wiring WR11 through the PMOS transistor MP1, and the electric charge is accumulated in the wiring parasitic capacitance C13, so that the internal voltage VDD is reduced. .

In addition, while the ground voltage GND is supplied to the power supply wiring WR12, but the wiring parasitic capacitance C14 exists in the inverter enable wiring VNL, the wiring parasitic capacitance C14 is applied to the power supply wiring WR12 through the NM0S transistor MN1 by turning on the NMOS transistor MN1. The electric charge accumulated in the wiring parasitic capacitance C14 is given to the power supply wiring WR12, and the ground voltage GND is raised.

As described above, when the internal voltage VDD and the ground voltage GND fluctuate, a problem occurs that the inverters IV1 to IV4 do not operate normally. However, the junction capacitance C11 between the P-type well layer 2 and the N-type bottom layer 7A is increased. By actively using this, this can be prevented.

<B-3. Effect>

Hereinafter, the operation and effect of the inverter 200 will be described with reference to FIGS. 15 and 16.

For the same reason as described in the first embodiment, by thickening the P-type well layer 2, the junction capacitance C11 between the P-type well layer 2 and the N-type bottom layer 7A can be increased, thereby operating the inverter 200. In this case, the voltage drop of the power supply wiring WR11 can be reduced.

That is, in operation of the inverters IV1 to IV4 (FIG. 15), by turning on the PMOS transistor MP1, the wiring parasitic capacitance C13 of the inverter enable wiring VPL is applied to the power supply wiring WR11 via the PM0S transistor MP1, and temporarily, the internal voltage VDD ( 15) is lowered.

However, since the charge accumulated in the junction capacitor C11 is given to the power supply wiring WR11 through the N-type bottom layer 7A, the N-type well layer 4, the N-type impurity layer 45, and the contact hole CH11, the power supply wiring WR11. By suppressing the voltage drop of, the internal voltage VDD can be maintained at a constant value. The current flowing at this time is the current I1 shown in FIG. At this time, the N-type bottom layer 7A is connected to the internal voltage VDD in the portion not shown in FIG.

Further, by thickening the P-type well layer 2, the distance to the P-type well layer 5 can be shortened, and the resistance R12 of the P-type well layer 5 can be reduced, and the power supply wiring WR12 of the sense amplifier can be reduced. Voltage rise can be reduced.

That is, in the operation of the inverters IV1 to IV4, by turning on the NMOS transistor MN1, the wiring parasitic capacitance C14 of the inverter enable wiring VNL is applied to the power supply wiring WR12 via the NM0S transistor MN1, and the ground voltage GND (Fig. 15) temporarily rises. do.

However, since the resistance R12 of the P-type well layer 5 is smaller, the contact hole CH21, the P-type impurity layer 55, the P-type well layer 5, the epitaxial layer 3, and the N from the power source wiring WR12. A current flows into the semiconductor substrate 1 through the type well layer 2, thereby suppressing the voltage rise in the power supply wiring WR12 and maintaining the ground voltage GND at a constant value. The current flowing at this time is the current I2 shown in FIG. At this time, the semiconductor substrate 1 is connected to the ground voltage GND.

As described above, in the inverter 200 of the second embodiment, since the internal voltage VDD and the ground voltage GND given to the inverters IV1 to IV4 can be maintained at a constant value in the transition from the standby state to the operating state, the inverters IV1 to IV4 can operate normally.

At this time, as shown in FIG. 16, the N-type bottom layer 7A of the inverter 200 is provided so as to be continuous to the lower portion of the P-type well layer 6 and the lower portion of the N-type well layer 4. This is a large value.

<C. Application Examples of the Present Invention>

In Examples 1 and 2 described above, an example in which the present invention is applied to a DRAM and an inverter has been described. However, the present invention relates to a semiconductor device in which the potential of the power supply wiring (including the grounding wiring) needs to be kept constant. It is effective for a NAND circuit, a NOR circuit, an XOR circuit, an SRAM memory cell, a transmission gate, a domino logic circuit, and the like. In addition, the circuit system does not supply the internal voltage VDD and the ground voltage GND at the time of activation of any circuits such as analog circuits, RF (Radio Frequency) circuits, digital circuits, and the like. By applying the structure, the same effect is obtained.

In addition, in Example 1, although the structure which hold | maintains the electric potential of the power supply wiring (including earth wiring) of the sense amplifier used for DRAM was shown constant, the structure of a sense amplifier is not limited to the structure shown in FIG. In addition, the application of the present invention is not limited to the sense amplifier used for DRAM.

For example, it can be applied to sense amplifiers mounted in semiconductor devices such as SRAM, flash memory, EEPROM, magnetic random access memory (MRAM), and nitride read only memory (NR0M), and needless to say. .

Here, MRAM is a memory using a magnetic tunnel junction (MTJ) obtained by sandwiching an insulator into two ferromagnetic materials for a memory device, and the direction of magnetization of the two ferromagnetic materials of the magnetic tunnel junction device constituting the memory cell is different. The external magnetic field is controlled so as to be in the same or opposite directions, and data is stored in a manner in which the directions of the magnetizations are the same or in opposite directions to 0 or 1. At this time, data writing is performed by changing the direction of magnetization of one ferromagnetic material by using a magnetic field generated by flowing a predetermined current through the word line and the bit line.

In the NR0M, the portion corresponding to the gate insulating film of the MOS transistor is a multilayer film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film (this is called an ONO film), and a predetermined amount of voltage is applied to the gate electrode. In this state, the voltage to be provided to the drain layer and the voltage to be provided to the source layer are provided to be interchanged with each other. In the silicon nitride film of the ONO film, the memory stores one bit of information in two different places.

This is because electrons accumulated in the silicon nitride film are difficult to diffuse in the silicon nitride film in the transverse direction (gate length direction).

When appropriate voltages are provided to the drain layer and the source layer, information is read out whether or not a channel current flows between the source and the drain. At this time, the voltages provided to the drain layer and the source layer are replaced by whether the storage portion of the information in the silicon nitride film, that is, the presence of electrons is the source layer or the drain layer.

At this time, in erasing the information, while providing a predetermined amount of voltage to the gate electrode, the voltage to be provided to the drain layer and the voltage to be provided to the source layer are alternately provided to introduce holes into the silicon nitride film. The electrons accumulated in the silicon nitride film are erased.

According to the semiconductor device according to one aspect of the present invention, a fifth semiconductor layer of the first conductivity type disposed on the entire inner surface of the second semiconductor surface of the main semiconductor layer is arranged to have a thickness for forming a PN junction with the fourth semiconductor layer. And a junction capacitance between the fifth semiconductor layer and the fourth semiconductor layer, the first power supply wiring is routed through the fourth semiconductor layer and the third semiconductor layer when a voltage drop due to parasitic capacitance occurs in the first power supply wiring. Electric charge can be supplied from the junction capacitance, and the voltage of the first power supply wiring can be maintained at a constant value. In addition, by setting the fifth semiconductor layer to a thickness at which the fourth semiconductor layer and the PN junction are formed, the distance between the fifth semiconductor layer and the second semiconductor layer can be shortened and the resistance value of the second semiconductor layer can be reduced. . As a result, when a voltage rise occurs due to parasitic capacitance in the second power supply wiring, it is easy to extract charges from the second power supply wiring through the second semiconductor layer, and the voltage of the second power supply wiring is kept constant. I can keep it.

According to the semiconductor device according to another aspect of the present invention, since the epitaxial layer is used as the main semiconductor layer, a semiconductor device excellent in operating characteristics can be obtained.

According to the semiconductor device according to another aspect of the present invention, since the main semiconductor layer, which is the SOI layer, is electrically insulated, it is easy to fix the potential of the main semiconductor layer.

According to the semiconductor device according to another aspect of the present invention, since the fourth semiconductor layer is arranged to contact the bottom surface of the third semiconductor layer, the area of the fourth semiconductor layer can be increased to increase the bonding capacity, The voltage of the first power supply wiring can be surely maintained at a constant value.

According to the semiconductor device according to another aspect of the present invention, since the thickness of the second region of the fifth semiconductor layer is arranged so as to protrude in the direction of the second semiconductor layer, the second region is thicker than the thickness of the first region. The distance between the second semiconductor layer and the fifth semiconductor layer is shortened, so that the resistance value of the second semiconductor layer can be further reduced, and it is easier to extract charges from the second power supply wiring through the second semiconductor layer. Thus, the voltage of the second power supply wiring can be reliably maintained at a constant value.

According to the semiconductor device according to another aspect of the present invention, since the fifth semiconductor layer is fixed to the second voltage by the plug layer in contact with the boundary between the first region and the second region of the fifth semiconductor layer, Compared with the case where the plug layer is provided separately in the region and the second region, the occupied area is reduced.

According to the semiconductor device according to another aspect of the present invention, by maintaining the voltage of the first and second power supply wiring at a constant value, the driving ability of the transistors constituting the sense amplifier is not reduced, and the information on the bit line is sensed. The delay time to discrimination can be kept short, and the fall of the sense speed of a sense amplifier can be prevented.

According to the semiconductor device according to another aspect of the present invention, the inverter can be operated normally by maintaining the voltages of the first and second power supply wirings at a constant value.

According to the method of manufacturing a semiconductor device according to one aspect of the present invention, a substrate having a relatively high concentration of impurities of the first conductivity type is heated for 30 minutes or more in a temperature range of 900 ° C to 1200 ° C, thereby providing a first conductivity in the semiconductor substrate. Since the fifth semiconductor layer is formed by diffusing the impurities of the die, the fifth semiconductor layer can be easily formed.

According to the method of manufacturing a semiconductor device according to another aspect of the present invention, the step (b) serves to selectively form an element isolation insulating film inside the first main surface of the main semiconductor layer. Compared with the case of using, a process can be simplified.

According to the semiconductor device manufacturing method according to another aspect of the present invention, since the heating time of the semiconductor substrate is from 150 minutes to 400 minutes, the fifth semiconductor layer is reliably at a thickness for forming the PN junction with the fourth semiconductor layer. Can be formed.

According to the semiconductor device manufacturing method according to another aspect of the present invention, since the fifth semiconductor layer is formed by ion implantation, controllability such as the thickness of the fifth semiconductor layer is good.

Claims (3)

A main semiconductor layer of a first conductivity type disposed on the entire main surface of the semiconductor substrate and having a plurality of wiring layers disposed thereon; A first semiconductor layer of a first conductivity type selectively disposed inside a first main surface of the main semiconductor layer; A second conductive layer of a first conductive type and a second conductive type selectively disposed in the first main surface of the main semiconductor layer adjacent to the first semiconductor layer so as to sandwich the first semiconductor layer therebetween A third semiconductor layer, A fourth semiconductor layer of the second conductivity type selectively disposed in the main semiconductor layer below the first semiconductor layer so as to be in contact with at least a bottom surface of the first semiconductor layer; A fifth semiconductor layer of a first conductivity type disposed on the entire inner surface of the second main surface of the main semiconductor layer, The fifth semiconductor layer is disposed to a thickness that forms a PN junction with the fourth semiconductor layer, and has a bonding capacity between the fifth semiconductor layer and the fourth semiconductor layer. The plurality of wiring layers, A first power supply wire to which a first voltage is supplied; Has a second power supply wiring to which a second voltage lower than the first voltage is supplied; The third semiconductor layer is electrically connected to the first power supply wiring, And the second semiconductor layer is electrically connected to the second power supply wiring. A main semiconductor layer of a first conductivity type disposed on the entire main surface of the semiconductor substrate and having a plurality of wiring layers disposed thereon; A first semiconductor layer of a first conductivity type selectively disposed inside a first main surface of the main semiconductor layer; A second conductive layer of a first conductive type and a second conductive type selectively disposed in the first main surface of the main semiconductor layer adjacent to the first semiconductor layer so as to sandwich the first semiconductor layer therebetween A third semiconductor layer, A fourth semiconductor layer of the second conductivity type selectively disposed in the main semiconductor layer below the first semiconductor layer so as to be in contact with at least a bottom surface of the first semiconductor layer; In the manufacturing method of a semiconductor device comprising a fifth semiconductor layer of a first conductivity type disposed on the entire inner surface of the second main surface of the main semiconductor layer, (a) preparing a substrate having a relatively high concentration of impurities of a first conductivity type as said semiconductor substrate, (b) After forming the main semiconductor layer on the entire main surface of the semiconductor substrate, and before forming the first to fourth semiconductor layers, the semiconductor substrate is 30 minutes in a temperature range of 900 ℃ to 1200 ℃ And a step of diffusing the first conductive type impurity in the semiconductor substrate to form the fifth semiconductor layer by the above heating. A main semiconductor layer of a first conductivity type disposed on the entire main surface of the semiconductor substrate and having a plurality of wiring layers disposed thereon; A first semiconductor layer of a first conductivity type selectively disposed inside a first main surface of the main semiconductor layer; A second conductive layer of a first conductive type and a second conductive type selectively disposed in the first main surface of the main semiconductor layer adjacent to the first semiconductor layer so as to sandwich the first semiconductor layer therebetween A third semiconductor layer, A fourth semiconductor layer of the second conductivity type selectively disposed in the main semiconductor layer below the first semiconductor layer so as to be in contact with at least a bottom surface of the first semiconductor layer; In the manufacturing method of a semiconductor device comprising a fifth semiconductor layer of a first conductivity type disposed on the entire inner surface of the second main surface of the main semiconductor layer, After the main semiconductor layer is formed on the entire main surface of the semiconductor substrate, and before forming the first to fourth semiconductor layers, the first conductive type impurities are ion implanted over the entire surface of the main semiconductor layer, And a step of forming the fifth semiconductor layer.