WO1996035997A1 - Processeur parallele - Google Patents

Processeur parallele Download PDF

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Publication number
WO1996035997A1
WO1996035997A1 PCT/RU1996/000127 RU9600127W WO9635997A1 WO 1996035997 A1 WO1996035997 A1 WO 1996035997A1 RU 9600127 W RU9600127 W RU 9600127W WO 9635997 A1 WO9635997 A1 WO 9635997A1
Authority
WO
WIPO (PCT)
Prior art keywords
sοedinen
maτρitsy
vχοdοm
uπρavleniya
elemenτοv
Prior art date
Application number
PCT/RU1996/000127
Other languages
English (en)
Russian (ru)
Inventor
Gennady Ivanovich Bacherikov
Viktor Ivanovich Gevorkyan
Original Assignee
Yalestown Corporation N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yalestown Corporation N.V. filed Critical Yalestown Corporation N.V.
Priority to PCT/RU1996/000127 priority Critical patent/WO1996035997A1/fr
Publication of WO1996035997A1 publication Critical patent/WO1996035997A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Definitions

  • the invention is available to the computer and is intended for use in high-speed systems of large data processing.
  • the product purchased as a part of the process has an inadequate speed of exchange with external devices, limited speed and non-negligibility.
  • the task of the present invention is to create a process with a faster performance, which ensures the simultaneous execution of small programs.
  • This task is achieved by the fact that a well-known process, containing the first and second buffers, the control unit, the counting of the address, and the running speed of the process, ⁇ tsess ⁇ ny ⁇ elemen ⁇ v, ⁇ azhdy of ⁇ y ⁇ s ⁇ edinen s ⁇ ve ⁇ s ⁇ vuyuschimi v ⁇ dami and vy ⁇ dami with s ⁇ sednimi ⁇ tsess ⁇ nymi elemen ⁇ ami ma ⁇ itsy, v ⁇ dy and vy ⁇ dy ⁇ y ⁇ b ⁇ az ⁇ vany s ⁇ ve ⁇ s ⁇ vuyuschimi ⁇ dn ⁇ imennymi v ⁇ dami and vy ⁇ dami ⁇ ayni ⁇ ⁇ tsess ⁇ ny ⁇ elemen ⁇ v, ⁇ ichem ⁇ e ⁇ vy and v ⁇ y vy ⁇ dy bl ⁇ a u ⁇ avleniya s ⁇ edineny s ⁇ v ⁇
  • FIG. 1 a structured circuit of the declared parallel process with a process unit based on a nine process unit is presented;
  • Fig. 2 shows a structural diagram of a primary element on a single computing structure; on fig.Z - structural diagram of the block of the initial download;
  • Fig. 4 shows a structural diagram of a control unit;
  • Fig. 5 shows the structured circuit of a parallel computer on the basis of the declared parallel circuitry with a parallel structure;
  • the proposed process contains a matrix of 17 process elements 1, 9-16, first 2 and second 3 buffers, a block of 4 controls, and a quick shutdown of 5
  • Each of the process elements 1, 9-16 is connected with the corresponding inputs and outputs with the adjacent * process elements. All five outputs of the matrix 17 through the corresponding outputs of the process elements 1, 9 are connected to the outputs of all the other process elements 10-16.
  • the outputs of the matrix 17 are actual, and this program input is intended for entering the program into the process elements 1, 9 - 16, and the output is in the open mode
  • the output of matrix 17 is intended for issuing an initialization signal for operation of unit 4 of the control.
  • the output of the matrix 17 initiates the download of the program (program) in the matrix.
  • the fourth output of the matrix 17 gives the initial address of the recorded or downloaded program.
  • the fifth output of the matrix 17 is intended for the issuance of a responsive storage device 6 write or read mode.
  • Each cell 18-26 has a single output, one that allows input and output and a few inlets and outlets.
  • ⁇ se ⁇ g ⁇ ammnye v ⁇ dy-vy ⁇ dy yachee ⁇ 18-26 ⁇ dn ⁇ g ⁇ ⁇ tsess ⁇ n ⁇ g ⁇ elemen ⁇ a 1, 9 - 16 ⁇ sled ⁇ va ⁇ eln ⁇ s ⁇ edineny d ⁇ ug with d ⁇ ug ⁇ m and che ⁇ ez ⁇ g ⁇ ammny v ⁇ d s ⁇ ve ⁇ s ⁇ vuyuscheg ⁇ ⁇ tsess ⁇ n ⁇ g ⁇ elemen ⁇ a - with ⁇ dnim of ⁇ az ⁇ yad ⁇ v ⁇ e ⁇ v ⁇ g ⁇ egis ⁇ a 2 za ⁇ isi ⁇ g ⁇ ammy ⁇ ⁇ dn ⁇ y ⁇ mande in ⁇ azhduyu yachey ⁇ u.
  • Each process element 1, 9-16 is connected to the control unit of each cell 18-
  • All cells 18-26 are syncronized from the general generator (not shown), this is done by each team at a time.
  • the data in the investigation without bias for the bit is transmitted to the neighboring cells or issued to the outside for communication with external memory devices 36-39 or external devices 40-43.
  • the outputs and outputs of cells 18-26 are intended to perform the following functions:
  • the informational inputs and outputs serve for the transmission of information in a thorough manner from the other industrial process to the other.
  • Unit 7 of the initial download contains a single vibrator 27, which operates when the power is turned on, the resistor 28 and the power supply 29 are connected.
  • Block 4 of the control (Fig. 4) consists of a count of 30 and a permanent memorizing device 31, which contains a temporary record.
  • the outputs of unit 4 are connected to the corresponding discharges of the standard device 31.
  • the counter 30 is triggered by the signal from the unit 7 of the initial load 17 or 1.
  • a successive alarm switch ensures that the timing diagrams are read and signals are sent to the corresponding outputs.
  • the outputs and outputs of unit 4 of the control perform the following functions: - Startup is intended for starting up power supply unit 4 and turning on the power;
  • the initialization input is intended to initialize the operation of unit 4 of the control
  • initiation - input of initiation - is appropriate for initiating the download of the program (program) in the matrix 17;
  • the first output is intended for issuing a control signal to a permanent memorizing device 5;
  • the second output is intended for issuing a control signal to a portable memorizing device 6;
  • the proposed device operates the following way.
  • Block 4 of the control for the boot signal from the block 7 of the initial boot or for the signal from the output of the matrix 17 records the initial address of the executed memory of the process.
  • the simultaneous second register 3 with an output of the matrix 17 is recorded information, in which case the elements 1, 9-16 will be recorded.
  • each of cells 18-26 receives its own command.
  • Block 4 of the control unit gives a signal to stop the input of the program, after which the second program 3 is reset to "0", which means that the process starts in the process, it means that the process
  • the first part of the process, which is part of the process element, is the part of the initial boot process, which ensures the connection of the process with other process components and external devices. Further, the change and start-up of the program takes place at the expense of the process, the process of the element or external devices (in particular, the other process).

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)

Abstract

Cette invention peut trouver des applications dans les systèmes informatiques à grande vitesse de traitement en temps réel de flux importants de données. Le processeur parallèle comprend une unité (7) de charge initiale, une unité de commande (4), un premier (2) et un second (3) registres tampons, des unités de mémoire permanente (5) et opérationnelle (6), un compteur (8) d'adresses, ainsi qu'une matrice (17) d'éléments de processeur (1, 9 à 16), lesquels se présentent chacun sous forme d'une matrice de cellules de calcul uniformes. Lors du fonctionnement d'un système informatique faisant appel à ce processeur, il est possible d'effectuer simultanément plusieurs programmes avec une vitesse importante d'échange de données entre les unités de mémoire, les autres processeurs et les dispositifs externes. La rapidité de fonctionnement de ce processeur permet d'effectuer des centaines de milliards d'opérations à la seconde.
PCT/RU1996/000127 1996-05-22 1996-05-22 Processeur parallele WO1996035997A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/RU1996/000127 WO1996035997A1 (fr) 1996-05-22 1996-05-22 Processeur parallele

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/RU1996/000127 WO1996035997A1 (fr) 1996-05-22 1996-05-22 Processeur parallele

Publications (1)

Publication Number Publication Date
WO1996035997A1 true WO1996035997A1 (fr) 1996-11-14

Family

ID=20129998

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU1996/000127 WO1996035997A1 (fr) 1996-05-22 1996-05-22 Processeur parallele

Country Status (1)

Country Link
WO (1) WO1996035997A1 (fr)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4858177A (en) * 1987-03-27 1989-08-15 Smith Harry F Minimal connectivity parallel data processing system
US4873626A (en) * 1986-12-17 1989-10-10 Massachusetts Institute Of Technology Parallel processing system with processor array having memory system included in system memory
EP0485690A2 (fr) * 1990-11-13 1992-05-20 International Business Machines Corporation Système à processeur associatif parallèle
EP0495537A2 (fr) * 1983-05-31 1992-07-22 W. Daniel Hillis Processeur parallèle
US5152000A (en) * 1983-05-31 1992-09-29 Thinking Machines Corporation Array communications arrangement for parallel processor
US5157785A (en) * 1990-05-29 1992-10-20 Wavetracer, Inc. Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit
EP0544127A2 (fr) * 1991-11-27 1993-06-02 International Business Machines Corporation Système d'ordinateur dynamique à architecture parallèle multimode en forme de réseau
EP0557997A2 (fr) * 1992-02-28 1993-09-01 Hitachi, Ltd. Appareil et système de traitement d'information
EP0570741A2 (fr) * 1992-05-22 1993-11-24 International Business Machines Corporation Commande pour un réseau de processeurs SIMD/MIMD
DE4416881A1 (de) * 1993-05-13 1994-11-17 Martin Vorbach Datenverarbeitungseinrichtung

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0495537A2 (fr) * 1983-05-31 1992-07-22 W. Daniel Hillis Processeur parallèle
US5152000A (en) * 1983-05-31 1992-09-29 Thinking Machines Corporation Array communications arrangement for parallel processor
US4873626A (en) * 1986-12-17 1989-10-10 Massachusetts Institute Of Technology Parallel processing system with processor array having memory system included in system memory
US4858177A (en) * 1987-03-27 1989-08-15 Smith Harry F Minimal connectivity parallel data processing system
US5157785A (en) * 1990-05-29 1992-10-20 Wavetracer, Inc. Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit
EP0485690A2 (fr) * 1990-11-13 1992-05-20 International Business Machines Corporation Système à processeur associatif parallèle
EP0544127A2 (fr) * 1991-11-27 1993-06-02 International Business Machines Corporation Système d'ordinateur dynamique à architecture parallèle multimode en forme de réseau
EP0557997A2 (fr) * 1992-02-28 1993-09-01 Hitachi, Ltd. Appareil et système de traitement d'information
EP0570741A2 (fr) * 1992-05-22 1993-11-24 International Business Machines Corporation Commande pour un réseau de processeurs SIMD/MIMD
DE4416881A1 (de) * 1993-05-13 1994-11-17 Martin Vorbach Datenverarbeitungseinrichtung

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