WO2009008078A1 - 半導体記憶装置及びシステム - Google Patents

半導体記憶装置及びシステム Download PDF

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Publication number
WO2009008078A1
WO2009008078A1 PCT/JP2007/063855 JP2007063855W WO2009008078A1 WO 2009008078 A1 WO2009008078 A1 WO 2009008078A1 JP 2007063855 W JP2007063855 W JP 2007063855W WO 2009008078 A1 WO2009008078 A1 WO 2009008078A1
Authority
WO
WIPO (PCT)
Prior art keywords
address
redundant
memory device
semiconductor memory
selecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/063855
Other languages
English (en)
French (fr)
Inventor
Hiroyuki Kobayashi
Daisuke Kitayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to JP2009522476A priority Critical patent/JP4957800B2/ja
Priority to KR1020107000341A priority patent/KR101125953B1/ko
Priority to PCT/JP2007/063855 priority patent/WO2009008078A1/ja
Publication of WO2009008078A1 publication Critical patent/WO2009008078A1/ja
Priority to US12/683,029 priority patent/US7933159B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)

Abstract

　半導体記憶装置は、メモリセル配列と、冗長要素と、切り替え信号に応じて複数のアドレスから１つのアドレスを冗長アドレスとして選択するアドレス指定部と、外部から入力されるアドレスがアドレス指定部の選択する冗長アドレスに一致すると冗長要素を選択するデコーダ回路と、外部からの入力に応じて切り替え信号を変化させることにより冗長要素に割り当てる冗長アドレスを変更可能に構成されるテストモード設定回路を含む。
PCT/JP2007/063855 2007-07-11 2007-07-11 半導体記憶装置及びシステム Ceased WO2009008078A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009522476A JP4957800B2 (ja) 2007-07-11 2007-07-11 半導体記憶装置及びシステム
KR1020107000341A KR101125953B1 (ko) 2007-07-11 2007-07-11 반도체 기억 장치 및 시스템
PCT/JP2007/063855 WO2009008078A1 (ja) 2007-07-11 2007-07-11 半導体記憶装置及びシステム
US12/683,029 US7933159B2 (en) 2007-07-11 2010-01-06 Semiconductor memory device and system with redundant element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/063855 WO2009008078A1 (ja) 2007-07-11 2007-07-11 半導体記憶装置及びシステム

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/683,029 Continuation US7933159B2 (en) 2007-07-11 2010-01-06 Semiconductor memory device and system with redundant element

Publications (1)

Publication Number Publication Date
WO2009008078A1 true WO2009008078A1 (ja) 2009-01-15

Family

ID=40228275

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/063855 Ceased WO2009008078A1 (ja) 2007-07-11 2007-07-11 半導体記憶装置及びシステム

Country Status (4)

Country Link
US (1) US7933159B2 (ja)
JP (1) JP4957800B2 (ja)
KR (1) KR101125953B1 (ja)
WO (1) WO2009008078A1 (ja)

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US9047978B2 (en) 2013-08-26 2015-06-02 Micron Technology, Inc. Apparatuses and methods for selective row refreshes
JP2015219938A (ja) 2014-05-21 2015-12-07 マイクロン テクノロジー， インク． 半導体装置
KR20160004585A (ko) * 2014-07-03 2016-01-13 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
JP2017182854A (ja) 2016-03-31 2017-10-05 マイクロン テクノロジー， インク． 半導体装置
US10490251B2 (en) 2017-01-30 2019-11-26 Micron Technology, Inc. Apparatuses and methods for distributing row hammer refresh events across a memory device
US10580475B2 (en) 2018-01-22 2020-03-03 Micron Technology, Inc. Apparatuses and methods for calculating row hammer refresh addresses in a semiconductor device
CN112106138B (zh) 2018-05-24 2024-02-27 美光科技公司 用于行锤击刷新采样的纯时间自适应采样的设备和方法
US11152050B2 (en) 2018-06-19 2021-10-19 Micron Technology, Inc. Apparatuses and methods for multiple row hammer refresh address sequences
US10685696B2 (en) 2018-10-31 2020-06-16 Micron Technology, Inc. Apparatuses and methods for access based refresh timing
CN113168861B (zh) 2018-12-03 2024-05-14 美光科技公司 执行行锤刷新操作的半导体装置
CN117198356A (zh) * 2018-12-21 2023-12-08 美光科技公司 用于目标刷新操作的时序交错的设备和方法
US10957377B2 (en) 2018-12-26 2021-03-23 Micron Technology, Inc. Apparatuses and methods for distributed targeted refresh operations
US10770127B2 (en) 2019-02-06 2020-09-08 Micron Technology, Inc. Apparatuses and methods for managing row access counts
US11615831B2 (en) 2019-02-26 2023-03-28 Micron Technology, Inc. Apparatuses and methods for memory mat refresh sequencing
US11043254B2 (en) 2019-03-19 2021-06-22 Micron Technology, Inc. Semiconductor device having cam that stores address signals
US11227649B2 (en) 2019-04-04 2022-01-18 Micron Technology, Inc. Apparatuses and methods for staggered timing of targeted refresh operations
US11264096B2 (en) 2019-05-14 2022-03-01 Micron Technology, Inc. Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits
US11158364B2 (en) 2019-05-31 2021-10-26 Micron Technology, Inc. Apparatuses and methods for tracking victim rows
US11069393B2 (en) 2019-06-04 2021-07-20 Micron Technology, Inc. Apparatuses and methods for controlling steal rates
US11158373B2 (en) 2019-06-11 2021-10-26 Micron Technology, Inc. Apparatuses, systems, and methods for determining extremum numerical values
US10832792B1 (en) 2019-07-01 2020-11-10 Micron Technology, Inc. Apparatuses and methods for adjusting victim data
US11139015B2 (en) 2019-07-01 2021-10-05 Micron Technology, Inc. Apparatuses and methods for monitoring word line accesses
US11386946B2 (en) 2019-07-16 2022-07-12 Micron Technology, Inc. Apparatuses and methods for tracking row accesses
US10943636B1 (en) 2019-08-20 2021-03-09 Micron Technology, Inc. Apparatuses and methods for analog row access tracking
US10964378B2 (en) 2019-08-22 2021-03-30 Micron Technology, Inc. Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation
US11200942B2 (en) 2019-08-23 2021-12-14 Micron Technology, Inc. Apparatuses and methods for lossy row access counting
US11302374B2 (en) 2019-08-23 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic refresh allocation
US11302377B2 (en) 2019-10-16 2022-04-12 Micron Technology, Inc. Apparatuses and methods for dynamic targeted refresh steals
KR102697631B1 (ko) 2019-10-28 2024-08-23 삼성전자주식회사 리페어 단위를 가변하는 메모리 장치 및 그것의 리페어 방법
US11309010B2 (en) 2020-08-14 2022-04-19 Micron Technology, Inc. Apparatuses, systems, and methods for memory directed access pause
US11380382B2 (en) 2020-08-19 2022-07-05 Micron Technology, Inc. Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
US11348631B2 (en) 2020-08-19 2022-05-31 Micron Technology, Inc. Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
US11222682B1 (en) 2020-08-31 2022-01-11 Micron Technology, Inc. Apparatuses and methods for providing refresh addresses
US11557331B2 (en) 2020-09-23 2023-01-17 Micron Technology, Inc. Apparatuses and methods for controlling refresh operations
US11222686B1 (en) 2020-11-12 2022-01-11 Micron Technology, Inc. Apparatuses and methods for controlling refresh timing
US11462291B2 (en) 2020-11-23 2022-10-04 Micron Technology, Inc. Apparatuses and methods for tracking word line accesses
US11264079B1 (en) 2020-12-18 2022-03-01 Micron Technology, Inc. Apparatuses and methods for row hammer based cache lockdown
US11482275B2 (en) 2021-01-20 2022-10-25 Micron Technology, Inc. Apparatuses and methods for dynamically allocated aggressor detection
US11600314B2 (en) 2021-03-15 2023-03-07 Micron Technology, Inc. Apparatuses and methods for sketch circuits for refresh binning
US11664063B2 (en) 2021-08-12 2023-05-30 Micron Technology, Inc. Apparatuses and methods for countering memory attacks
US11688451B2 (en) 2021-11-29 2023-06-27 Micron Technology, Inc. Apparatuses, systems, and methods for main sketch and slim sketch circuit for row address tracking
US12597459B2 (en) 2021-12-29 2026-04-07 Micron Technology, Inc. Apparatuses and methods for row hammer counter mat
US12165687B2 (en) 2021-12-29 2024-12-10 Micron Technology, Inc. Apparatuses and methods for row hammer counter mat
US12125514B2 (en) 2022-04-28 2024-10-22 Micron Technology, Inc. Apparatuses and methods for access based refresh operations
US12112787B2 (en) 2022-04-28 2024-10-08 Micron Technology, Inc. Apparatuses and methods for access based targeted refresh operations
US12592271B2 (en) 2022-12-22 2026-03-31 Micron Technology, Inc. Apparatuses and methods for increased reliability row hammer counts

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06150689A (ja) * 1992-11-10 1994-05-31 Nec Corp 半導体メモリ
JPH07288078A (ja) * 1994-03-31 1995-10-31 Sgs Thomson Microelectron Inc ヒューズ焼切をエミュレート可能なヒューズ回路
JPH0935493A (ja) * 1995-07-15 1997-02-07 Toshiba Corp 半導体メモリ装置、マイクロコントローラ及び半導体メモリ装置の製造方法
JPH09251797A (ja) * 1996-03-18 1997-09-22 Fujitsu Ltd 半導体記憶装置、その救済方法及びその試験方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06163704A (ja) 1992-11-25 1994-06-10 Hitachi Ltd 半導体装置
JPH06243698A (ja) 1993-02-19 1994-09-02 Hitachi Ltd 半導体記憶装置
JPH06275095A (ja) * 1993-03-18 1994-09-30 Fujitsu Ltd 半導体記憶装置及び冗長アドレス書込方法
JPH07153296A (ja) * 1993-11-26 1995-06-16 Nec Corp 半導体記憶装置
JP3774500B2 (ja) * 1995-05-12 2006-05-17 株式会社ルネサステクノロジ 半導体記憶装置
JPH10326496A (ja) * 1997-05-26 1998-12-08 Hitachi Ltd 半導体記憶装置
JP3189886B2 (ja) * 1997-10-30 2001-07-16 日本電気株式会社 半導体記憶装置
JP3594891B2 (ja) * 2000-09-12 2004-12-02 沖電気工業株式会社 半導体記憶装置およびその検査方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06150689A (ja) * 1992-11-10 1994-05-31 Nec Corp 半導体メモリ
JPH07288078A (ja) * 1994-03-31 1995-10-31 Sgs Thomson Microelectron Inc ヒューズ焼切をエミュレート可能なヒューズ回路
JPH0935493A (ja) * 1995-07-15 1997-02-07 Toshiba Corp 半導体メモリ装置、マイクロコントローラ及び半導体メモリ装置の製造方法
JPH09251797A (ja) * 1996-03-18 1997-09-22 Fujitsu Ltd 半導体記憶装置、その救済方法及びその試験方法

Also Published As

Publication number Publication date
US7933159B2 (en) 2011-04-26
KR20100028099A (ko) 2010-03-11
JP4957800B2 (ja) 2012-06-20
KR101125953B1 (ko) 2012-03-22
US20100110809A1 (en) 2010-05-06
JPWO2009008078A1 (ja) 2010-09-02

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