V Questions with… DAMO Academy’s Dr. Jianyi Meng
Alibaba DAMO Academy Chief Scientist Dr. Jianyi Meng on what it took to achieve an on-chip AI milestone for RISC-V, and his hopes for RISC-V Summit China 2026.
Project Snapshot Building on the long-standing use of programmable system-on-chips (SoCs) for edge computing in other domains, this work explores their early adoption in application-specific…
Alibaba DAMO Academy Chief Scientist Dr. Jianyi Meng on what it took to achieve an on-chip AI milestone for RISC-V, and his hopes for RISC-V…
How I went from three assigned milestones to shipping the ISA Configuration Builder and the Extension Sandbox One of the things I love most about…
Codethink's Paul Sherwood shares his experience on how automakers lose control of software, and how open standards like RISC-V restore independence.
There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in…
Maven Silicon CEO P R Sivakumar on using RISC-V to bridge the skills gap, building a stronger engineering community and preparing new talent for an…
Project Snapshot The Monte Cimone project is a RISC-V-based testbed for High-Performance Computing (HPC) clusters. This work presents Monte Cimone v3 (MCv3), the third iteration…
'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign…
MIPS’ Sameer Wasson explains why an automotive OEM’s choice of instruction set architecture (ISA) should prioritize supplier choice, software reuse and long-term economic control.
Project Snapshot This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V…
EDACrux, offered free to the RISC-V ecosystem, serves to demonstrate how success is built upon our members’ commitment to openness.
Project Snapshot Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified…
There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in…
EDACrux, offered free to the RISC-V ecosystem, serves to demonstrate how success is built upon our members’ commitment to openness.
Having spent much of my career flying the flag for B2B tech, I know that belief in the thing you’re championing runs deeper than commercial…
Voting is now open for RISC-V International's Board of Directors. Learn how to nominate, understand board member responsibilities, and discover key election dates.
The RISC-V Ratified Specifications Library consolidates all of the available RISC-V specifications into one single, accessible repository.
Ahead of Embedded World, we explore what our members and co-exhibitors will showcase in Nuremberg, the common threads linking their work, and what this reveals…
Porting Software to RISC-V (LFD114) is our free course for experienced engineers who need to move performance-critical software to RISC-V.
The newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
At RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
The eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
Alibaba DAMO Academy Chief Scientist Dr. Jianyi Meng on what it took to achieve an on-chip AI milestone for RISC-V, and his hopes for RISC-V…
How I went from three assigned milestones to shipping the ISA Configuration Builder and the Extension Sandbox One of the things I love most about…
Codethink's Paul Sherwood shares his experience on how automakers lose control of software, and how open standards like RISC-V restore independence.
Maven Silicon CEO P R Sivakumar on using RISC-V to bridge the skills gap, building a stronger engineering community and preparing new talent for an…
'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign…
MIPS’ Sameer Wasson explains why an automotive OEM’s choice of instruction set architecture (ISA) should prioritize supplier choice, software reuse and long-term economic control.
Developer and RISC-V Mentee Animesh Agarwal talks us through what he learned during his time on placement at Ventana Micro, and how it changed how…
In this blog, Krste Asanović explains why in 2026, the state of the RISC-V union isn't just strong: it's stronger than ever.
Verification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently.
I have just returned from the 2025 RISC-V Industry Development Conference, held across Zhuhai and Macau. Guided by the 2025 theme “Accelerating Standardization, Facilitating Connection”…
I’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in…
By setting a clear, stable standard, the RVA23 profile’s ratification is spurring top vendors to align on a common RISC-V hardware goal. All we need…
Alibaba DAMO Academy Chief Scientist Dr. Jianyi Meng on what it took to achieve an on-chip AI milestone for RISC-V, and his hopes for RISC-V…
Maven Silicon CEO P R Sivakumar on using RISC-V to bridge the skills gap, building a stronger engineering community and preparing new talent for an…
'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign…
Project Snapshot Building on the long-standing use of programmable system-on-chips (SoCs) for edge computing in other domains, this work explores their early adoption in application-specific…
Project Snapshot The Monte Cimone project is a RISC-V-based testbed for High-Performance Computing (HPC) clusters. This work presents Monte Cimone v3 (MCv3), the third iteration…
Project Snapshot This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V…
Project Snapshot Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified…
Project Snapshot This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9), enabling always-on, real-time, energy-efficient edge…
Project Snapshot Community-maintained Docker packages bring v29 to RISC-V64 within days of official release, not months. Fully automated pipelines compile natively on RISC-V hardware, delivering…
Project Snapshot How does performance modeling accelerate real hardware innovation in open RISC-V designs? In this paper, Thales demonstrates a performance model of the CVA6…
Project Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is…
AI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Project Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…