One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
In this blog, Krste Asanović explains why in 2026, the state of the RISC-V union isn't just strong: it's stronger than ever.
Developer and RISC-V Mentee Animesh Agarwal talks us through what he learned during his time on placement at Ventana Micro, and how it changed how…
Porting Software to RISC-V (LFD114) is our free course for experienced engineers who need to move performance-critical software to RISC-V.
AI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
In this blog, Krste Asanović explains why in 2026, the state of the RISC-V union isn't just strong: it's stronger than ever.
And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
Verification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently.
I have just returned from the 2025 RISC-V Industry Development Conference, held across Zhuhai and Macau. Guided by the 2025 theme “Accelerating Standardization, Facilitating Connection”…
Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
I’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in…
The newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
Porting Software to RISC-V (LFD114) is our free course for experienced engineers who need to move performance-critical software to RISC-V.
The newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
At RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
The eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
Risky Systems’ Bob Jones explains why the company’s latest core is set to revolutionize the AI SoC market, and how it intends to use it…
RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two days of keynotes, technical sessions, workshops, and demos.
Summary Under the theme “RISC-V: The Future of Open Hardware and Innovation,” the event brought together industry leaders, researchers, and tech enthusiasts for a full…
Summary Despite a bit of rainy weather, the Tokyo RISC-V community came together at a local restaurant for a lively evening of conversation, networking, and…
Summary A small but spirited crowd in Bangalore came together to dive into RISC-V’s future in the region—exploring RISC-V on FPGA, discussing where the local…
Summary World RISC-V Day Beijing brought the community together for a high-energy, high-impact celebration of open computing. With 200+ attendees onsite and 5,400+ participants joining…
And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
The 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
We explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Author: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
With IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
By Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
By: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
The RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
AI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Project Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…
Project Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…
Project Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering…
Project Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs.…
Project Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the…
Project Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and…
Greg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V…
TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
Introduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to…
And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
The 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
We explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Author: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
With IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
By Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
By: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
The RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…