The Final Verification Frontier: How We Battle-Hardened RISC-V for Space
Verification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently.
And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
newelectronics: Quintauris and Vector have partnered to integrate MICROSAR Classic into the RT-EUROPA real-time RISC-V automotive platform, giving developers a faster, standards-compliant path to building…
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
Verification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently.
I have just returned from the 2025 RISC-V Industry Development Conference, held across Zhuhai and Macau. Guided by the 2025 theme “Accelerating Standardization, Facilitating Connection”…
Channel Life: The IoT semiconductor market is heading into a major shift by 2026, driven by the mainstream adoption of edge AI, the rise of…
Electronic Design: Although the RISC-V Summit North America 2025 has concluded, viewers can still explore many of the keynotes and sessions now available online. William…
Semiconductor Engineering: AI continues to migrate towards the edge and is no longer confined to the data center. Edge AI brings several key advantages, delivering…
Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Andes: d-Matrix and Andes have partnered to integrate Andes’ high-performance AX46MPV RISC-V CPU IP into d-Matrix’s next-generation Raptor accelerator, the first to feature 3D In-Memory…
EDN: RISC-V adoption in automotive applications is accelerating, with new partnerships and certified processor cores enabling software-defined vehicles and safety-critical systems. Collaborations among Quintauris, Andes,…
WebProNews: RISC-V International has achieved Publicly Available Specification (PAS) Submitter status from ISO/IEC JTC1, marking a major step toward international standardization of its open instruction…
The newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
At RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
The eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
Risky Systems’ Bob Jones explains why the company’s latest core is set to revolutionize the AI SoC market, and how it intends to use it…
RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two days of keynotes, technical sessions, workshops, and demos.
A Note From Our CEO Welcome to the latest RISC-V newsletter, my first as the new CEO at RISC-V International. I’m incredibly excited to step…
In this episode of Embedded Insiders, we’re joined by RISC-V’s newest CEO, Andrea Gallo, who outlines his vision for the company’s future. From accelerating ecosystem growth…
As RISC-V turns 15, we explore how a summer grad project became the official compute architecture of nations – and why its story is just…
RISC-V International and the RISE Project are teaming up to participate in the Yocto Project. RISC-V International has upgraded from Silver to a Platinum membership…
RISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June…
And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
The 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
We explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Author: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
With IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
By Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
By: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
The RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Project Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…
Project Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…
Project Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering…
Project Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs.…
Project Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the…
Project Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and…
Greg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V…
TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
Introduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to…
Tammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During…
And the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
The 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
We explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Author: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
Introduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
by Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
With IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
By Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
By: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
The RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
newelectronics: Quintauris and Vector have partnered to integrate MICROSAR Classic into the RT-EUROPA real-time RISC-V automotive platform, giving developers a faster, standards-compliant path to building…
Channel Life: The IoT semiconductor market is heading into a major shift by 2026, driven by the mainstream adoption of edge AI, the rise of…
Electronic Design: Although the RISC-V Summit North America 2025 has concluded, viewers can still explore many of the keynotes and sessions now available online. William…
Semiconductor Engineering: AI continues to migrate towards the edge and is no longer confined to the data center. Edge AI brings several key advantages, delivering…
Andes: d-Matrix and Andes have partnered to integrate Andes’ high-performance AX46MPV RISC-V CPU IP into d-Matrix’s next-generation Raptor accelerator, the first to feature 3D In-Memory…
EDN: RISC-V adoption in automotive applications is accelerating, with new partnerships and certified processor cores enabling software-defined vehicles and safety-critical systems. Collaborations among Quintauris, Andes,…
WebProNews: RISC-V International has achieved Publicly Available Specification (PAS) Submitter status from ISO/IEC JTC1, marking a major step toward international standardization of its open instruction…
EEWorldOnline: MIPS has begun sampling its new I8500 processor, a scalable, multithreaded data movement processor IP designed for real-time, event-driven computing across hyperscale, automotive, industrial,…
EDN: At RISC-V Summit North America 2025, industry leaders unveiled the latest advances in CPU cores, vector processors, and AI-powered designs shaping the next wave…
Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors. In a…
Google Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI…
Annual RISC-V Summits, organized by RISC-V International, serve as vital hubs for innovation, writes SemiWiki's Daniel Nenni.