Personal Data
- Username:
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estool
- Joined:
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2010-06-11 04:24:21
Projects
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Gen CSRs
Control/Status Register (CSR) Generator for FPGA and ASIC
Last Updated:
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PLP
Powerfull pre-processor
Last Updated:
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SmGen
Verilog Finite State Machine (FSM) Code Generator
Last Updated:
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