1

EL 302
Digital Integrated Circuits

Lab3
Positive Edge Triggered D Flip-Flop
With Asynchronous Set and Reset

E.Selin Baytok
8088





27.04.2007





Purposes:

Designing a CMOS positive (rising) edge triggered master-slave type D Ilip-Ilop with a low-asserted
asynchronous set and reset using AMS 0.35 m CMOS technology according to the Iollowing criteria:

Clock signal parameters: trise tIall 100 ps, duty cycle 50 and Iclk(min) 1 GHz.
Output load 50 IF.
Standard cell layout.



2


1. Introduction

Flip Flops are employed as storage elements in synchronous circuits. This element operates according
to the clock edge, depending on the design its output changes on the rising (positive) or Ialling (negative) edge
oI the clock signal and keeps the data during the clock cycle.



Fig 1 Transition Table oI D-Flip-Flop Fig 2 D-Flip-Flop

2. Schematic Design

2.1. Topology Selection

In order to design a positive edge triggered d Ilip Ilop master-slave conIiguration was used. In this
conIiguration two latches composed oI two back-to-back inverters were cascaded with opposite clock signs.
When clock makes its transition Irom low to high, d input is passed into the Ilip Ilop. Since the slave latch is
blocked by the low clock signal data is kept in the master latch. At negative edge oI the clock slave latch
becomes transparent and the stored data is sent to output Q.


Fig 3 Synchronous Master-Slave ConIiguration Fig 4 Transition Through One Clock Cycle

Since asynchronous set and reset Iunctions are required Ior this design back-to-back inverters were turned into
nand gates in order to be able to change the output instantaneously when an asynchonous set or reset data is
asserted. Nor gates could also be employed but it was not preIerred because oI its lower speed and assymetric,
large layout. As asynchronous inputs set and reset signals are to be 'anded, they should be low asserted in
order to change the output reagardless oI the value kept in Ilip Ilop.
3

Fig 5 Asynchronous Master-Slave ConIiguration



2.2. Design Parameters

According to the topology chosen nand gates design in the previous laboratory were implemented and nmos
transistor size to be used as pass gates were chosen to be the same with the nand gate nmos size in order to
make the design compatible with the other elements like inverter in layout stage. Final nmos size value was
4.1u and pmos value was 3.7u Ior the overall circuit.


Fig 6 Schematic View oI D-Flip Flop


3. Layout Design

In this part it was tried to achieve minimum area Ior the layout according to the standard cell procedure. The
only problem here were the cross connections. They were increasing the crosses oI metal1 layer on poly
layers thereIore metal2 layer was to be applied Ior the input connections. Final layout dimension was 28u X
19.6u
4


Fig 7 Final Layout Design oI D-Flip Flop

4. Measurements

4.1. Propagation Delay, Rise Time and Fall Time of the Output
In order to measure the rise and Iall time oI the D-Ilip Ilop circuits in the Figure 6 and 8 were used. Signals
provided Ior measurement are as Iollows:

D Clk Clk-not Set Reset
Source Type Vpulse Vpulse Vpulse Vdc Vdc
Voltage Range 0:3.3V 0:3.3V 3.3:0V 3.3V 3.3V
Period 2ns 1ns 1ns - -

Table 1 Measurement Inputs

Fig 8 Schematic oI Test Circuit Ior Extracted Version
5


4.1.1 Schematic Results



Fig 9 Transient Analysis oI D-Flip Flop, High-to-low and Low-to High delays respectively

4.1.2 Extracted Version Results



Fig 10 Transient Analysis oI D-Flip Flop, High-to-low and Low-to High delays respectively

4.2. Total power dissipation

Current was making peaks at the clock transitions. By keeping output toggling throughout measurement with
the inputs in Table 1, total current driven by the circuit was plotted.With the help oI calculator in Cadence the
rms value oI the current was calculated as the average current and it was multiplied by 3.3V Vdd to Iind the
overall power dissipation.



6
4.2.1 Schematic Results



Fig 11 Current,D, Clock Signals oI Schematic

4.2.2 Extracted Version Results


Fig 12 Clock, D, CurrentSignals oI Extracted Version

4.3. Set Function and Set-to-Output Time

Unlike the previous case set option was made Iunctional by eliminating input. ThereIore it was
directly observed at the output.In order to test whether set Iunction is asynchronous it was asserted
during the clock cycle.It was cheked that the output was rising to logic 1 when set is asserted.
Set-to-Output time was measured Irom 50 oI set signal to the 50 oI the response.
Signals provided Ior measurement are as Iollows:

7
D Clk Clk-not Set Reset
Source Type Vdc Vpulse Vpulse Vpulse Vdc
Voltage Range 0V 0:3.3V 3.3:0V 3.3:0V 3.3V
Period - 1ns 1ns 10ns -

Table 2 Measurement Inputs

4.3.1 Schematic Results



Fig 13 Clock, D, Q and Set Signals oI Schematic

4.3.2 Extracted Version Results



Fig 14 Clock, D, Q and Set Signals oI Extracted Version
8
4.4. Reset Function and Reset-to-Output Time

Similar to set Iunction input was eliminated and the reset option is tested by applying the Iollowing signals:
D Clk Clk-not Set Reset
Source Type Vdc Vpulse Vpulse Vdc Vpulse
Voltage Range 3.3V 0:3.3V 3.3:0V 3.3V 3.3:0V
Period - 1ns 1ns - 10ns
Table 3 Measurement Inputs

It was observed that the output was lower down to logic 0 anytime reset signal is asserted. Reset-to-Output time
was measured Irom 50 oI reset signal to the 50 oI the response.

4.4.1. Schematic Result


Fig 15 Clock, D, Q and Reset Signals oI Schematic

4.4.2. Extracted Version Result


Fig 16 Clock, D, Q and Reset Signals oI Extracted Version
9
4.5. Setup Time

In order to measure setup time in extraceted version, a delay is given to the input signal when the other
signal are as in table1. The minimum time period Ior the input signal to be asserted beIore the positive edge oI
the clock was measured such that iI the signal is given 1ps later the output would be altered as in Figure 17.


Fig 17 Clock, D, Q and Q-not Signals oI Extracted Version

4.6. Hold Time

By adjusting the delay, the input to the system is pushed beyond the clock signal`s positive edge. A time
interval which will the input should be kept the same aIter the positive clock edge is searched. But no matter
how close the input signal to the clock signal is no Ialse output is generated.It is concluded as zero hold time
Ior the extracted version oI D-Ilip Ilop.


Fig 18 Clock , D , Q and Q-not Signals oI Extracted Version
10

5. Tests for Compatibility

5.1. Consecutive Flip Flops

Since this Ilip Iop is to be used in more than one amount in more complex circuits also with other elements.
It was required to test the element whether it is going to be Iunctioning at 1 GHz when it is combined
consecutively. The test schematic is included as Figure 19.

Fig 19 Two Consecutive D- Flip Flop Test Circuit



Fig 20 Transient Analysis oI Consecutive D-Flip Flops, High-to-low and Low-to High
Delays respectively

5.2. Combined Layouts

It is veriIied that Ilip Ilops can be placed back to bak and upside down together in a layout as in Fig 21.

11


Fig 21 Compatibility Test Ior D-Flip Flop Layout

6. Discussion

Schematic Extracted Consecutive
Trise 233.7ps 257.4ps 230.9ps
Tfall 265.4ps 293 ps 269ps
Tpropagation 249.55ps 275.2ps -
Power Dissipation 1.366 mW 1.821mW -
Set-To-Output Time 214.3ps 207ps -
Reset-To-Output Time 477.5ps 491.9ps -
Tsetup - 193.8ps -
Thold - 0 -

Table 4 Data measured Irom Schematic and Extracted version

As the propagation time values are observed it is seen that extracted version is slower than the schematic
version. It should have been because the parasitic eIIects rooted Irom layout design dominated the time gained
by nand gates.
Increase in power dissipation in extracted version should be because oI the long junction layers and parasitic
eIIects in the layout design.
As it was expected set-to-output time was measured smaller than that oI reset-to-output time since reset signal
has to propagate through two nand and one pass gate to aIIect the output while set signal only passes through
one nand gate to the output.
When two Ilip Ilops were placed consecutively the output signal seemed to be quicker that may be because oI
the output oI the Iirst Ilip Ilop and the input oI the second Ilip Ilop was becoming narrower on propagation
thereIore the second Ilip Ilop will be introduced logic 1 Ior a shorter period oI time, leading to a quicker
transition.