Binary Adder cum Subtractor

Vivek Modi
Registration number – 11401966
RE2407B30
Department of Electronics and Communication
Lovely Professional University
Phagwara, Punjab
vivekmodi1991@gmail.com

Abstract— Today, all gadget and smart machine are become The below the logical expression and figure of the Half
smaller and smarter because of it’s an era of device adder. We can also built a full adder using with or without half
miniaturization and smart performance. The only way to give a adder.
smart performance is to perform a two or more individual
operations are done by one circuit. This document tells about an
overview of the addition and subtraction operations can be
combined into one circuit with one common binary adder by
including a discrete gate with each full-adder and circuit can be
performing.

Index Terms—adder & full adder, subtractor and full

subtractor, combine adder cum subtractor, result and discussion,
conclusion, references.

I. INTRODUCTION
As the demand grow for the very High Performance and high
density integrated circuit. So every logical circuits are dump into the But in this term we discuss about only full adder. As we
single chip. So now all things are talks about the digital circuits. know that we can built a full adder using with a half adder or
In digital circuits, there are the two types of the circuit (I) without using with a half adder. Below the diagram of the Full
sequential circuit (II) combinational circuit. A developer can be adder[2].
decide which types of circuit, they want to work or design. To
talk about an adder–subtractor is a circuit that is capable and
performing of adding or subtracting numbers (in particular,
binary). One circuit can be depict that does adding or
subtracting task depending on a control signal. It is also a
possible to construct a circuit that performs both addition and
subtraction at the same time[1][8].
II. BASIC OF ADDER
In the processor, there are several number of blocks to
perform a various types of operation for drive the computer or
any embedded system. Each block contain a different types of
circuits. So we concern about the ALU(arithmetic and logical
unit). A unit a computer which carries out arithmetic and
logical operations.
In electronics, an adder or summer is a digital circuit that
performs addition of numbers. Adder are a part of the core of III. BASIC OF SUBTRACTOR
an arithmetic logic unit(ALU). The control unit decides which Subtraction is a mathematical operation that represents the
operations an ALU should perform (based on the op code operation of removing objects from a collection. And here in
being executed) and sets the ALU operation. The basic thing is VLSI field we mention as a Subtrator[4].
Half adder. The Half adder is an illustration of a simple, First, we discuss about the Half subtrator and then we can
functional digital circuit built from two logic gates. The Half go for Full subtractor. A Half subtractor can be designed using
adder adds to one bit binary numbers(AB). The output is the the same concept as that of a Half adder.
sum of the two bits (S) and the Carry (C). Note how the same In electronics, as a same way the concept of the subtractor
two inputs are directed to two different gates[6]. is same like adder. But only difference is put an one additional
inverter gate before two gate as see in the figure. A subtractor Now in next part, we discus in 4-bit adder cum subtractor.
can be designed using the same approach as that of an adder. Below the fig the main function is select line M.
There are two major parameter that one is difference between
the two binary number and second one is borrow[2]. M Operation
0 Addition
1 Subtraction

Now to talk about the full subtractor. We can write a

expression in below As we know that we can built a full-
subtractor using with a half subtractor or without using with a
half subtractor. Below the diagram of the Full subtractor[2].

M: controller, adding when M=0 and Subtracting when M=1.

Adding: A+B. Sub: A-B. V: overflow flag, denote that an
overflow happened when V=1[5].
Let us start with a making a Adder cum Subtractor using with

The full-subtractor is a combinational circuit which is used to

perform subtraction operation using with three bits.
D=X-Y-Z
B=1 if X<(Y+Z)

IV. ADDER CUM SUBTRACTOR

In digital electronics, everything should be in single chip.
So this thing is only happened due to device miniaturization. In
above both topics has a individually content and each block can
perform only one operation. Now to talk about the both things
in a single block. We talk about a one single block which can
be perform a both operation simultaneously with help of the
select line M.[7]
The addition and subtraction can be combined into one
circuit with one common binary adder. The mode M controls Fig. 1 Schematic for inverter gate.
the operation. During the operation, If M=0 then circuit is an
adder or if M=1 then circuit is subtractor. It can be done by Cadence Virtuoso and cadence 180nm Technology. Then, first
using exclusive-OR for each Bit and M[5]. start with cadence virtuoso tools. It’s a very costly tools.
In this case, for simplicity I consider the only single bit First, we design the full adder. If we design an full adder then
operation. So it’s easy to perform and easy to understand. we need of some logic gates. Like XOR, AND and OR. First
requirement is to design this logic gates and then using with
this gates we can built a full adder circuit.
Below the Fig 1 is that schematic for inverter gate.

Fig. 4 Test-bench for XOR gate.

Next, we design the remain the two more logic gates for
future purpose. And then we can build a full adder circuit.

Fig. 2 Test-bench for inverter gate.

And also fig 2 is a test-bench for inverter gate. Which can

be perform an operation with respect to the apply input.

Fig. 5 Schematic for AND gate.

Fig. 3 Schematic for XOR gate.

Here, the fig 3 depicted that the schematic for XOR gate
and we used the inverter gate before the output. And the below
the fig 4 for test-bench in terms of WOR gate. Fig. 6 Test-bench for AND gate.
 Fig. 10 Test-bench for FULL ADDER.

Fig. 7 Schematic for OR gate.

Fig. 8 Test-bench for OR gate. Fig. 11 Output waveform for FA.

Fig. 9 Schematic for FULL ADDER using with gates.. Fig. 12 output waveform for FA.
 The snapshots of Schematic for full adder are shown in Fig
11 and Fig 12 for single bit operation.

Fig. 15 Test-bench for 4-BIT ADDER cum SUB using with

FA and XOR gates.

V. RESULTS AND DISCUSSION

The adder cum subtractor circuit based on CMOs logic gates.
And found out that the input parameter can be change with
Fig. 13 Layout fig of 4-BIT ADDER CUM SUBT. respect to time then the output changes i.e. if M=0 then
performing the Addition and M=1 then performing the
Above fig mention that the 4-Bit adder cum subtrator using Subtraction as shown in Figure16,17 and 18.
with single bit full adder and put an external XOR gate for
selecting the operation which can be represent a M.
As a starting point of the topic, for simplicity we consider
only a single bit adder cum subtractor. And then after we have
two option for designing the full adder cum subtractor.
(1) we can built an adder cum subtrator using with single bit
adder cum subrator. And
(2) we can built an adder cum subtrator using with full adder
and XOR gate as mention below the figure 14.

Fig. 16 Output for 4-BIT ADDER cum SUB using with FA

and XOR gates.
The power and delay specifications obtained from above
analysis are provided in table1.
Table 1.
Sl. Specification (W/L)ratio µm Power Delay
No.

1 Adder cum (W/L)n=2/0.18 31.7µW 6.8nsec

subtravtor (W/L)p=2.5/0.18

Fig. 14 Schematic for 4-BIT ADDER cum SUB using with

FA and XOR gates.
 From the calculated value of power consumption and delay,
it can be inferred that the adder cum subtractor based up on the
full adder circuit has lesser power consumption. But lesser
performance in terms of delay because of trade-off in speed
power product that can be very negligible.
CONCLUSION
First thing is this operation is a part of ALU. In this term
we are discussing a only adder cum subtractor operation. But
inside the ALU has more number of task which can be
perform by a processor. So If u increase the more number of
input bit then also increase a time to perform the operation. So
we can increase the clock frequency then the performance is
faster in terms of large number of input.
REFERENCES
[1] Malvino, “Digital computer electronics.” Third edition.
[2] Samir palnitakar, “Verilog HDL” second edition.
[3] S.M.Kang, Y.Leiblibici, “CMOS Digital Integrated Circuits”,
Tata McGraw-Hill Education,2003
Fig. 17 Output for 4-BIT ADDER cum SUB using with FA [4] Basic of subtractor. http://www.ustudy.in/node/3036
and XOR gates. [5] Islamic University of Gaza Faculty of Engineering Department
of Computer Engineering Fall 2011 ECOM 4113: Digital
Design LAB Eng. Ahmed Abumarasa
[6] Wikipedia free encyclopedia.
[7] M.V Subramanyam, “Switching theory and logic design”
Google Book.
[8] M. Morris Mano, Michael D Ciletti, “Digital Design” fifth
edition Pearson edition

Fig. 18 Output for 4-BIT ADDER cum SUB using with FA

and XOR gates.