Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
(RACE-2014), 28-29 March 2014
1
CMOS Based Design Simulation Of
Adder /Subtractor Using Different Foundries
Ranjeeta Verma
1
, Rajesh Mehra
2
1 2
Department of Electronics and Communication Engineering
1
ME Scholar, NITTTR, Chandigarh - 160019
2
Associate Professor, NITTTR, Chandigarh - 160019
1
ranjeeta.verma.singhal@gmail.com
Abstract- In this paper a 4 bit parallel adder/subtractor circuit has been designed and analyzed. The circuit uses a
controlled adder/subtractor circuit which converts the negative numbers into their 2s complement. A comparative study
of the silicon area and the power consumption has been done in the circuit using different channel lengths such as 65nm,
45nm. The circuit is designed and simulated using DSCH schematic tool and the layout is developed by Microwind VLSI
CAD Tool. The designed circuit has shown a remarkable reduction in the consumed power of 93% and a reduction of
49% in consumed area in 45nm foundry as compared to 65nm foundry. The simulation has been done using BSIM4
device modeling.
Keywords - Full Adders, Full Subtractors, Controlled Inverters, CMOS.
I. INTRODUCTION
Addition forms the basis for many processing operations, from counting to multiplication to filtering. As a result,
adder circuits are of great interest to digital system designers. Adders and Subtractors are important components
in the applications like Digital Signal Processing (DSP)architectures. For signal processing, digital full-adder and
full-subtractor are the basic logic circuits which can find applications in digital computing and packet labels
processing [1]. Addition is the most basic arithmetic operation; and adder is the most fundamental arithmetic
component of the processor [2]. The rapid increase in the number of transistors on chips has enabled a dramatic
increase in the performance of computing systems [3]. Computations need to be performed using low- power, area-
efficient circuits operating at greater speed [2].
The design criterion of a full adder cell is usually multi-fold. Transistor count is, of course, a primary concern
which largely affects the design complexity of many function units such as multiplier and algorithmic logic unit
(ALU). The limited power supply capability of present battery technology has made power consumption an
important figure in portable devices [2]. The power consumption in a CMOS digital circuit can be calculated using
Eq.1. Whether it is a general-purpose system or an application specific processor, addition is by far the most frequently
used operation.[4]
P = f
CV
dd
2
+ fI
off
V
dd
+ I
off
V
dd
(1)
Full Adders - A full Adder is a cominational circuit that performs addition of two bits taking into consideration
about a 1 that may have generated by the previous stage as shown in Figure (1). The circuit has 3 inputs A,B, Cin
and two outputs S and Cout. The inputs A and sum B are the bits to be added and Cin is the carry from the previous
stage while S is the output sum and Cout is the output carry as in Eq.2 and Eq. 3.
Sum = A B Cin (2)
Cout= (A.B) +(Cin .(AB)). (3)
Proceedings of National Conference on Recent Advances in Electronics and Communication
Engineering (RACE-2014), 28-29 March 2014
2
Figure 1. Full Adder
Full Subtractors - A full subtractor is a combinational circuit that performs a subtraction between two bits taking
into account that a 1 may have been borrowed by a lower significant stage[3] shown in figure(2).
Figure 2. Full Subtractor
The circuit has 3 inputs A, B ,BOR
IN
and two outputs D and BOR
OUT
. The inputs A, B, BOR
IN
are the minuend,
subtrahend and previous stage borrow respectively while D is the output Difference and BOR
OUT
is the output
Borrow as in Eq.4 and Eq. 5.
BOR
OUT
= BOR
IN
(AB + AB) + AB (4)
Difference = A B BOR
IN
(5)
In this paper a unified adder/subtracter circuit has been analyzed which performs the addition as well as subtraction
of two 4 bit binary numbers. The circuit also detects the overflow if occurs in case the sum exceeds the permissible
limit of the circuit.
II. ADDER/ SUBTRACTOR CIRCUIT
In this paper a 4 bit unified parallel adder/subtractor circuit with a overflow detector is analyzed. Subtraction of
two binary numbers can be accomplished by adding 2s complement of the subtrahend to the minuend [5] shown in
figure(3).
Figure 3. 4 bit paralel adder-subtractor
The circuit uses 4 units of full adders and a separate XOR gate is used to detect any overflow in the circuit.This
circuit performs both the operations of addition as well a subtraction. The bits of the binary number B
3
B
2
B
1
B
0
are
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
(RACE-2014), 28-29 March 2014
3
fed to the controlled inverter which is a XOR gate.The 4 bit binary number A
3
A
2
A
1
A
0
is
added to a 4 bit binary
number B
3
B
2
B
1
B
0
when the mode control bit M is
in logic 0 state. When the input M is in logic state1 then the
binary number B
3
B
2
B
1
B
0
in the present state gets complemented. If the same 1 is also fed in the carry in of the LSB
Full adder then the 2s complement of binary number B3B2B1B0 is added
to the binary number A
3
A
2
A
1
A
0.
The
output of the circuit
in this case is the subtration of the two numbers that is A-B.This circuit also indicates the
occurrence of the Overflow if the output exceeds the permissible limit of the circuit. The carry out C
3
from third full
adder stage and the carry out C
4
from fourth full adder stage is given as input in the XOR gate to give the overflow.
The output OVERFLOW of the circuit gives a logic 1 if overflow occurs, else it remains in the 0 state.
III. SCHEMATIC DESIGN SIMULATION
The schematic design of the 4 bit composite parallel adder-subtractor is shown in figure (4) and is drawn in DSCH
tool and its working is verified in accordance to its truth table.If the control iput M is low then the circuit behaves
as an Adder and when it is High the circuit behaves as a Subtractor. The subtraction operation is converted into
addition by complementing the minuend by passing it through the XOR. If a result of an n-bit addition does not fall
within the allowed range, then an arithmetic overflow occurs.[6]. The controlled input M modifies the behavior of
circuit according to Table1.
Figure 4. gatel level schematic of adder-subtractor
Table 1 : Behaviour of Circuit
M Behaviour of circuit
0 Adder
1 Subtractor
The ciicuit behaviour for input conditions
a. B
3
B
2
B
1
B
0
as 1111 and A
3
A
2
A
1
A
0
as 1101 for M as 1 is shown in Figure 5.
Proceedings of National Conference on Recent Advances in Electronics and Communication
Engineering (RACE-2014), 28-29 March 2014
4
Figure 5. Timing Diagram for a.
The output Sum S
3
S
2
S
1
S
0
is 1110 and the output carry C
4
C
3
C
2
C
1
is 0001.
b. B
3
B
2
B
1
B
0
as 1111 and A
3
A
2
A
1
A
0
as 0101 for M as 0 is shown in Figure 6.
Figure 6. Timing Diagram for b.
The output Sum S
3
S
2
S
1
S
0
is 0100 and and the output carry is 1111. This verifies the working of the circuit.
The simulation of the schematic is done in the DSCH tool. The VERILOG File is generated and then this file is
compiled in the Microwind Tool to obtain its physical layout.The simulation of the circuit is performed using the
BSIM4 model.The Berkeley Short- Channel IGFET Model (BSIM) is a very elaborate model that is now widely
used in circuit simulation.[7].
IV. RESULTS AND DISCUSSIONS
Decrease in power consumption in digital circuits is of major concern as it improves the battery life. Power
consumption issues can lead to over consumption of resources when devices are cascaded [8]. This power reduction
will produce an overall inceased delay.
This section presents the layout and analog simulations of the dicussed circuit under different foundries such as
65nm and 45 nm adder-subtractor. The analog simulation is performed using Microwind Lite 3.1 tool.
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
(RACE-2014), 28-29 March 2014
5
Figure 7 Layout of 65 nm CMOS 4 bit Adder-Subtractor
The circuit is simulated and compared for performance. using this tool. Figure 7. Shows the layout of 65nm CMOS
4 bit adder-subtractor
Figure 8. Analog simulation of circuit in 65nm Foundry.
The analog simulation of the circuit in 65 nm CMOS Technology is shown in Figure 8.The simulations are used to
analyze and compare the performance of the circuits.
Figure 9 . Layout of 45 nm CMOS 4 bit Add-Sub
Figure 9 shows the layout of 45nm CMOS 4 bit adder-subtractor. The layout shows the various metals layers and the
polysilicon gate and their interconnections through via. The pMOS or the pull up network is shown at the top and
the nMOS or the pull down network is shown at the bottom in the layout.
Proceedings of National Conference on Recent Advances in Electronics and Communication
Engineering (RACE-2014), 28-29 March 2014
6
Figure 10. Analog simulation of circuit in 45nm Foundry
Analog simulation of 4 bit adder subtractor in 45 nm foundry is shown in figure 10.The schematic of the circuit is
designed and tested in DSCH 3.1 and then its VERILOG file is generated which is further compiled to obtain the
analog simulation in the Microwind 3.1 Tool.
The analysis of the area and power consumption by the circuit is also performed by the Microwind designing Tool.
The performance comparison between area and power of CMOS 4 bit adder-subtractor based on 65nm and 45nm,
foundries is performed .The circuit is designed using 65nm and 45nm channel lengths and have layout width and
height of 48.9m/16.1m and 35.0m/11.5m respectively.
TABLE 2. Comparative Study of Power and Area
Parameter 65nm 45nm
Area(m
2
) 787.8 401.9
Power(W) 50.222 2.937
Figure 11.. Graphical Comparison ofArea and Power
0
100
200
300
400
500
600
700
800
65nm 45nm
Area(m2)
Power(W)
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
(RACE-2014), 28-29 March 2014
7
The comparison of area and power consumption in 4 Bit Adder-Subtractor design based on different channel lengths
is summarized in Table 2. The graphical analysis makes it clear that the area consumed by the 4 bit Adder-
Subtractor circuit is minimum for the 45nm CMOS Technology. Area consumption by 65 nm CMOS Technology
is reduced by 51% as compared to 90 nm CMOS Technology. The analysis also shows that the power consumed
by the 45nm CMOS Technology is minimum. Power consumption of 65nm foundry is reduced by 94% as compared
to 90nm CMOS Technology.
V. CONCLUSION
This paper studies the effect of various channel lengths on the power and area consumption of a 4 bit adder-
subtractor circuit with overflow detection. The composite 4 bit Adder- Subtractor circuit is used instead of separate
adder subtract circuit which saves resources. The power consumed by the composite circuit in 65nm and 45nm
foundries is 50.22 W and 2.937 W respectively. The area consumed by the composite circuit in 65nm, 45nm,
channel lengths is 787.8 m
2
and 401.9 m
2
respectively.
VI. REFERENCES
[1] L. Lei, J. Dong, Y. Zhang, H. He, Y. Yu and X. Zhan, Reconfigurable photonic full-adder and full-subtractor based on three-input XOR gate
and logic minterms in ELECTRONICS LETTERS March 2012 Vol. 48 No. 7.
[2] M.B. Damle, Dr. S.S Limaye, M.G. Sonwani, Comparative Analysis of Different Types of Full Adder Circuits IOSR Journal of Computer
Engineering (IOSR-JCE) - ISSN: 2278-8727Volume 11, Issue 3 , 2013, PP 01-09.
[3] Milind Gautam, Shyam Akashe, Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique, International
Conference on Computer Communication and Informatics , pp. 1-4 Jan 2013.
[4] Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens Area-Time-Power Tradeoffs in Parallel Adders IEEE Transactions On
Circuits And Systems ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 10, OCTOBER 1996
.
[5] Digital Electronics, Principles, Devices and Applications, by Anil. K. Maini pp 245-246.
[6] Sayeeda Sultana and Katarzyna Radecka, Reversible Adder/ Subtractor with Overflow Detector in Proc. Of 54
th
International Midwest
Symposium on Circuits and Systems,pp. 1-4 2011.
[7] N. Weste and David Harris,Ayan Banerjee, CMOS VLSI Design, Third Edition pp 22-23.
[8] Anjali Sharma,Rajesh Mehra, Low Level TG Full Adder Design Using CMOS Nano Technology 2
nd
IEEE International Conference on
Parallel, Distributed and Grid Computing, pp. 210-213, 2012.
