L10: Analog Building Blocks

(OpAmps, A/D, D/A)

Acknowledgement:
Materials in this lecture are courtesy of the following sources and are used with permission.
Dave Wentzloff

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 Introduction to Operational Amplifiers

DC Model „ Typically very high input

resistance ~ 300KΩ
+ Rin „ High DC gain (~105)
a ⋅ vid Rout
vid vout „ Output resistance ~75Ω
−
Vout = a ( f ) ⋅ Vin

LM741 Pinout a(f)

+10 to +15V

10 5 -20dB/
Reprinted with
permission of
National
Semiconductor
decade
Corporation.

-10 to -15V f
Reprinted with permission of National Semiconductor Corporation. 10Hz
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 The Inside of a 741 OpAmp
Reprinted with
permission of Differential Current Source Additional
National
for biasing Gain Stage Output Stage
Semiconductor
Corporation. Input Stage

Output devices
provides large
drive current

Bipolar version
has small input
Bias current

MOS OpAmps
have ~ 0 input
current

Gain is Sensitive to Operating Condition

(e.g., Device, Temperature, Power supply voltage, etc.)
Reprinted with permission of National Semiconductor Corporation.

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 Simple Model for an OpAmp

VCC vout VCC = 10V

i+ ~ 0
+
vid +
- - + -100μV
vid
i- ~ 0 vout ε = 100μV
-
-VCC -VCC = -10V
Reasonable
approximation

Linear Mode Negative Saturation Positive Saturation

+ + + + + +
vid + +
vid +
- avid vout - -VCC vout vid - +VCC vout
- - - - - -

If -VCC < vout < VCC vid < - ε vid > ε

Small input range for “Open” loop Configuration

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 The Power of (Negative) Feedback

R1 R2 R1 R2
-
vout - +
vin +
+ vin + vid +
- - - avid vout
+ -

vin + vid vout + vid v vin vout ⎡1 a 1⎤

+ =0 vid = out =− ⎢ + + ⎥
R1 R2 a R1 a ⎣ R1 R2 R2 ⎦

R2 a
≈ − (if a >> 1)
vout R2
=−
vin (1 + a )R1 + R2 R1

ƒ Overall (closed loop) gain does not depend on open loop gain
ƒ Trade gain for robustness
ƒ Easier analysis approach: “virtual short circuit approach”
ƒ v+ = v- = 0 if OpAmp is linear
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 Basic OpAmp Circuits

Voltage Follower (buffer) Non-inverting

+
vin +
vout −
-
R + R2
vout ≈ 1 vin
vout ≈ vin
R1

Differential Input
Integrator

t
( ) vout ≈ − 1
∫v
R2
vout ≈ v − vin1 in dt
R1 in 2 RC
−∞

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 Use With Open Loop

Analog Comparator:

Is V+ > V- ?
The Output is a DIGITAL signal

LM311 is a single supply

comparator

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 Data Conversion: Quantization Noise

A/D Conversion D/A Conversion

3Vref
11

Analog Output
4
Binary Output

10
Vref
2

01 Vref
4

00 0
0 Vref
4
Vref
2
3Vref
4
Vref 00 01 10 11
Analog Input Binary code

digital
code
vin A/D D/A
+ vnoise
Quantization
− noise
LSB
„ Quantization noise exists even with
ideal A/D and D/A converters Vref Vref 3Vref
v in
4 2 4
Vref

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 Non-idealities in Data Conversion
Offset – a constant voltage offset that appears Gain error – deviation of slope from ideal value
at the output when the digital input is 0 of 1
Analog

Offset

Analog
Gain
error error
Ideal Ideal

Binary code Binary code

Integral Nonlinearity – maximum deviation from Differential nonlinearity – the largest increment
the ideal analog output voltage in analog output for a 1-bit change

Integral
nonlinearity
Ideal
Analog

Ideal
Analog
Non-
monoticity
Binary code Binary code
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 R-2R Ladder DAC Architecture

-1

ƒ Note that the driving point impedance (resistance) is the same

for each cell.
„ R-2R Ladder achieves large current division ratios with only
two resistor values
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 DAC (AD 558) Specs

„ 8-bit DAC
„ Single Supply Operation: 5V to 15V
„ Integrates required references
(bandgap voltage reference)
„ Uses a R-2R resistor ladder
„ Settling time 1μs
„ Programmable output range from
0V to 2.56V or 0V to 10V
„ Simple Latch based interface

Image courtesy of Analog Devices. Used with permission.

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 Chip Architecture and Interface

D[7:0] LATCH

CE CS

Outputs are noisy

when input bits settles,
so it is best to have inputs
stable before latching
the input data

Image courtesy of Analog Devices. Used with permission.

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 Setting the Voltage Range

Very similar to a
non-inverting amp

Strap output for

different voltage
ranges

Image courtesy of Analog Devices. Used with permission.

Convert data to
Offset binary
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 Another Approach: Binary-Weighted DAC
R
„ Switch binary-weighted
currents
- vout
b3 b2 b1 b0 + „ MSB to LSB current ratio is 2N
I I I
I 2 4 8

vout = − IR(b3 + 12 b2 + 14 b1 + 18 b0 ) AD9768

„ Analog Devices AD9768

uses two banks of
ratioed currents
„ Additional current
division performed by
750 Ω resistor between
the two banks

Image courtesy of Analog Devices. Used with permission.

Reference current source

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 Glitching and Thermometer D/A

„ Glitching is caused when

switching times in a D/A are not
synchronized Binary Thermometer
„ Example: Output changes from 0 0 0 0 0
011 to 100 – MSB switch is 0 1 0 0 1
delayed 1 0 0 1 1
„ Filtering reduces glitch but 1 1 1 1 1
increases the D/A settling time
„ One solution is a thermometer R
code D/A – requires 2N – 1
switches but no ratioed
currents
vout
vout 011→ 100 T0 T1 T2
I I I

t vout = − IR(T0 + T1 + T2 )
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 Successive-Approximation A/D

ƒ D/A converters are typically compact and easier to design. Why not A/D convert
using a D/A converter and a comparator?
ƒ D to A generates analog voltage which is compared to the input voltage
ƒ If D to A voltage > input voltage then set that bit; otherwise, reset that bit
ƒ This type of A to D takes a fixed amount of time proportional to the bit length

Vin code

D/A

+ −
C

Comparator
out
Example: 3-bit A/D conversion, 2 LSB < Vin < 3 LSB
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 Successive-Approximation A/D

Data

Successive
D/A Approximation
N
Converter Generator

- Done
vin Sample/ Control
+
Hold Go

„ Serial conversion takes a time equal to N(tD/A + tcomp)

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 Successive-Approximation A/D
(AD670)
Unipolar (BPO =0)

„ ~10μs conversion time

Bipolar (BPO =1)

Image courtesy of Analog Devices. Used with permission.

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 Single Write, Single Read Operation
(see data sheet for other modes)

R/W tw
Write

CE, CS Read
tDC
Status tDT
tc tTD
Data Valid Data Valid

tw (write/start pulse width) = 300ns (min)

tDC (delay to start conversion) = 700ns (max)
tc (conversion time) = 10μs (max)
tTD (Bus Access Time) = 250 (max)
tDT (Output Float Delay) = 150 (max)
ƒ Control bits CE and CS can be wired to ground if A/D is the only chip driving the bus
ƒ Suggestion: tie CE and CS pins together and hardwire BPO and Format

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 Simple A/D Interface FSM

clk cs_b CS
CE
reset r_w_b
R/W AD670
FSM
sample status
STATUS

Data[7:0]

dataavail

Q D

Status should be
synchronized: why?

Courtesy of James Oey and

Cemal Akcaba Figure by MIT OpenCourseWare.

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 Example A/D Verilog Interface

module AD670 (clk, reset, sample, dataavail, // State declarations.

r_wbar, cs_bar, status, state); parameter IDLE = 0;
parameter CONV0 = 1;
// System Clk parameter CONV1 = 2;
input clk; parameter CONV2 = 3;
// Global Reset signal, assume it is synchronized parameter WAITSTATUSHIGH = 4;
parameter WAITSTATUSLOW = 5;
input reset; parameter READDELAY0 = 6;
parameter READDELAY1 = 7;
// User Interface parameter READCYCLE = 8;
input sample;
output dataavail; always @ (posedge clk or negedge reset)
begin
// A-D Interface if (!reset) state <=IDLE;
input status; else state <=nextstate;
reg status_d1, status_d2;
output r_wbar, cs_bar; status_d1 <= status;
output [3:0] state; status_d2 <= status_d1;

// internal state r_wbar <= r_wbar_int;

reg [3:0] state; cs_bar <=cs_bar_int;
reg [3:0] nextstate;
reg r_wbar_int, r_wbar; end
reg cs_bar_int, cs_bar;
reg dataavail; 1/5 2/5

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 Example A/D Verilog Interface (cont.)

always @ (state or status_d2 or sample) begin CONV2:

// defaults begin
r_wbar_int = 1; cs_bar_int = 1; dataavail = 0; r_wbar_int = 0;
cs_bar_int = 0;
case (state) nextstate = WAITSTATUSHIGH;
end
IDLE: begin WAITSTATUSHIGH:
if(sample) nextstate = CONV0; begin
else nextstate = IDLE; cs_bar_int = 0;
end if (status_d2) nextstate = WAITSTATUSLOW;

CONV0: else nextstate = WAITSTATUSHIGH;

begin end
r_wbar_int = 0;
cs_bar_int = 0; WAITSTATUSLOW:
nextstate = CONV1; begin
end cs_bar_int = 0;
if (!status_d2) nextstate = READDELAY0;
CONV1: else nextstate = WAITSTATUSLOW;
begin end
r_wbar_int = 0;
cs_bar_int = 0;
nextstate = CONV2;
end

3/5 4/5
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 Example A/D Verilog Interface(cont.)

READDELAY0:
begin
cs_bar_int = 0;
nextstate = READDELAY1;
end

READDELAY1:
begin
cs_bar_int = 0;
nextstate = READCYCLE;
end

READCYCLE:
begin
cs_bar_int = 0;
dataavail = 1;
nextstate = IDLE;
end

default: nextstate = IDLE;

endcase // case(state)
end // always @ (state or status_d2 or sample)
endmodule // adcInterface

5/5
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 Simulation
On reset, present state goes to 0 r_w_b must stay low for at least 3 cycles (@ 100ns period)

Enable read flip-flop

Status is synchronized – two register delays

Wait for ~10μs for status to go low

Sample pulse initiates Notice a one cycle delay since A/D

data conversion control signal delayed through a register

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 Flash A/D Converter

Vref vin „ Brute-force A/D conversion

+
„ Simultaneously compare the
R
C analog value with every
The rmom eter to binary
− possible reference value
R + b0 „ Fastest method of A/D
C
− b1 conversion
R + „ Size scales exponentially
C with precision
−
(requires 2N comparators)
Comparators
R

Can be implemented as OpAmp in open loop

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 AD 775 – Flash Data Converter

Image courtesy of Analog Devices. Used with permission.

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 High Performance Converters:
Use Pipelining and Parallelism!
Pipelining (used in video rate, RF basestations, etc.)
1-bit 1-bit
− −
Amplifier Amplifier
Sample/ A/D D/A
2
Sample/ A/D D/A
2 …
Hold Converter Converter Hold Converter Converter
+ +
Parallelism (use many slower A/D’s in parallel to build very
high speed A/D converters)
1 GHz
Clock
DLL [ISSCC 2003],
Poulton et. al.
80 Radix Converters
80 T/Hs and V/Is

80 Slice Decimator
80 ADC Slices

Clock
8 Mem Controllers

1MByte SRAM

CMOS
Gen
20Gsample/sec,
Buffer Chip
2 muxes
8-bit ADC
0.18- CMOS ADC Chip from Agilent Labs
Figure by MIT OpenCourseWare. Adapted from Poulten, Ken, et al. "A 20 GS/s 8b ADC with a 1MB Memory in 0.18um CMOS."
IEEE International Solid-State Circuits Conference Paper 18.1, 2003.

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 New Trend: Eliminate OpAmps!
(Use Comparators, more digital…)

„ Op amps must achieve high

open-loop gain and fast
settling time under
feedback.
„ High gain becomes
increasingly difficult
achieve due to low device
gain.
„ Solution: Comparator
based analog Design
„ Dramatic power savings
possible

Courtesy of Prof. Harry Lee, ISSCC 2006. Used with permission.

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 Summary of Analog Blocks

„ Analog blocks are integral components of any

system. Need data converters (analog to digital
and digital to analog), analog processing
(OpAmps circuits, switched capacitors filters,
etc.), power converters (e.g., DC-DC
conversion), etc.
„ We looked at example interfaces for A/D and
D/A converters
† Make sure you register critical signals (enables, R/W,
etc.)
„ Analog design incorporate digital principles
† Glitch free operation using coding
† Parallelism and Pipelining!
† More advanced concepts such as calibration

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