Unit- V

Chapter
9
Data Converters
Syllabus
Digital to analog data converter (DAC) : Circuit diagram and working of weighted resistor DAC and
R-2Rladder DAC, DAC specifications / selection factors. Analog to digital data converter (ADC) : Biock
diagram, Types and working of dual slope ADC, Successive approximation, Flash type ADC, ADC
selection factors / specifications.

Chapter Contents
o4- Need of Data Converters
9.7 Analog to DigitalConverters (ADC)
DAC Fundamentals 9.8 Types of A to D Converters
9.2

9.3 Binary Weighted Resistor DACc 9.9 The Parallel Comparator or Flash ADC

9.4 R-2R Ladder Network 9.10 ADC Specifications/Selection Factors

9.5 R-2R Ladder DAC 9.11 ADC Applications

9.6 DAC Specifications / Selection Factors
Digital Techniques Data Converter
9-2
Data converters
9.1
Need of Data
The
Converters :
signals
can be analog or digital by nature.
D to A convertors
IAto Dconverters

Sometimes we need to convert analog signals into the Flash

digital equivalent and vice Wblghted type ADC
versa. resistorDAC
The electronic circuits used for
such a conversion are R-2R ladder Counter
called as data converters. (A to D type DAC type ADC
and D to A
converters). Single and
dual
Due to the advantages offered by the
digital systems,
they are widely used in many
fields such as Successive
approximation
instrumentation, computers, communication and type ADC
control,
Classification of data converters
In many such (C-1177) Fig. 9.1.1 :
applications the signal are not available in DAC Fundamentals :
the digital form. 9.2
some A+.
Most of the physical are used as a part of
quantities such as Since D to Aconverters first
pressure, displacement, vibrations etc.
temperature, Dconverters, we are
going to discuss the DAC
are available in Transfer
analog form. 9.2.1 Circuit Symbol and
Characteristics :
These quantities are represented 3-bit DAC are shown i
form but it
accurately in analog The circuit symbol of a
is
difficult to process, store or transmit the
Fig. 9.2.1(a).
analog signal because error gets introduced easily,
due Reference DAC V,=Analog output
to noise.
voltage VA
Hence to reduce these errors it is always
better to
express these physical quantities in the digital form. Digital input
do d, d,
The digital representation of a signal (C-3161) Fig. 9.2.1(a) : Circuit
symbol of DAC
makes storage
possible, processing simpler and transmission easier. There are three digital inputs and one analog
output
"d," is the least
Therefore A to D conversion is necessary. Now once the "d," is the most significant bit MSB and
significant bit LSB.
processing, transmission etc. is done the signal should
be brought back to its analog form, for which the Dto The 3-bit digital word will have eight different possible
combinations from 000 to 111.
A conversion is essential.
V,
voltage, VES
Both ADC and DAC circuits are called as dataconverters
and they are available in the IC form. . o r . . . o - . .

output
9.1.1 Types of DataConverters: Analog
Output value for
The data converters are basically of two types: 1LSB input
1. Digitalto Analog Converters (DACS). + Digital input
2. Analog to Digital Converters (ADCS).
The classification of data converters is shown in
Fig. 9.1.1. (C-3162) Fig. 9.2.1(b) :Plot of an analog output voltage versus
digital input code for a 3-bit DAC
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93 Data Coverters
Input-Output Equation :
Hthe
Ex. 9.2.1: Calculate the analog Output of a 4-bit DAC
inputoutput equation of a DAC can be
used to digtal input is 1011 Assume Ves =5V
The the analog output voltage
calculate
given digital input
word. corresponding
to Soln.:
The 4-bt digital word is d, dd, d, d, m1011 with Vg 5
the

inputto a DAC block is an "n" bit

the
Ianalog
f
digital wordfor the
outputvoltage is V, then the expression and Volts and K 1, then the corresponding analog output
(923)
analogoutputvoltage V, is given by, voltage V, can be obtained by using Equation
as:
DVs (d,2 +d,2+.. + d,24
.(9.2.1) V, = S(1 x2h+0+1,2)+(1 2)
where, VES = Fullscale output voltage.
= n-bit binary = 5 [0.5 +0 + 0.125 +0.0625]
dy, dz...d, fractional word with -Ans.
V, = 34375 Volts
the decimal point at words
extreme left. Similarly. we can convert the digital input
d, = MSB (most significant bit) with of
1d, d, d, = 0000 and 1111 into analog voBtages
a weight of Vgs /2. Vo =0 Volts and 4.6875 Volts respectively.
d. = LSB (least significant bit) with the analog output
An altermative method to obtain
as follows. The output
a weight of Vgs /2. age ror a given digital input is mutiplying he
Wecan substitute VEs by KVRRie. the vOtage V can be obtained by
reference voltage resolution by the change in LSB.
towrite -(924)
V, =KVald,2 + d, 2+... +d,2] That means, V, = Resolution x D
..(9.2.2) where D = Decimal value of
the digital input
= Scaling factor W-23
where K
Ifwesubstitute. 9.2.3 Types of Dto A Converters : W-19.
D =[d,21 +d, 2 +... + d, 2 then MSBTE Questions Marks)
Qj List the types of DAC. (W-19, W-23, 2
V, = KVD network used, we
..9.2.3) Depending on the type of resistive circurts.
where Diss called as the fractional binary value. converter
have different types of D to A
The input output equation is applicable to all types of Some of them are :
DACS. 1 Binary weighted resistor DAC.
VEs: 2 R-2R ladder type DAC.
Fullscale voltage
The full scale analog output voltage Ves is defined as 9.3 Binary Weighted Resistor DAC :
the output voltage corresponding to the digital input Circuit diagram :
with all digits 1. weighted resistor type
Ihe circuit diagram of binary
DAC is as shown in Fig. 9.3.1.

RE

Binary welghted Analog

resistors
g2'R output
voltage Vo
Summing
Electronlc amplifier
switches

-Va (Reference votage)

öd, (LSB) Õ
d, (MSB)
n-bit digital input
(K-582) Fig. 9.3.1:Weighted resistor DAC
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 Data Converters
Digital Techniques 94
by,
voltage V, is given
This circuit uses a resistive network of binary The output
weighted
resistors followed by a summing amplifier. The resistors V, = ,Re
+d, 2]
2* R, 2 R. 2'R are from the
network of binary R;
Vapd, 2 + d,2 . (933)
weighted resistors. = voltage.
required expression for output
There are "n" number of electronic This is the (9.3.3), we e
switches used, one comparing Equations (9.3.2) and
per digital bit. They are Single Pole Double Now
Throw conclude that,
(SPDT) type switches.
R
The position of the moving arm of a switch is K = R and VEs = Va
controlled
by the binary input bit applied to it. K= 1.
So if R = R then
For example, if the binary bit d, = 1, then the first SPDT d, 2-2,+ .... + d, 2"] .(9.34)
V, = Va fd, 2+ Equation
switch will connect resistor 2*R to a negative
reference substituting the values of d dz -.d, in
By analon
voltage (- V) and when the binary input d, is "0" then value of corresponding
(9.3.3) we can obtain the
this switch will connect this resistor to
ground. output voltage Vo
Thus an n-bit digital word willdecide the positions of all Waveform of a
9.3.2 Output Voltage
the SPDT Switches and connect their 3-Bit DAC :
corresponding shown in Fig. 9.3.1
uses an
binary weighted resistors to either - Va or ground. The circuit of DAC
Therefore the use of a
Depending upon the positions of various switches, the "inverting" summing amplifier.
gives a positive analog
currents I to I, will start flowing through the resistors negative reference voltage (- Va) voltage V, we
the output
2'R to 2'R respectively as shown in Fig. 9.3.1. output voltage. Now to plot
Equation (9.3.3).
9.3.1 Expression for Analog Output Voltage : are going to use
K= (R /R) = 1 and n = 3.
In this equation substitute
Let the n-bit digital input Word to the DAC be d, d, ... at the DAC input is 3-bit
d, with d, as MSB (Most Significant Bit) and d, as LSB That means the digital word

(Least Significant Bit). long.

d, 2
: V, = Va [d, 2+ d, 2 +
.(9.3.5)
Let Re be the feedback resistor and I, be the output
any one combination of
current. Now let us calculate V, for
the equivalent circuit
Let the OP-AMP in Fig. 9.3.1 be an ideal OP-AMP so d, d, d. Let d, d, d, = 100, then
of DAC is as shown in Fig. 9.3.2.
that the current flowing into its input terminals is zero Point A is at
virtual ground
due to infinite input resistance. A
Assuming the OP-AMP of Fig. 9.3.1 to be ideal, the
output current I, can be expressed as the sum of ,=0=0
individual currents through the weighted resistors.
(Current going into the OPAMP terminal is zero.) Eloctronio
switches Digltal input = 100

VR VR VR
+ ...... ..(9.3.1)
--VR
Note that d,, d,...., can have a value of either "0" od,= 0 Ïd, =0 o d, =1
or "1".
t-Digital input 100
(K-583) Fig. 9.3.2 : Equivalent circuit of DAC for digital
V
R d, 2+ d,2+...+ d, 2"] ..(9.3.2) input d, d, d, = 100

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Switches corresponding 95
Thetwo to the
the resistors 2'R and
connect
2'Rto inputs d, and d, 9.3.3 Data Converters
ground
As
Ais at virtual
point
will be equal to zero groundas potential, the DiThe saccuracy
DAC: advantaandges stabity
of Woighted Resistor
,
andl,
Howeverthe switch
shown in currents
Fig 932 of ths tpe of DAC

the
resistor 2R to - V¡ andcorrespondidue ntog to d, wil
connect 2
depends on the accuracy of the resstors ued
This type of DAC a wide range of resistor
between A and - Va
Current l, will flow.potential difference requires
values. If the number of digts "n per bunary word
is 8then the
Substitutingthe values of d,, snallest resistor is 2 R R2 while
d, and d, into the largest one is 2 Rie 128 R2 Thus the largest
(9.35) we can obtain the
analog output voltage Equation
V, as: resistor is 128 times, the smallest one. This
V, = Va[1 x2* +0x2-2, proportion will be worse for still higher values of
n (say n = 12).
Similarly, we can obtain 3 For n = 12, if the smallest resistance is 25 k2, then
the
output voltage for all the
possible input digital words
from 000 to 111, as ne largest one wallbe 2 x 25 kn = 5.12 M2 The
in Table 9.3.1
shown fabrication of such alarge resistance in an IC
formn

(C-8316) Table 9.3.1 IS not practically possible The smallest resistance

Digital input Cannot be smaller than 2.5 ko2 This is necessary to
Analog avoid the loading effect.
d, d, da output
Voltage V, 4
1t Is very difficult to achieve and maintain accurate
0 1 Tauos over a wide range of resistor values. This
1 0
VB puts a restriction on the use of weighted resistor
2 V/8
DAC for the values of n less than 8-bits. Therefore
1 3 VJ8
1 the resolution of Such a DAC is poor.
4V8
5
Ine rinite resistance of the switches will disturb the
1 1 5 V/8
6 V8 Currents particularly in the Most Significant Bit
1 7 V8 (MSB) position because the current setting
resistors in the MSB pOsition are small in walue.
The graph of digital input code versus
plotted in Fig. 9.3.3. Thus the output voltage 9.3.4 of Weighted Resistor DAC:
V, is
staircase waveform.
DAC output is a
1
Advantages
Simple circuitry.
Analog output 2 Easy calculations.
Zva voltage
Ex. 9.3.1 :Describe how binary weighted network functions
as a DAC ? What is the full scale output for a 6-bit binary
weighted network with Vot = 10 V?
Soln.:
For a DAC,

8 Vo = Va [d, 2 +d, 2 +d, 2

+d, 2 +d, 2+ d, 2
To find Vs We have to substitute d, d, d, da ds d
Va Basic
= 111111
step size
000 001 010 011 100 101 110 111 Vs = 10 (1 x 2 + (1x2 +(1 x2}
Digital input code
(K-584) Fig. 9.3.3 : Staircase output for DAC
+(1x2+ (1x 2)+ 1x2]
= 10 x 0.9844 = 9.844 Volts -..Ans.

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9-6
Ex. 9.3.2 : Draw the
circuit diagram of 4-bit binary V, for 10001 :
or vanable
resistor type of DAC ADply weigntea 2. 2)+0+0+0+(1 x21
obtain the equation for Millman's theorem to V, = 10[(1 x
For this drcuit if '0' = output analog voltage
0Vand'1' = + 10 V V, = 5.3125
Volts Ans.
Find R-2R Ladder Network:
1
The full scale 9.4
output
2
The output voltage voltage This is the second type of resistive network used for the
change due to
3
The analog output voltage for a LSB D to A conversion.
Soln.: digital input 1011. ladder
the basic R-2R network It
Refer section 9.3 for 4-bit Fig. 94.1 shows
weighted resistor DAC. two values, Rand 2R
only
Given : V = 10 V, n = 4. consists of resistors of
1. Full scale output (Analog
voltage: voltaga)
V = Ve ld, 2+ d, 2'+ d, 2R
2+ d, 2 MSB
Vo = Vs if d, d, d, d, = LSB
1111
4 bit digital
:. Vs = 10 [(1 x25 + (1× 25+
(1x2)+ (1x21 Input
R-2R ladder network
Vs = 10 x 0.9375 = 9.375 Volts (K-585) Fig. 9.4.1: 4bit
-Ans.
construction and analysis
2
Output voltage change due to LSB: This will simplify the
componente
Let d, d, d, d, = 0001 network and also the selection of network
R-2R ladder type Dac
.:. V = 10 [0 + 0 + 0+ (1x 21 The R-2R network is the heart of
a 4 bit R-2R networ
10 and the one shown in Fig. 9.4.1 is
16 = 0.625 Volts bit, 5 bit orn bit R-D
..Ans. It is possible to have a 2 bit, 3
3 V, for digital input =1011: ladder.
with d, as the
Vo = 10 (1lx2h+0+ (1 x2)+ (x2) d, d, da d, is a 4 bit digital input word
= 10 [(1/ 2) + (1 /8) + (1/16)] = 10 Most Significant Bit (MSB) and d4 as the Least
(0.6875) Significant Bit (LSB).
V, = 6.875 Volts
..Ans. proportionalto
V, is the analog output voltage which is
Ex. 9.3.3 : Calculate the analog output for 5 bit
weighted the digital input.
res1stive type DACfor inputs :
1. 10110 9.5 R-2R Ladder DAC: S-19
2. 10001
Assume logic "0' =0 Vand logic '1' =10 V. MSBTE Questions
Soln. : Q.1 Draw the circuit diagram of 4 bit R - 2R ladder
For a 5 bit weighted resistor DAC, DAC and obtain its output voltage expression.
(S-19,6 Marks)
Vo = V(d, x2h +(d, x2h +(d, x z
Circuit diagram :
+(d, x2") +(d, x2 )1
1. V, for 10110: The problem of using a wide range of resistor values
(for weighted resistor DAC)can be solved by using the
Vo = 10 [( lx2')+0+ (1x2') +(1x2') +0] R-2R ladder type DAC.
= 10[0.5 + 0.125 + 0.0625] The circuit diagram for R-2R ladder type DAC is shown
Vo = 6.875 V ...Ans.
in Fig. 9.5.1.

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97
2R

2A 2RS Analog 2R
2R output
voltaga V,
Rasistoni
Resistors in Resistos R- 29
serion Re
seros A+Ro 2R
Eloctronic
MSB Reteronce 2
LSB voltage (-Va) circults to
d,0
-Digital input 100
od, =1 ses) Fig. 9.5.3: Simplified equivalernt
the left of B
is
K-586) Fig. 9.5.1: R-2R ladder DAC of Fig. 95.4(a)
The simplified equivalent circuit
Itshows that only two values of resistors are required redrawn as shown in Fig. 9.5.4(b).
2RO parallel with each
namelyRQ and
As the two resistors Rand 2R are in resistance
in a
This method is therefore suitable for the realization of other, their parallel combination resuits
integratedcircuits (aC). of (2 R/3) 2 Resistors in
-VA parallei
The value of Rin Fig. 9.5.1 can be anywhere between 2R IIR= 2R/3
2R R A -VR 2R ®)
2.5k2to10ko but it should not be less than 2.5 ko
2R
9.5.1
0peration of R-2R ladder DAC: S-19| QVitual
ground
MSBTE Questions k-2RI3

Draw the circuit equivalent circuit

Q. 1
diagram of 4 bit R- 2R ladder
(a) Simplified lequivalent circuit (b) Final
DAC and obtain its Output voltage expression. (K-589) Fig. 9.5.4

(S-19, 6 Marks) Voltage at node Bis given by,

Refer to Fig. 9.5.1 where the number of digits per binary (2R/3)
word is assumed to be 3 (i.e. n = 3). 2R + (2R/3)
2R
Resistors in parallel -(9.5.1)
2RIl2R=R 4 (2R/3) x-Ve
R ©R. R 6R + 2R

2R inverting amplifier
Considering the OP-AMP to be an
32R 2R 2R
in
the DAC is as shown
the equivalent circuit of
by.
Fig. 9.5.5. Hence the output voltage is given
K-587) Fig. 9.5.2 : Simplified R-2R ladder DAC (9.5.2)
- 2R
Vin = R
The switch positions indicate that the binary word is
2R
d, d, d, = 100.
R
The original circuit can now be simplified as shown in
oVo
Figs. 9.5.2 and 9.5.3 respectively.
The simplified circuit shown in Fig. 9.5.2 gets further
reduced to the simplified equivalent circuit shown in (K-590) Fig. 9.5.5
Fig. 9.5.3 Thus for a binary input of 100 the analog output
The equivalent resistance to the left of node "B" in produced is V/2.
Fig. 9.5.2 is only "2R" and node Ais at "irtual ground Similarly, it is possible to obtain the analog output
potential. voltages for other digital input words.
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9-8
Applications of DIA
Output voltage waveform 9.5.3

Table 951 Iists the digtal inouts and

S-23
corresponding MSBTE Questions DAC.
analog output votages and Fig 956 shows the ofADC and
Q. 1Write applicatons (S-23, 4 Marka)
staircase output voltage waveform obtained for R-Zk
ladder DAC Note that this is exactly identical to the one
digtal process1ng systemto convert digtal
drawn for the weighted resistor DAC 1 In any
command signal into analog one. (eg motor
(C-4316) Table 9.5.1 speed contro)
Digital input Analog converters such as counter ADC or
In the Ato D
d, d,
output 2 approximation type ADC
d, Voitage V, successive plotter
infomation on CRT or XY
1
0
3 For displaying
V8
1 2 VJ8 4 Incomputers.
equipments such as Curve tracere
1 1
3 V8 5 In the electronic
4 VJ8 Comparison of DACs: W-22
1 1 5 V8 9.5.4
1
1 6 VJ8
MSBTE Questions
1 1 7 VJ8 and weighted
Compare between R-2R ladder DAC
Q,1 (W-22, 4 Marks)
Va tAnalog
8
output
voltage
points).
resistor DAC (Four
shows the comparison of R-2R ladder DAe
Table 9.5.2
DAC.
and weighted resistor
Comparison of DACs
Table 9.5.2 :
Weighted R-2R Ladder
Sr. Parameter Resistor DAC DAC
No.
Slightly
1 Simplicity Simple
complicated
Wide ange is Resistors of
2. Range of only two values
Basic required.
resistor
step size are required.
000 001 010 011 100 101 110 111 values.
Two
Digital input code 3. Number of One
resistors per
(K-591) Fig. 9.5.6: Staircase analog output voltage bit.
for R-2R ladder DAC
Easy to
4. Ease of Not easy to
9.5.2 expand for expand.
Advantages of RI2R Ladder DACs : expansion.
more number of
1. Because we need resistors of only two values bits.
(R and 2R), it is easier to build this circuit assume
Ex. 9.5.1 : For a 6-bit binary R-2R ladder,
accurately.
0' = 0 Volt and '1"' = + 10 Volts. Find the output voltages for
2. We can increase the number of input bits just by
following digital inputs :
adding more sections of same R/2R values. 1. 101001
3 The equivalent resistance to the right of each 2. 11001
labelled node (A, B, C -)will be equal to 2R. Hence Soln. :
current flowing downwards, away from each node n =6, Type of DAC:R-2R ladder.
Given:
equal to the current flowing towards right.
Binary 0 = 0 volt, Binary 1 = 10V.
4
Due to the small resistance range required, the R
2R ladder can be fabricated monolithically, with a
To find : Analog output.
high accuracy and stability. From the given data V¡ = 10 V.
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that the analog output V,

write 9-9
We
can is givenby. Data Converters
21 d,2+ d,2+ d, 2 Ex.
= Vald,
if5V9.appears
5A:Whatat
+ d, 2 is the ful voltage of a 3 bit R-2R DAC
101001: scale
V,for Soln. : output when input is 101 ?Explan
1, ,= l and d, =1
d, = Fullscale voltage
10(1 x2)+(1 +2) +1251 Full scale output
Vo
- 6.40625 Volts corresponds to d, d, d, = 111
Vo os, =S[17'+1 42' + 1 2)
11001:
V,for = 5(0875] = 4375 Volts Ans.
10[(1 ×23
2
V, =
= 3.90625 Volts 2+0+0 +(1x21 Ex.
8 V
9.5.5: AD-A
and converter has a full scale analog output of
accepts 4 binary bits as inputs Find the voltage
9.5.2:Find percentage resolution and corresponding to each analog step
Soln. :
Ex.
following R-2R ladder: resolution in volts
forthe Given: Full scale analog
output =
A12bitDAC with full
ful scale V
1.
output + 10Volts Full scale output corresponds to d, d, d, d, =(1111),
A9bitDAC with full scale output + 5 Volts V, = Va [d, x2+ d, x2+d, x2+ d, x2](1)
2.
Soln.:

Resolution = 8V =
-1 0.9375 Va .:. V, = 8.533 V

where, VES = Full scale

output dnaiog step corresponds to increment in LSB by 1
and n = Number of bits. voltage. pur voltage corresponding to each analog step is
% Resolution = 0x 100 he voltage corresponding to d,d,d,d, =0001
Vo = V, [0 +0+ 0+ (1 x2 )
Here n = 12 and VE=+ 10 V 1
1. = 8.533 x = 0.533 Volts ..Ans.
.. Resolution =
10 Vo 16
= 0.00244 V
2-1 Ex. 9.5.6:Calculate analoa outout of 4bit DAC for
.% Resolution = 100 = 0.0244 digital input 1101. Assume VES =5 V.
W-18. W-22, 4 Marks
2.
Hence n = 9and Ves = +5V
Soln. :
: Resolution = 9=0.009785 V Given : 4 bit DAC, Input = 1101, Vs = 5V.
:. Resolution = x 100 =0.195 To find : V
Step 1 : Find VR :
. a6.3:A 4bit DIA converter produces an output voltage
Ves Corresponds to Vin = 1111.
af A5 V for an input code of 100%. What will be the value of
outout voltage for an input code of 0011 ? But Vo = Va [dË x 2 + dz 2 + d x 2+ d x2
Soln. : 5 = Va (1/2) + (1/4) + (1/8) + (1/16)]

Given : N=4, VEs = 4.5 Volts, Digital input = 0011 5 = 0.9375 VR

V =Vs [d, x2+ d, x 2 +da x2 +d, x 2 .:. VR = 5.33 Volts ...(1)
Step 2: Find Vo :
= 4.5 [0 + 0 +1x2+1x21
= 4.5 x 0.1875 = 0.84375 Volts Vo = 5.33 [(1/2) + (1/4) + 0 + (1/16)]
..Ans.
Vo = 4.33 Volts ..Ans.

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Data Converten
Ex. 9.5.7 : Calculate the number of b1ts in
Its value depends on the the digital
register type DAC for inputsanalog outout for 4 bit weigted the number of bits,,
1 1011 input applied to DAC Higher higher
is the resolution
2 1001
defined in two
Resolution of a DAC can be
Assuma Ves) full scale range of voitage is 5 V
ways : They are
dif erent
discUssed in the following explanation
is the number.
Soln. :
W.19.6 Marks The first definition of resolution
values that can
1,
different analog output voltage
1011 : Refer Ex 921 n-bit DAC,
provided by a DAC. For an
2. 1001 : Resolution = 2 (9.61)
Analog output voltage, 4-bit DAC is 2 = 16 and that
Hence the resolution of a
resolution increases wis
Vo = Vs [d,2+ d, 2 + ...+ dn 2"] of a 3-bit DAC is 2 = 8. Hence
number of bits.
the increase in
= 5[(1 x 2) +0 +0 + [(1 x 2) defined in an alternative way as the ratio
Resolution
= 5[0.S +0 +0 + 0.0625] voltage resulting from
of change in analog output
.. Vo = 2.8125 Volts input.
..Ans. change of 1 LSB at the digital
definition, we need
Ex. 9.5.8 : Calculate analog output of 4 bit DAC for digital To calculate the resolution with this
V;; and the
input is 1100. Assume VES = 5V.
S-22, 4 Marks to know the full scale analog output voltage
Soln. : number of digital inputs "n".
voltage Vss is defined ae
Given: N=4, Vs = 5V, Digital input = 1100 The full scale analog output
digital inpUt
To find: Analog output voltage the output voltage corresponding to the
given by,
with all digits 1. Therefore the resolution is
Vo = Vss [d, 2 + d 2+ d; + da 2 Vs
Resolution = 2'-1 ..(9.6.2)
= 5[(1 x 0.5) + (1 x 0.25) + 0+ 0]
= 5 (0.5 + 0.25]
where n = Number of digital inputs.
.:. Vo = 3.75 Volts 2. Accuracy:
...Ans.
9.6 DAC Specifications /Selection Accuracy of a DAC indicates how close the analoa
value. In short it
Factors: output voltage is to its theoretical
S-19 the
indicates the deviation of actual output from
MSBTE Questions theoretical value.
91 State twO specification of DAC. (S-19, 2 Marks)
Accuracy depends on the accuracy of the values of
D to A converters have the following important resistors used in the ladder, and the precision of the
characteristics (specifications): reference voltage used.
1 Resolution
Accuracy is always specified in terms of percentage of
2. Accuracy
the full scale output. That means maximum output
3 Linearity 4. Temperature sensitivity voltage. e.g. if the full scale output is 15 V and accuracy
5. Settling time 6. Speed is ± 0.1 percent then the maximum error is given by
0.001 x 15 = 0.015 V or 15 mV.
7. Long term drift 8. Supply rejection
3. Linearity :
Let us discuss them one by one.
1. Resolution :
The relationship between the digital input and analog
output is expected to be linear. However practically it is
Resolution is defined as the smallest possible change in not so due to the error in the values of resistors used
the analog output voltage. Resolution should be as high
for the resistive networks.
as possible.
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Techniques
9-11
Temperaturosensitlvity :
Data Converters
idealrequirement is
that the
The
converter should
analog output
not change voltage
Va (Rotererra)
to A due to
of
in
D
temperature hanges MSB

But practically the analog output is a function of

temperature
Anag
Input ADC dijia!
It is so because the resistance values and OP-AMP
LSB
parameterschange with changes in
settlingtime:
temperature EOC
(San of (End of
Theoreticallythe analog output voltage should Gonvercn) cnvergion)
(K409) Fig. 9.71:Basic block diagram
change change
instantaneously as soon as there is a
digitalinput.
in the The function of ADC is exactly apposte to that of a
DAC The input to an ADC is the analog vtage V, and
Practically the analog output of a Dto A
change instantaneously. Due to the converter does at the
output we get an "n" brt digrtal word
not
OP-AMP in the circuit, oscillations are
resistors and In the n-bit digtal output d represents the Most

output.
obsserved at the Signrficant Brt (MSB) and d. is the Least Signficarnt Bt
a) The analog input voitage V, produces an output
The time required to settle the analog output within 1/2
LSB of the final value, from the
digital word, having a functionalvalue "D given by.
instant
called as settling time.
of change in D = d, 2+ d, 2 2 .+ d, 2 (971)
digital input is
+
The
should be.as short as possible. settling time In addition to the analog input voltage Va the ADC
Speed: block has areference voltage Va input and two control
6
It is defined as the time taken by a DAC to perform a lines SOC and EOC.
The Start of Conversion (SO input is used to start the
conversion from digital to analog. It is
also defined as Ato D conversion whereas the End of Conversion (EOC)
the number of conversions that can
be performed per Output goes high to indicate that the conversion is
second. The speed of DAC should be as
high as complete.
possible. The relation between the analog input voitage V and
Long term drift:
7. the digital output Dis given by.
This results mainly due to resistor and semiconductor V
-(9.72)
D =d, 2+ d,2+...d, 2" =YV.V
aging and can affect all the characteristics.
Characteristics mainly affected are linearity, speed etc. Where K = Constant.
8. Supply rejection: Va = Reference voltage.
Ves = Full scale input voltage.
It indicates the ability of DAC to maintain all its
V, = Analog input voltage.
important characteristics unchanged when the supply
voltage is varied.
Conversion time:
Refer Fig. 9.7.2. At t =to a SOC signal is given to the
Supply rejection is usually specified as percentage of
ADC and at t = t we get EOC output.
full scale change at or near full scale at 25° C. Conversion
time
9.7 Analog to Digital Converters (ADC):
-Time
Block diagram : -

The simple block diagram of an ADC is shown SOC EOC

in Fig. 9.7.1. (K-609(a) Fig. 9.7.2 : Graphical representation of
conversion time

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9-12
The time Vn (Rolorono voltago)
difference
as "conversion time.between these two instants is called
The conversion time should be as small as Comparators

Practically it can have

values from a few possible.
to a feW msec. hundreds of us
9.8
Types of A
to D oY (MSB)
There are various
circuits
Converters : Analog
inputo
Priority
oncoder 2-bit output
available for the A to D VA o Yo (LSB)
ConverSions. VA
They use different principles V
of operation
Conversion. for
Some of them are :
1 4
Flash type or
2 simultaneous ADC
Tracking servo type.
or (K-611) Fig. 9.9.2 : 2-bit flash
type ADC
3
Single slope Ato D The inverting (-) input terminal of each
comparator ie
4
converter.
Counter type ADC. connected to a different reference voltage. V, V, and v.
5.
Successive approximation Ato D converter. are the reference voltages for the three comparators
6 Dual slope Ato D
converter Integrator type). respectively as shown in Fig. 9.9.2.
from the
9.9 The Parallel These reference voltages have been derived
Flash ADC : Comparator
or voltage source V2 by using a resistive divider. The
reference voltages are : V = Va/4, V = Va/2
The parallel comparator ADC V,=3 V4.
uses a number of OP-AMP
comparators. The comparator outputs C, C, and C are connected to
Therefore let us first revise the an encoding network which will produce
2-bits
principle of a
comparator. The principle of a comparator has been equivalent to the analog input voltage. The encoder
summarized in Fig. 9.9.1. used is "priority encoder".
Analog input Comparator Condition of Output
Inputs The comparator outputs for various windows, and the
voltages
V,=1 priority encoder output are given in Table 9.9.1.
V, =0 (C-9408) Table 9.9.1 :Summary of operation
(Reference) VA= VA Previous of 2-bit flash type ADC
value Priority
Comparator encoder
(K-610) Fig. 9.9.1: Principle of operation of a Analog Input
comparator Range
number voltage V Volts
outputs
output
9.9.1 Two Bit Flash Type ADC :
A C,C YY,
Circuit diagram: 1 0<Va<Vl4
The circuit diagram for a two bit parallel
comparator
2 VJ4 <V,<V2 0 1 0 1

ADC is as shown in Fig. 9.9.2. 3 V/2< Va<3V4| o 1 1 1

The non-inverting (+) input terminal of each 4 3VJ4 <V<VR1 1 1 1

comparator has been connected to the analog input Operation of two bit flash type ADC :
voltage VA
Consider the first range of input voltage ie.
As seen in the circuit diagram three comparators are
0< Va < V/4. In this range the reference voltages
being used.
V, V, and Vare all higher than the input voltage.

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Therefore the output voltages of
all the Data Corverers
low ie. C C, C, = 000 and
the comparators Operation
are
output of the priority encoder is 00 as coresponding
shown in
The
operation of ths
Table9 91 Tatie 99 2
second range
Inthe
of input voltage ie
VJA V, < AY Table 992Summary oof operation of a bit ADC
VJ2,thereference voltage V, VJ4 is less than v,
Therefore the output of comparator 1
Anaiogogtal
input output
only is hgh Voltaga V,4,,
(C1). 0-05
other two comparators produce 05-15
The a "0
voltage(C, = CG= 0). output 15-25
25-35 1
of
The output the priority encoder is 01 as 35-45
Table 9.9.1. shown in 45-55 1

55-65
Similarlythe operation can be
two voltage ranges.
explained for the other >65 1 1

Ihe resistance ladder shown in Fig 993 s used to

Thus we obtain a two bit digital output from the analog
input voltage V.
generate different reference voltages ranging from
0.5 V to 65 V.
3-Bit Flash Type ADC :
9.9.2 Inese reference votages are applied to the inverting
Circuitdiagram : terminals of Comparators. The analog input V is
all the
The 2-bit ADC circuit is not used applied to the non-inverting terminals of
practically. Practically
3. 4 or even more number of output bits are required. comparators.
a priority
The circuit diagram of a 3-bit flash type ADC is as Tne comparator outputs are applied to
shown
shown in Fig. 9.9.3.
encoder which produces a 3-bit digital output as
Vref 8V = VES
in Table 9.92.
Bank of comparators
6.5V Advantages of Flash Type ADC:
speed of
1. This circuit has the advantage of high
takes place
conversion as the A to D conversion
55V

simultaneously and not sequentially.

of ADC is
4.5V
5
2. Typically the conversion time of this type
100 nS or less. Thus this is the fastest ADC.
3.5V Priority
do 3 bit
4
encoder d, digital Disadvantages of Flash ADC :
output ADC is
1 The biggest disadvantage of this type of
25V
that a large number of comparators are required to
be used. For a 2-bit ADC, three comparators are
1.5V
used. For a 3-bit ADC we need seven comparators
and for a4-bit ADC the number of comparators
LSB =05v
required to be used is fifteen. Thus with increase in
R
2 the number of bits by 1, the number of
-o Analog input Va= 0to 7 Vots
comparators willapproximately double.
(K-612) Fig. 9.9.3: 3-bit flash type ADC

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PuDIiCat o n s
 14
Wih inreed eurter tite " the prity Gpetion i
enodes becones itressirgy eomple
1
.0.3 Suooesalve Approximatlon ADO
(BA - ADC):
MBUTE Questios
he A
a.1 Dscribe the working of irtte the "K inp,
uoesahve 2 As soon 5 we
ADC, Define resohuion and
approdmaton M8 d, 1with al other tns to ze
The
set the
converon tme 0D
ont is l0
associated with ADC,
W48, 6Mara) the trial codeat the SAR
then appied
a.2 Drew the drout of &-bn ADC This rial ode is
succsive upprodmation type comeponding unpt AC
ADC and eplain Ire working. input of a DAC The
(49,4 Maro) the comparator, # U, <V) ie
.3 Describe the working
principle of ie Vo is aplied to
ucooselve # trial Code s less
than the cornect d
approximation ADC.
(W-19,4Marks) representtion then comparstor outpt
ges hig
Prlnciple of operatlon :
which is applied to SAR
Successive approximation ADC is one of the most comparator output the Mse d
3. In response to high
widely and popularly used ADC technique. lower hgnificart
is maintained at 1" and the ned
The ADC operation is based upon an the SAR outpu
efficient "code bit d, is made "1" The tríal code at
search strategy to complete the n-bit comversion in just now becomes 1100 0000. The
corresponding DAC
n-clock periods. the proces
Output is compared with VA and
Thus it takes much shorter continues as explained in 2.
coversion time as
compared to the counter type ADC. onty
4 However for the first trial code of 1000 0000
Block diagram : VA< Vo then the comparator output will go low
The block diagram /circuit diagram of the successive ie. 0. The SAR will respond to it by reseting its
MSB bit d, to 0 and making the next bit d, = 1 o
approximation ADC is as shown in Fig. 9.9.4.
that the new trial code is 0100 0000.
Analog Cormparator 80c (8tart of Corverelon)
Input VA
EOC(End of Converslon)
5. This procedure is repeated for all the subsequent
bits one at a time, until all bit positions are tested.
SAR -Clook L
6. As soon as the DAC output Vo crosses V, ( ie.
d dg
M8B
-4lnoin digital V > V), the comparator changes state and this is
-d,| utput
LSB taken as End of Conversion (EOC command.
DAC Output Vp
DAC Table 9.9.3 explains the operation of successive

(K-615) Fig. 9.9.4:Successive approximation ADC

approximation type ADC in a simple way.

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(K-616) Table 915
1 9.9Intialy
.3:Sequence of
SAR operation the successive
in Data Converters

Ouput approximatlon ADC technique

Bitd, dmade
,dCampar0o00stor euu 1 1
S. V50
D000
ls
2 New SAR output d,
,
Campare V, wi-th1000
V0000
VoVa
.Make bit d,Compar
1 ator oufgut 1
3
New SAR output:d,
Compare Vod,with VA1100 0000
Vo<Vbit . Comparator
Make d, =1. output=1.
4
New SAR oUtput:d,
d, =
Compare V, with Va1110 0000
Vo>Va i.
So make d,= Comparat
0 or output =0
and d,= 1
5
New SAR output:d,
d, =1101 0000
Compare Vo with Va
Vo<Va .
So maka d, =1Comparator output =0.

6
New SAR
output:d, ....d,
Continue the same process 1101 1000
as follows
SAR output
Comparator output
1 10 1
100 0,
Vo>V
1 10 1 Make d, =0 and d =1
0100
Vo>VA

Make de =0 and d, =1
1101 001 0
Stop as V, V

Suppose that for the given analog input voltage the Advantages :
correct digital output is 1101 0010. Then the SAC ADC 1. The conversion time is equal to the "n" clock ycle
reaches this word in the way shown in Table 9.9.3. period for an n-bit ADC. Thus conversion time is
Table 9.9.3 showS that for Va Vo the comparator very short.
2 For example, for a 10-bit ADC with a clock
output becomes high and for VA < V, the comparator
output is low. frequency of - 1 MHz, the conversion time will be
10 × 10ie. 10 sec only.

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 Data Converten
Digital Techniques 9-16
3
Conversion time is constant and independent of Circult description
the amplitude of analog signal VA SOC signal to start the
A
logic accepts the
The control
Disadvantages:
1 The to D conversion and generates tOC Signal
when the
circuit is complex
2 ConversIon is over.
Ihe conversion time is longer as compared to flash which
type ADC controls the two switches S and S, out of
Italso
whose one terminal
Applications : a single pole three way switch
S, is
second one ie
Due to the advantages mentioned earlier the analog voltage Va
successive iS connected to connected to
the third one is
approximation ADC is most widely used in the Connected to ground and
arm of
microprocessor based data acquisition systems negative reference voltage - VREF- The moving
a terminal of
1C ADC 0809 uses the concept of the inverting (J input
successive S, is connected to
approximation.
integrator Aj
9.9.4 Dual Slope Integrator ADC : integrator and A, is a
S-22 OP-AMP A, is a simple
the
the counter we get
MSBTE Questions Comparator. At the output of
Q. 1 Draw block diagram of dual slope ADC and explain n-bit digital output.
its working.
(S-22, 6Marks)
This is a very widely used ADC. It requires more Operation:
output voltage
conversion time but it is extremely accurate. Initially assume that the integrator
RESET condition ie. counter
Principle of operation : V, =0and the counter is in
In this ADC, an unknown analog voltage and a known Output is 00.
S, is connected to
reference voltage, are converted into equivalent time Refer to Fig. 9.9.6. At t = to, Switch
periods using an integrator. ground and switch S, is closed.
These time periods are then measured by a counter. connected across the
The capacitor CA gets
This circuit is called as a dual slope ADC because the
Comparator output.
analog voltage A and the reference voltage are
Integrator JAutozero
converted to ramp signals of different slopes by the output
integrator. voltage ’time

Block diagram :
The block diagram of dual slope ADC is shown in
Slope Slope =VaEF/RC
-Va/ RC
Fig. 9.9.5.
Analog Integrate VA Integrate VAEF
inputo Switch
VA S. R
(K-618) Fig. 9.9.6: Waveforms of adual slope ADC
Comparator
Aq
GND Ag Any offset voltage present in the OP-AMPs will appear
-VREF ntegrator
across the capacitor CAz:
This will provide an automatic compensation for the
input offset voltage of all the amplifiers.
n - stage
SOC Control logic Counter
Therefore integrator output voltage is zero for the
Digital
EOC output interval to to t, in Fig. 9.9.6.
(K-617) Fig. 9.9.5 : A dual slope ADC
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it ,the
instant
SOC command is given to the control
nurmber
At t, the counter output
At shows
logic
connected|to Va and S, is opern circuited (oresponding to Nclock cycles t has counted during
SwitchS,is period t, to t,
memory to hold the
Ca
then acts as a voltage
required Thus this number N represents the time taken for
the offset zero. Hence Ch is known as
to
keep the integrator output to reduce from -V to 0
autozerocapacitor,
ADC will Hence N represents the desired digital output code
From t, to
t this integrate the analog input proportional to the analog input VA
a
fixed duration off2" number of clock cycles.
V,for IfV increases, then the integrator capacitor wil charge
Thistimeinterval is required for the counter to advance
to a higher negative voltage during the time interval T;
through all its possible output states, because for an
ineretore the time , required to reduce the integrator
n-bit counter there will be 2 possible output states.
output to zero increases.
The
counter output then reduces to zero. Iherefore the counter output count (N) will be higher.
The time duration t, to t, is represented by " T, in
Thus Nis proportional to Va
Fig.9.9.6. Advantages of dual slope ADC :
Theintegrator output during this period is given by. N Ve
it is
tz
1
Ihe expression for V, is V,= 4 . hence
Vo =-Jv,
RC dt =-VAT,
RC (9.9.1) independent of R.Cand T. Thus drifts in any of the
tË
Components affects T, and T, in the same
This expression represents a straight line with aslope of proportion and ADC output is unaffected.
- V/RC.
2 If T, is chosen so that it is related to power supply
Thus we get a decreasing ramp as shown in Fig. 9.9.6.
period, the noise and hum on the input line get
The time period T; is thus represented by 2 clock largely averaged out Hence, dual slope ADC is
cycles. capable of rejecting noise and hum.
. T. = 2"× T... where T= One clock ycle period
3. Offset correction can be introduced by a relatively
At the end of interval T, the integrator input is simple circuit, facilitating auto-zeroing.
connected to a fixed negative reference voltage 4. Low cost.
- VaF Via switch S,.
5. Accuracy of the dual-slope ADC can be of the
The integrator output now starts increasing towards order of 0.05 %, which is adequate for most
zero with a positive slope as shown in Fig. 9.9.6. The applications.
slope is VREF/RC for the duration t, to ta. Disadvantage of dual slope ADC:
The counter starts counting from 0. The integration will
The only major drawback of a dual slope type ADC is its
continue till the integrator output is non-zero. long conversion time as compared to other ADCs.
At instant ta the integrator output reduces to zero, the 9.9.5 Comparison of AD Converters :
comparator output goes from HIGH to LOW and the
The comparison of different types of A to D coverters
clock pulses given to the counter are stopped.
is given in Table 9.9,4.

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Table 9.9.4IComparion of A/Donverters Dual slope

Sr
Parameter Successive approximation
No Flash type
Longest
Converson ime Shortest Moderately long Slowest
2 Speed Fastest Faster than dual slope
Very accurate
3 Accuracy of Less accurate Moderately accurate
conversion Longest Therefore a
Higher than that of flash type sample and hold circuit ie
4 Input hold time Almost zero
on the number
ADC Itdepends necessary.
of bits
Low
5 Cost Very costly as a large number of Moderately high
comparators are being used. Cost
6 good High accuracy, loW
|Advantages High speed and no input hold time. Constant conversion time.
medium
speed, high accuracy,
cost. slow,
7 Long conversion time,
Disadvantages Low accuracy, high cost. Not many. speed, long input hold
time.

8 Allthose applications
Applications All high speed applications such as |All data acquisition systems.
storage CRO, fiber optic which need very high
communication etc. accuracy.

9.10 ADC Specifications/Selection 9.10.2 Conversion Time:

W-18
Factors:
Some of the important characteristics of ADC are: MSBTE Questions
approximation
1 Resolution. Q. 1 Describe the working of suCcessive
and conversion time
2. Conversion time. ADC. Define resolution
3 Quantization error. associated with ADC.
(W-18, 6 Marks)

9.10.1 Resolution: w.i8 Definition:

It is the total time required to
convert the analog input
MSBTE Questions
Q. 1 Describe the working of successive approximation signal into a corresponding digital output.
As we know, the conversion time
depends on the
ADC. Define resolution and conversion time
associated with ADC. (W-18, 6 Marks) Conversion technigque used for an ADC.
Definition: The conversion time is also dependent on the
Resolution is defined as the maximum number of digital propagation delays introduced by the circuit
output codes. This is same as that of a DAC. components.

Resolution = 2" ...(9.10.1) Conversion time should ideally be zero and practically
be as smallas possible.
Alternatively, resolution can be defined as the ratio of
the change in the value of the input analog voltage Va 9.10.3 Quantization Error :

required to change the digita! output by1 LSB. As shown in Fig. 9.10.1, the digital output not always
Ves the accurate representation of the analog input.
.. Resolution = .(9.10.2)
2-1
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Actual output Data Corverters
Dgta
o lu u t

In computerised
Quantzod 6 NC and CNC
instrurmentation sptems
1. Output mxnnes
Review Questions
Q1
Eplan the necesstyof ung the data corverers
Q2
100
Eplain the basic principle of a Dto Acverer
L 12 LSB Q3
(Maximum quantzation erro eine and expiain the term "Resolution n
connecion with Dto Aconverters
o10

Define and explain the input-output equaton of D to

001
A converter
1/8- -28-38-+48-+t5/8-+6/8-7/8- Anaicg
input Q.5 DAC
Name various techniques used for
(K-623) Fig. 9.10.1:
:A graph of input and output
voltages for an ADC
impiementaton.
Q.6 Win the heip of a neat circut diagram, expla1n the
For example, any input voltage between 1/8 to 2/8 of
operation of binary weighted resistor DAC
full scale will be converted to a digital word of "001".
Q.7 What do vou understand by the term binary
This approximation process is called as quantization
and the error due the quantization process is called weighted resistors ?
as quantization error. Q. 8 Derive the expression for the analog output voitage
plot the
The maximum value of quantization error is ± 1/2 LSB. OT a binary weighted resistor DAC and
output voltage for a 4-bit digtal input word
The quantization error should be as small as possible. It
can be reduced by increasing the number of bits
Q.9 What are the disadvantages of binary weighted
resistor DAC ?
rho increase in number of bits will also improve the
resolution. Q. 10 With the help of neat circuit diagram, explain re
operation of an R-2R ladder DAC.
9.11 ADC Applications : S-23
perfonance to
Q. 11 R-2R ladder DAC is superior in
MSBTE Questions weighted resistance DAC- Justify.
o.1 Write applications of ADC and DAC. R-2R ladder
Q. 12 State and explain the advantages of
(S-23, 4 Marks)
DAC.
Some of the important generalapplications of ADC are
as follows: Q. 13 Explain in brief different types of DIA techniques.

In the digital instruments such as digital voltmeter., Q. 14 Compare various DAC techniques.
1
frequency counter etc. Q. 15 State various important specifications of DAC and

2 Inthe data acquisition system. explain any four of them.

3 In the digital tachometers for speed measurement Q. 16 Explain in brief different types of ADOC techniques.
and feedback. Q. 17 State and explain the important specifications of
4. In digital recording and reproduction. ADC.

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920
of conversion time and
Q 18 Explain the operabon of dual slope ADC and state Q21 Give the significance
to ADC
its advantages accuracy with respect
Q19 List various methods of Dconversionn and explain Q22 Give an application of DA Converters

the one which is the fastest appications of WD converter

Q 23 Give the
a 20 With the heip of a neat biock dsadvantages ofIsingle sioA
diagram, explain the O 24 State advantages and
operation of a sucoessive approximation type ADG WD converters
and dual siope
and state its advantages over the other
types of
ADC

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