SYED HASAN SAEED
hasansaeedcontrol@gmail.com
https://shasansaeed.yolasite.com
Syed Hasan Saeed, Integral University,
1
Lucknow
DECODER
&
ENCODER
Syed Hasan Saeed, Integral University,
2
Lucknow
DECODER
• A decoder is a combinational circuit.
• A decoder accepts a set of inputs that represents a binary
number and activates only that output corresponding to the
input number. All other outputs remain inactive.
• Fig. 1 shows the block diagram of decoder with ‘N’ inputs and
‘M’ outputs.
• There are 2N possible input combinations, for each of these
input combination only one output will be HIGH (active) all
other outputs are LOW
• Some decoder have one or more ENABLE (E) inputs that are
used to control the operation of decoder.
Syed Hasan Saeed, Integral University,
3
Lucknow
BLOCK DIAGRAM OF DECODER
A0 B0
A1 B1
A2 B2
. DECODER .
. .
. .
. .
AN-1 BM-1
N- Inputs M- Outputs
Only one output is High for
each input
Fig. 1
Syed Hasan Saeed, Integral University,
4
Lucknow
2 to 4 Line Decoder:
Block diagram of 2 to 4 decoder is shown in fig. 2
A and B are the inputs. ( No. of inputs =2)
No. of possible input combinations: 22=4
No. of Outputs : 22=4, they are indicated by D0, D1, D2 and D3
From the Truth Table it is clear that each output is “1” for only
specific combination of inputs.
TRUTH TABLE
A D0
INPUTS OUTPUTS
2X4 D1
Decoder A B D0 D1 D2 D3
B D2
0 0 1 0 0 0
D3
0 1 0 1 0 0
Inputs Outputs
1 0 0 0 1 0
Fig. 2
1 1 0 0 0 1
Syed Hasan Saeed, Integral University,
5
Lucknow
BOOLEAN EXPRESSION:
From Truth Table
D0 A B D1 A B
D2 A B D3 AB
LOGIC DIAGRAM:
A B
A B
D0 A B
D1 A B
D2 A B
D3 A B
Fig. 3
Syed Hasan Saeed, Integral University,
6
Lucknow
3 to 8 Line Decoder:
Block diagram of 3 to 8 decoder is shown in fig. 4
A , B and C are the inputs. ( No. of inputs =3)
No. of possible input combinations: 23=8
No. of Outputs : 23=8, they are indicated by D0 to D7
From the Truth Table it is clear that each output is “1” for only
specific combination of inputs.
A D0
.
B 3X8 .
Decoder .
C .
D7
Inputs Outputs
Fig. 4
Syed Hasan Saeed, Integral University,
7
Lucknow
TRUTH TABLE FOR 3 X 8 DECODER:
INPUTS OUTPUTS
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0 D0 A B C
0 0 1 0 1 0 0 0 0 0 0 D1 A B C
0 1 0 0 0 1 0 0 0 0 0 D2 A B C
0 1 1 0 0 0 1 0 0 0 0 D3 A B C
1 0 0 0 0 0 0 1 0 0 0 D4 A B C
1 0 1 0 0 0 0 0 1 0 0 D5 A B C
1 1 0 0 0 0 0 0 0 1 0 D6 A B C
1 1 1 0 0 0 0 0 0 0 1 D7 A B C
Syed Hasan Saeed, Integral University,
8
Lucknow
LOGIC DIAGRAM OF 3 X 8 DECODER:
INPUTS
A B C
A B C
D0 A B C
D1 A B C
D2 A B C
D3 A B C
OUTPUTS
D4 A B C
D5 A B C
Fig. 5
D6 A B C
D7 A B C
Syed Hasan Saeed, Integral University,
9
Lucknow
EXPANSION OF DECODERS:
The number of lower order Decoder for implementing higher order
Decoder can be find as
No. of lower order required = m2/m1
Where, m1=No. of Outputs of lower order Decoder
m2=No. of Outputs of higher order Decoder
Syed Hasan Saeed, Integral University,
10
Lucknow
3 x 8 Decoder From 2 x 4 Decoder:
X D0
INPUT
D1
Y 2 x 4 Decoder
D2
OUTPUT
E D3
D4
D5
2 x 4 Decoder
D6
D7
Fig. 6
Syed Hasan Saeed, Integral University,
11
Lucknow
Example: Implement the following multiple output function using a suitable
Decoder.
f1(A, B, C) = ∑m(0,4,7)+ d(2,3)
f2 (A, B, C) =∑m (1,5,6)
f3 (A, B, C) =∑m (0,2,4,6)
Solution: f1 consists of don’t care conditions. So we consider them to be logic 1.
0
1
f1(A, B, C)
A 2
3 x 8 Decoder
3
INPUTS
B f2 (A, B, C)
4
C
5 f3 (A, B, C)
7 Fig. 7
Syed Hasan Saeed, Integral University,
12
Lucknow
EXAMPLE: Implement the following Boolean function using suitable Decoder.
f1 (x,y,z)=∑m(1,5,7)
f2 (x,y,z)=∑m(0,3)
f3 (x,y,z)=∑m(2,4,5)
Solution: 0
1 f1 (x,y,z)
X 2
3 X 8 Decoder
Y 3 f2 (x,y,z)
INPUTS
Z 4
5
E f3 (x,y,z)
6
7
Fig. 8
Syed Hasan Saeed, Integral University,
13
Lucknow
EXAMPLE: A combinational circuit is defined by the following
Boolean function. Design circuit with a Decoder and external gate.
F1 (x, y,z) x y z x z (UPTU, 2004-05)
F2 ( x, y,z) x y z x z
SOLUTION: STEP 1: Write the given function F1 in SOP form
F1 ( x, y,z) x y z ( y y ) x z
F1 ( x, y,z) x y z x y z x y z
F1 ( x, y,z) m (0,5,7)
F2 ( x, y,z) x y z x z
F2 ( x, y,z) x y z ( y y ) x z
F2 ( x, y,z) x y z x y z x y z
F2 ( x, y,z) m (1,3,6)
Syed Hasan Saeed, Integral University,
14
Lucknow
Boolean Function using Decoder:
X 2 F1
3x8
Decoder 3
Y
4 F2
5
Z
6
7
Fig. 9
Syed Hasan Saeed, Integral University,
15
Lucknow
ENCODER
• An Encoder is a combinational logic circuit.
• It performs the inverse operation of Decoder.
• The opposite process of decoding is known as Encoding.
• An Encoder converts an active input signal into a coded output signal.
• Block diagram of Encoder is shown in Fig.10. It has ‘M’ inputs and ‘N’ outputs.
• An Encoder has ‘M’ input lines, only one of which is activated at a given time,
and produces an N-bit output code, depending on which input is activated.
A0 B0
‘M’ Inputs
‘N’ Outputs
A1 B1
A2 B2
-------
-------
Encoder
AM-1 BN-1
Fig. 10
Syed Hasan Saeed, Integral University,
16
Lucknow
• Encoders are used to translate the rotary or linear motion into a digital
signal.
• The difference between Decoder and Encoder is that Decoder has Binary
Code as an input while Encoder has Binary Code as an output.
• Encoder is an Electronics device that converts the analog signal to digital
signal such as BCD Code.
• Types of Encoders
i. Priority Encoder
ii. Decimal to BCD Encoder
iii. Octal to Binary Encoder
iv. Hexadecimal to Binary Encoder
Syed Hasan Saeed, Integral University,
17
Lucknow
ENCODER
M=4
M=22
M=2N
‘M’ is the input and
‘N’ is the output
A0
B0
A1
B1
A2 Encoder Decoder
A3 B2
4x2 2x4
B3
Fig. 11
Syed Hasan Saeed, Integral University,
18
Lucknow
ENCODER
M=4
M=22
M=2N
‘M’ is the input and
‘N’ is the output
A0 00
01
A1
10 Encoder Decoder
A2
A3
11 4x2 2x4
Fig. 12
Syed Hasan Saeed, Integral University,
19
Lucknow
ENCODER
M=4
M=22
M=2N
‘M’ is the input and
‘N’ is the output
A0 00
01 1
A1
10 Encoder Decoder
A2 0
A3
11 4x2 2x4
Fig. 13
Syed Hasan Saeed, Integral University,
20
Lucknow
ENCODER
M=4
M=22
M=2N
‘M’ is the input and
‘N’ is the output
A0 00
01 1
A1
10 Encoder Decoder
A2 0 10
A3
11 4x2 2x4
Fig. 14
Syed Hasan Saeed, Integral University,
21
Lucknow
PRIORITY ENCODER:
• As the name indicates, the priority is given to inputs line.
• If two or more input lines are high at the same time i.e 1 at the same time,
then the input line with high priority shall be considered.
• Block diagram and Truth table of Priority Encoder are shown in fig.15
Highest Priority
Input TRUTH TABLE:
D3
Y1 INPUTS OUTPUTS V
D2 D3 D2 D1 D0 Y1 Y0
Priority 0 0 0 0 x x 0
D1 Encoder
0 0 0 1 0 0 1
Y0
D0 0 0 1 x 0 1 1
0 1 x x 1 0 1
Lowest Priority Output 1 x x x 1 1 1
Input
Block Diagram of Priority Fig.15
Encoder
Syed Hasan Saeed, Integral University,
22
Lucknow
• There are four inputs D0, D1,D2, D3 and two outputs Y1 and Y2.
• D3 has highest priority and D0 is at lowest priority.
• If D3=1 irrespective of other inputs then output Y1Y0=11.
• D3 is at highest priority so other inputs are considered as don’t care.
K-map for Y1 and Y0
D1 D0 D1D0
D3D2 00 01 11 10 D3D2 00 01 11 10
00 X 0 0 0 00 X 0 1 1
01 1 1 1 1 01 0 0 0 0
11 1 1 1 1 11 1 1 1 1
10 1 1 1 1 10 1 1 1 1
Y1 D2 D3
Y0 D3 D2 D1
Fig. 16
Syed Hasan Saeed, Integral University,
23
Lucknow
LOGIC DIAGRAM OF PRIORITY ENCODER:
Y1 D2 D3
Y0 D3 D2 D1
D3 D2 D1 D0
Y1
Y0
Fig. 17
Syed Hasan Saeed, Integral University,
24
Lucknow
DECIMAL TO BCD ENCODER:
• It has ten inputs corresponding to ten decimal digits (from 0 to 9)
and four outputs (A,B,C,D) representing the BCD.
• The block diagram is shown in fig.18 and Truth table in fig.19
0
A
1
2 B
- - - - - - - - -
ENCODER
9 D
INPUTS OUTPUTS Fig. 18
Syed Hasan Saeed, Integral University,
25
Lucknow
Truth table:
INPUTS BCD OUTPUTS
0 1 2 3 4 5 6 7 8 9 A B C D
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1
Syed Hasan Saeed, Integral University,
Fig. 19
26
Lucknow
• From Truth Table it is clear that the output A is HIGH when input is
8 OR 9 is HIGH
Therefore A=8+9
• The output B is HIGH when 4 OR 5 OR 6 OR 7 is HIGH
Therefore B=4+5+6+7
• The output C is HIGH when 2 OR 3 OR 6 OR 7 is HIGH
Therefore C=2+3+6+7
• Similarly D=1+3+5+7+9
Logic Diagram is shown in fig.20
Syed Hasan Saeed, Integral University,
27
Lucknow
DECIMAL TO BCD ENCODER
+5V
0
1
2
3
4
5
6
7
8
9
A B C D Fig. 20
Syed Hasan Saeed, Integral University,
28
Lucknow
OCTAL TO BINARY ENCODER:
• Block Diagram of Octal to Binary Encoder is shown in Fig. 21
• It has eight inputs and three outputs.
• Only one input has one value at any given time.
• Each input corresponds to each octal digit and output generates
corresponding Binary Code.
D0
D1 X
D2
D3 ENCODER
Y
D4
D5
D6 Z
D7 Fig. 21
INPUT OUTPUT
Syed Hasan Saeed, Integral University,
29
Lucknow
TRUTH TABLE:
INPUT OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
Fig. 22
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Syed Hasan Saeed, Integral University,
30
Lucknow
From Truth table:
X D 4 D5 D 6 D 7
Y D 2 D3 D6 D7
Z D1 D3 D5 D 7
• It is assume that only one input is HIGH at any given time. If two outputs
are HIGH then undefined output will produced. For example D3 and D6
are HIGH, then output of Encoder will be 111. This output neither
equivalent code corresponding to D3 nor to D6.
• To overcome this problem, priorities should be assigned to each input.
• Form the truth table it is clear that the output X becomes 1 if any of the
digit D4 or D5 or D6 or D7 is 1.
• D0 is considered as don’t care because it is not shown in expression.
• If inputs are zero then output will be zero. Similarly if D0 is one, the
output will be zero.
•
Syed Hasan Saeed, Integral University,
31
Lucknow
X D 4 D5 D 6 D 7
Y D 2 D3 D6 D7
Z D1 D3 D5 D 7
LOGIC DIAGRAM:
D0 D 1 D2 D3 D4 D5 D6 D7
X D 4 D5 D 6 D 7
Y D 2 D3 D 6 D 7
Z D1 D3 D5 D7
Fig. 23
Syed Hasan Saeed, Integral University,
32
Lucknow
THANK YOU
Syed Hasan Saeed, Integral University,
33
Lucknow
