INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

DIGITAL CIRCUITS AND SYSTEMS

LAB MANUAL FOR

III YEAR/ V SEMESTER B.TECH (EE)

LAB CODE (EE-306)

INTEGRAL UNIVERSITY

DEPARTMENT OF ELECTRICAL
ENGINEERING
INTEGRAL UNIVERSITY
DASAULI KURSHI ROAD, LUCKNOW-226026
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

EXPERIMENT LIST

1 .Realize OR, NOR, XOR, XNOR gates using NAND gate and verify its truth
table.
2. Design and study of 1-bit Magnitude Comparator.
3. Design of Shift Registers.
4. (a) Design and test a CODE CONVERTER from decimal number to binary
number. Use diode and LED’s.
(b) Measure voltage drop across the diodes, LED’s and resistor R. Find the
current flowing through LED.
5.(a)Assemble the half Adder circuit using X-OR and AND gates. Verify the truth
table for Half Adder.
(b)Using two Half Adder and an OR gate, assemble Full Adder circuit, verify
truth table.
(c)Express sum and carry with all the minterms in minimization possible ?
6. Display of decimal digits using 7-segments LED display and a suitable decoder.
(a)Use a BCD to 7 segment decoder 0-9 digits.
(b)Study the 7 segment LED display. Is it common anode or common cathode
type? What is a suitable value or R for bright display of digit?
(c)Design a BCD to 7 segment decoder using NAND gates. Use K-Maps and
don’t care terms to implement the design with minimum number of gates.
7. STUDY OF FLIP-FLOPS (F/F)
(a)Design and test J-K Master-Slave F/F IC 74LS76. Make special observation of
edge triggering present and clear.
(c)Make and test D-F/F and T-F/F and verify its truth table.
8. STUDY OF COUNTER
(a)Design MOD-10 Counter using Master – Slave F/F (7476) and logic gates
(7400 & 7408). Verify truth table.
9. Study and verify 4-bit adder / subtractor circuit using IC7483 and IC7486.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

10. STUDY THE X-OR GATE IC-MODULE (7486)

(a)Verify the truth table and record voltage levels.
(b) Design a 3-input X-OR gate using 2-input X-OR gate. Obtain its truth table.
F1= A BC
(c) Design a 3-input X-NOR gate using 7486 &7402. Obtain its truth table.
F2= AʘBʘC
(d) Find expressions of F1 and F2 as Sum of product (SOP) and compare F1 and
F2.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

EXPERIMENT NO.1
MAKE OR, NOR, Ex-OR, Ex-NOR GATES USING NAND GATE
OBJECT: Realize OR, NOR, Ex-OR, Ex-NOR gates using NAND gate and verify
its truth table.
APPARATUS REQUIRED:

Sl.No. APPARATUS SPECIFICATION QTY.

1. Digital Trainer - 01
kit
2. IC’s(NAND) 7400 02
3. Bread Board - 01
4. Connecting wires - As per
Requirement

CIRCUIT DIAGRAM:

OR GATE-
INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

OR Gate Using NAND Gate IC

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Ex-OR GATE And NOR GATE using IC 7400

Ex-NOR GATE USING IC 7400

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
Universal gates. Basic gates form these gates.

OR GATE:

The OR gate performs a logical addition commonly known as OR

Function. The output is high when any one of the inputs is high. The output is low
level when both the inputs are low.
NOR GATE:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

The NOR gate is a contraction of OR-NOT. The output is high when both
Inputs are low. The output is low when one or both inputs are high.

X-OR GATE:
The output is high when any one of the inputs is high. The output is low
When both the inputs are low and both the inputs are high.

X-NOR GATE:

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an

inverter. Its output is "true" if the inputs are the same, and" false" if the inputs are
different.

NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when
both inputs are low and any one of the input is low .The output is low level when
both inputs are high.

Procedure:
1. Connect the logic gates as shown in the diagrams.
2. Feed the logic signals 0 or 1 from the logic input switches in different
combinations at the
Inputs A & B.
3. Monitor the output using logic output LED indicators.
4. Repeat steps 1 to 3 for OR, NOR, EX – OR & EX-NOR operations.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

and compare the outputs with the truth tables.

OBSERVATION TABLE:
Truth Table For OR Gate-
A B Y
0 0 0
0 1 1
Truth Table For Ex.NOR Gate-
1 0 1
1 1 1 A B Y
0 0 1
0 1 0
Truth Table for Ex. OR Gate
1 0 0
A B Y 1 1 1
0 0 0
0 1 1
1 0 1
1 1 0

RESULT:
Different logic gates are constructed using NAND gates and their truth tables are
verified .

CONCLUSION:

Any Boolean expression can be realized using OR, NOR, EX-OR, NAND,
EXOR gates.

PRECAUTIONS:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

1. All the connections should be made properly.

2. IC should not be reversed.

EXPERIMENT NO.2

1-BIT MAGNITUDE COMPARATOR

. OBJECT: Design and study of 1-bit Magnitude Comparator

APPARATUS REQUIRED:

Sl.No. APPARATUS SPECIFICATION QTY.

1. Digital Trainer kit - 01
2. Bread Board - 01
3. NOT GATE IC 7404 01
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

4. X-OR GATE IC 7486 01

5. AND GATE IC 7408 01
6. Connecting wires - As per Req.

:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

CIRCUIT DIAGRAM
1-bit Magnitude Comparator
output A = B is pr

THEORY:

Another common and very useful combinational logic circuit is that of the Digital
Comparator circuit. Digital or Binary Comparators are made up from
standard AND, NOR and NOT gates that compare the digital signals present at
their input terminals and produce an output depending upon the condition of those
inputs.
table. Firstly, the circuit You may notice two distinct features about the comparator
from the above truth does not distinguish between either two “0” or two “1”‘s as an
oduced when they are both equal, either A = B = “0” or A = B = “1”. Secondly

the output condition for A = B resembles that of a commonly available logic gate,
the Exclusive-NOR or Ex-NOR function (equivalence) on each of the n-
bits giving: Q = A ⊕ B
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Digital comparators actually use Exclusive-NOR gates within their design for

comparing their respective pairs of bits. When we are comparing two binary or
BCD values or variables against each other, we are comparing the “magnitude” of
these values a logic “0” against a logic “1” which is where the term Magnitude
Comparator comes from.

As well as comparing individual bits, we can design larger bit comparators by

cascading together nof these and produce a n-bit comparator just as we did for
the n-bit adder in the previous tutorial. Multi-bit comparators can be constructed to
compare whole binary or BCD words to produce an output if one word is larger,
equal to or less than the other.

A very good example of this is the 1-bit Magnitude Comparator. Here,one, two

4-bit words (“nibbles”) are compared to each other to produce the relevant output
with one word connected to inputs Aand the other to be compared against
connected to input B as shown below.

PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

OBSERVATION TABLE:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

TRUTH TABLE:

RESULT: The truth tables of one bit comparator are verified.

CONCLUSION: One bit comparator for truth table is verified

.
PRECATIONS:
1. All the connections should be made properly.
2. IC should not be reversed

EXPERIMENT NO.3

SHIFT REGISTERS
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

OBJECT: Design of Shift Registers.

APPARATUS REQUIRED:

1.

Sl. No. APPARATUS SPECIFICATION QTY.

1. Digital Trainer kit - 1
2. IC’s (Dual JK 7476 1
master slave Flip
flop)
3. Inverters IC 7404 1
5. Connecting wires - As per Req.

CIRCUIT DIAGRAM:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

IC 7476 Pin configuration

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Fig. Circuit Diagram of 4 Bit Shift Register

THEORY:
Shift registers are a type of sequential logic circuit, mainly for storage of digital
data. They are a group of flip-flops connected in a chain so that the output from
one flip-flop becomes the input of the next flip-flop. Most of the registers possess
no characteristic internal sequence of states. All flip-flop is driven by a common
clock, and all are set or reset simultaneously. In these few lectures, the basic types
of shift registers are studied, such as Serial In - Serial Out, Serial In - Parallel Out,
Parallel In – Serial Out, Parallel In - Parallel Out, and bidirectional shift registers.
A special form of counter - the shift register counter, is also introduced

PROCEDURE:

1. Verify the gates.

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

2. Make the connections as per the circuit diagram.

3. Switch on Vcc.

4. Applying i/p and Check for the outputs.

5. The readings of outputs should be tabulated.

OBSERVATION TABLE :

Line INPUTS OUTPUTS

NO. Clear DATA CLK Q1 Q2 Q3 Q4
Pulses
1 0 0 0 0 0 0 0
2 1 1 0 0 0 0 0
3 1 1 1 1 0 0 0
4 1 1 2 1 1 0 0
5 1 1 3 1 1 1 0
6 1 1 4 1 1 1 1
7 1 0 5 0 1 1 1
8 1 0 6 0 0 1 1
9 1 0 7 0 0 0 1
10 1 0 8 0 0 0 0
11 1 1 9 0 0 0 0
12 1 1 10 1 0 0 0

RESULT: Designing of shift Register is done.

CONCLUSION: Shift Register using J-K Flip –Flop for truth table is verified.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

PRECAUTION:
1. All the connections should be made properly.
2. IC should not be reversed

EXPERIMENT NO.4
CODE CONVERTER
OBJECT:
INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

• Design and test a CODE CONVERTER from decimal number to binary

number. Use diode and LED’S.
• Measure voltages drop across the diodes, LED’s and resistor R. Find the
current flowing through LED’s.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

APPARATUS REQUIRED:

Sl.No. APPARATUS SPECIFICATION QTY.

1. Digital Trainer kit - 01
2. Diodes IN4148 15
3. LED - 1
4. Resistor 1k ohm 1
5. Connecting wires - As per Req.

THEORY:

Code Converters: A code converter is a circuit that makes two digital systems
using different codes for the same information. It means that a code converter is a
code translator from one code to the other. The code converter is used since to
systems using two different codes but they need to use the same information. So
the code converter is the solution

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code,
the input lines must supply the bit combination of elements as specified by code
and the output lines generate the corresponding bit combination of code. Each one
of the four maps represents one of the four outputs of the circuit as a function of
the four input variables..
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

PROCEDURE:

1 .Connections were given as per circuit diagram

2. Plug the IC chip into the breadboard.

3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground and
PIN14 = +5V.

4. Logical inputs were given as per truth table

5 .Observe the logical output and verify with the truth tables

6. Connect the inputs of the gate to the input switches of the LED

7. Connect the output of the gate to the output LEDs.

8. Once all connections have been done, turn on the power switch of the
breadboard

OBSERVATION TABLE:
Truth Table (1) -

Decima Binary Output

Y3 Y2 Y1 Y0
l Input
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Truth Table (2) -

Voltage Output
Y3 Y2 Y1 Y0
Across
Diode (V) 0.62 0.61 0.62 0.62
LED(V) 1.63 1.64 1.64 1.64
Resistor(v 1.24 1.25 1.24 1.24
)
current 1.63 1.64 1.64 1.64
through
LED
(max)
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

RESULT: Designing and testing of a code converter from decimal number to

binary number by using LED and diode has been done.
Voltage across,
Diode =……..
LED = ……..
Resistor = …….
Current flowing through LED =…….mA

CONCLUSION: Decimal number to binary number code converter has been

designed using LED diodes and its truth table verified.
PRECAUTIONS:
1. All the connections should be made properly.
2. IC should not be reversedDEPTT.OF ECE/EIE
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

EXPERIMENT NO. 5

ADDER

OBJECT: Study of Half Adder and Full Adder.

• Assemble the Half Adder circuit using X-OR and AND gates. Verify the
truth table for Half Adder.

• Using two Half Adder and OR gate, assemble Full Adder circuit, Verify
truth table.

• Express sum and carry with all the minterms. Is minimization possible?

APPARATUS REQUIRED:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Sl.No. APPARATUS SPECIFICATION QTY.

1. Digital Trainer kit - 01

2. IC’s 7408,7432,7486 03

3. Bread Board - 01

4. Connecting wires - As per Req.

CIRCUIT DIAGRAM:

Fig: Circuit Diagram of Half Adder

Boolean Expression: Sum= A B; Carry =AB

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Fig : Circuit Diagram Of Full Adder

Boolean Expression: S= A B Ci; Carry Out (Co) =AB+Ci(A B) ;

THEORY:

Half Adder: A half adder is a logical circuit that performs an addition operation
on two binary digits. The half adder produces a sum and a carry value which are
both binary digits.

Full Adder: Full adder is a logical circuit that performs an addition operation on
three binary digits. The full adder produces a sum and carry value, which are both
binary digits. It can be combined with other full adders or work on its own.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

PROCEDURE:

• Collect the components necessary to accomplish this experiment.

• Plug the IC chip into the breadboard.

• Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.

• According to the pin diagram of each IC mentioned above, make the

connections according to circuit diagram.

• Connect the inputs of the gate to the input switches of the LED.

• Connect the output of the gate to the output LEDs.

• Once all connections have been done, turn on the power switch of the
Bread board

• Operate the switches and fill in the truth table (Write "1" if LED is ON
and"0" if LED is OFF apply the various combinations of inputs according to
the truth table and observe the condition of Output LEDs.

OBSERVATION TABLE:

TRUTH TABLE:

HALF ADDER

A B S C
0 0 0 0
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER

INPUT OUTPUT
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1

RESULT:

Function of Half Adder & Full Adder using two adder and OR gate is verified

CONCLUSION:

• To add two bits we require one EXOR gate(IC 7486) to generate Sum and one
AND (IC 7408) to generate carry.

• To add three bits we require two half adders.

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

PRECAUTIONS:

• All the connections should be made properly.

• IC should not be reversed.

EXPERIMENT NO. 6

OBJECT: Display of decimal digits using 7 segments LED display and a suitable
decoder.

(a) Use a BCD to 7 segment decoder 0-9 digits.

(b) Study the 7 segment LED display. Is it common anode or common cathode
type? What is a suitable value of R for bright display of digit?

(c) Design a BCD to 7-segment decoder using NAND gates. Use K-maps
and don't care terms to implement the design with minimum number of
gates.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

APPARATUS REQUIRED:

S.NO. APPARATUS QUANTITY SPECIFICATIONS

NAME
1. Digital Trainer Kit 1 Vinytics
2. 7 segment LED 1 SP5501/LTS542
display
3. IC 1 7446/7447
4. Connecting Wires As Required -

CIRCUIT DIAGRAM:

IC 7446/7447 Pin Configuration

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Fig.Connection of IC 7447 to 7-segment LED

THEORY:

LED is the best known of all optoelectronic devices, which emits a fairly narrow
bandwidth of visible or invisible light when its interval diode junction is stimulated
by a forward electronic current/voltage. The operation of LED is based on the
phenomenon of electro luminance under the influence of an electric field. As the
recombination of charge carriers take place in a forward PN junction as the
electrons cross from N region and recombine with holes emitting in P region. Free
electrons are in the conduction band of energy levels, while holes are in volume
energy band. Therefore, the electrons are at high energy level than the holes. For
the electrons to

Recombine with holes they must give some of their energy. These electrons get
energy in the form of heat and light.

LED emits no light when reverse biased. Digital watches, pocket calculators and
other digital instruments are example of devices that use such displays. The best
known display of this type is known as the seven segment display. It comprises
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

seven independently accessible photoelectric segments arranged in figure. The

segments are conventionally noted from a to g in manner as shown in the figure.

Truth Table:-

INPUTS OUTPUTS
Decima A B C D a b c d e f g
l
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1

Binary Coded Decimal

Decimal
D C B A Value

0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

1 0 0 0 8
1 0 0 1 9

Result: - Display of decimal digits using 7-segments is done and design and
minimization through K-Map is completed.

And the value of R for bright display of the digit is ……… ohm.

EXPERIMENT NO.7

FLIP- FLOP

OBJECT: Study of Flip – Flops.

• Design and test J-K, Flip Flop using NAND gates.
• Study J-K Master- Salve F/F IC 74LS76. Make special observation of
triggering, preset and clear.
• Make and test D-F/F and T-F/F , verify its truth table.
APPARATUS REQUIRED:

S.NO. APPARATUS SPECIFICATION QTY

1. IC’s 7476 , 7404 ,7410 03
2. Digital Trainer kit - -
INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

3. Bread Board - 01
4. Connecting wires & leads - As Per Req.

JK Flip Flop Using IC 7410 Pin Connections

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

D Flip Flop Using IC 7476

and IC 7404 T Flip Flop Using IC 7476 and IC 7404

IC 7410 pin configuration

IC 7410 pins

D-Flip-Flop
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

THEORY:

Sequential Logic circuits: In digital circuit theory, sequential logic is a type of

logic circuit whose output depends not only on the present input but also on the
history of the input. This is in contrast to combinational logic, whose output is a
function of, and only of, the present input. In other words, sequential logic has
state (memory) while combinational logic does not. The memory elements are
devices capable of storing binary info. The binary info stored in the memory
elements at any given time defines the state of the sequential circuit. The input and
the present state of the memory element determine the output. Memory elements
next state is also a function of external inputs and present state. A sequential circuit
is specified by a time sequence of inputs, outputs, and internal states.

Flip Flop: In electronics, a flip-flop is a circuit that has two stable states and can
be used to store state information. The circuit can be made to change state by
signals applied to one or more control inputs and will have one or two outputs.
Flip-flops and latches are used as data storage elements. There are four types of
flip flops. These are SR, D, JK and T. On this experiment we will explore the
operation of JK flip flop.

JK flip flop: JK flip flop is considered as the universal flip flop. When configured
in various ways, it is capable of operating like most other types of flip flop.A JK
flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR
type is defined in the JK type. Inputs J and K behave like inputs S and R to set and
clear the flip-flop. When logic 1 inputs are applied to both J and K simultaneously,
the flip-flop switches to its complement state, i.e., if Q=1, it switches to Q=0 and
vice versa.   In that way it is like a toggle. A clocked JK flip-flop is shown below.
Output Q is AND with K and CLK inputs so that the flip-flop is cleared during a
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

clock pulse only if Q was previously 1. Similarly, output Q’ is AND with J and
CLK inputs so that the flip-flop is set with a clock pulse only if Q’ was previously
1.
PROCEDURE:

• Collect the components necessary to accomplish this experiment.

• Plug the IC chip into the breadboard.
• Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
• According to the pin diagram of each IC mentioned above, make the
connections according to circuit diagram.
• Connect the inputs of the gate to the input switches of the LED.
• Connect the output of the gate to the output LEDs.
• Once all connections have been done, turn on the power switch of the Bread
board
• Operate the switches and fill in the truth table ( Write "1" if LED is ON and
"0" if LED is OFF apply the various combinations of inputs according to the truth
table and observe the condition of Output LEDs.
OBSERVATION TABLE:

TRUTH TABLE OF J-K FLIP-FLOP:

Input Output
Jn Kn Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Toggle
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

TRUTH TABLDE OF T-FLIP-FLOP:

Input Output
CLK T Qn+1
0 0 Qn
1 1 Qn

TRUTH TABLE OF D-FLIP-FLOP:

Input Output
CLK T Qn+1
0 0 0
1 1 1

RESULT: The truth table of D-Flip-Flop, T-Flip-Flop and J-K Flip- Flop are
verified

CONCLUSION: The function table of JK Flip- Flop, D-Flip-Flop, and T-Flip-

Flop using IC 7410 as been verified.

Discussion Questions:
1. What is D flip flop?
2. What is the function of D flip flop?
3. What is JK flip flop?
4. What is the disadvantage of JK flip flop?
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

5. What is SR flip Flop?

6. What is the difference between a Latch and a FLIP-FLOP?

PRECATIONS:

1. All the connections should be made properly.

2. IC should not be reversed.

EXPERIMENT NO.8

COUNTER

OBJECT: Design MOD-10 counter using Master –Slave Flip Flop verify its

truth table.

APPARATUS REQUIRED:

S.NO. APPARATUS SPECIFICATION QTY

1. IC’s 7476 , 7408 ,7400 03
2. Digital Trainer - -
kit
3. Bread Board - 01
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

4. Connecting - As Per Req.

wires & leads

CIRCUIT DIAGRAM:

Fig. MOD-10 Asynchronous Counter using IC 7476, IC 7400 and IC 7408

 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

IC 7476 Pins configuration

THEORY:

A Mod-10 counter has 10 possible states, in other words it counts from 0 to 9 and
rolls over. Let's take a look at how to build a Mod-10 counter

The first step is to determine how many flip-flops to use. We will use JK FFs for
our design. Since we need 10 states, 4 FFs will be required. The trick is to find a
way not to use all of those states. There must be a way to force the counter to stop
counting at 9 and roll over to 0. This is where asynchronous inputs come into play.
The asynchronous inputs can over-ride the synchronous inputs and force the
outputs to either LOW or HIGH.
Looking at the truth table, the counter should run from 0000 to 1001 and roll over
to 0000 again. Since the counter has to display 1001, the next binary value 1010
will be used to reset the counter to 0. For a JK FF, we have an asynchronous input
called CLEAR, when you assert this, flop's output goes to 0. Since this CLEAR
input is active high, we can use AND gate. The 2 FFs where a '1' occurs will be
tied to an AND gate and the output will be tied to a CLEAR
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

input. When the counter goes to 1001, the AND gate has a value '1' on its output
and will activate the CLEAR inputs of all FFs

PROCEDURE:

1. Connections are made as per the circuit diagram

2. Switch on the power supply.
3. Apply clock pulses and note the outputs after each clock pulse and note
done the outputs Q3,Q2, Q1, Q0.
OBSERVATION TABLE:
TRUTH TABLE:

Result: Study of counter is designed and truth tables are verified.

CONCLUSION: The function table of counter and J-K-Flip-Flop using IC 7476

as been verified

PRECATIONS:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

1. All the connections should be made properly.

2. IC should not be reversed.

Questions:
1. What is counter? What is the function of counter?
2. What is the maximum count in MOD-10 counter can count?
3. How will you calculate number of flip –flop used in MOD-10 counter?
4.How many types are counter?

EXPERIMENT NO.9

ADDER / SUBTRACTOR
INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

OBJECT: Study and verify 4-bit adder / subtractor circuit using IC7483 and
IC7486.
APPARATUS REQUIRED:

S.NO. APPARATUS SPECIFICATION QTY

1. IC’s 7486 , 7483 02
2. Digital Trainer - -
kit
3. Bread Board - 01
4. Connecting - As Per Req.
wires & leads

CIRCUIT DIAGRAM:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

4-Bit ADDER/Subtractor

THEORY:

A four-bit adder/subtractor demonstration. While it is perfectly possible to design a

custom circuit for the subtraction operation, it is much more common to re-use an
existing adder and to replace a subtraction by a two-complement's addition.

The applet shows how this is done. Click the input switches or type the’s’ bind key to
control the Sub/n Add switch, and ‘1’, '8' to control the A and B inputs.

When the Sub/Add input is low (0), the XOR-gates act as non-inverting buffers and the
carry-input to the adder is 0. Therefore, the adder calculates a four-bit sum plus carry-out:

(Cout, S3, S2, S1, S0) = (A3, A2, A1, A0) + (B3, B2, B1, B0)

If the Sub/Add input is high (1), the XOR-gates act as inverting buffers, and the carry-
input to the adder is 1.

(Cout, S3, S2, S1, S0) = (A3, A2, A1, A0) - (B3, B2, B1, B0)
PROCEDURE:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

1-Apply the input to A0 to A0 and B0 to B3.

2-Connect C0 carry output and Cin carry input.
3-Check the output sum on the S0 to S3 and also C0
4-The truth table of adder and subtractor are noted down.

OBSERVATION TABLE: D3D2D1 D0

Cin=0 C4 C3 C2 C1 C0 Carries
A4 A3 A2 A1 A0
B4 B3 B2 B1 B0
+
C4 S3 S2 S1 S0 Sum

Cin=1 A3 A2 A1 A0
B3 B2 B1 B0

D3 D2 D1 D0 Difference

TRUTH TABLE OF SUM/SUBTRACTOR

INPUT OUPUT
Cin A3 A2 A1 A0 B3 B2 B1 B0 Co S3/D3 S2/D2 S1/D1 S0/D0
0 1 1 1 0 0 0 0 1 0 1 1 1 1
0 1 1 1 1 1 1 0 1 1 1 1 1 0
0 0 0 1 1 1 0 0 0 0 1 0 1 1
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1 1 1 1 0 0
1 1 0 0 0 1 0 0 0 1 0 0 0 0
1 1 1 0 1 1 1 0 0 1 0 0 0 1

RESULT: study of 4-bit ADDER / SUBTRACTOR is done.

CONCLUSION: Thus 4-bit ADDER / SUBTRACTOR is studied.

PRECATIONS:
1. All the connections should be made properly.
2. IC should not be reversed.

EXPERIMENT NO. 10

OBJECT: STUDY THE X-OR GATE IV MODULE (7486)

(a) Verify the truth table and record the voltage levels.

(b) Design a 3-input X-OR gate using 2-input X-OR gate. Obtain its truth table
F1= A BC

(c) Design a 3-input X-NOR gate using 7486 & 7402. Obtain its truth table.F2=Aʘ
Bʘ C
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

(d) Find the expression of F1and F2 as sum of product (SOP) and compare F1and
F2 .
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

APPARATUS REQUIRED:

S.NO. APPARATUS QUANTITY SPECIFICATIONS

NAME
1. Digital Trainer Kit 1 Vinytics
2. IC's 2 7486 & 7402
3. Connecting Wires As Required -

CIRCUIT DIAGRAM:

X-OR GATE:
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

 3-INPUT Ex- OR GATE:

3-INPUT Ex-NOR GATE:

THEORY:

EX-OR (Exclusive OR) gate

An X-OR gate is a gate with two or more input and one output. The output of the
two input EX-OR gate assumes a HIGH state. This is equivalent to saying that the
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

output is HIGH. If either input A or input B is HIGH and LOW when both are 0 or
1 simultaneously. The exclusive features eliminates a similarity to the OR gate.
The EX-OR gate respond with the high output only when an odd number of input
is HIGH. When there is an even number of HIGH input such as two or four, the
output will always be LOW.

The main characteristic property of X-OR gate is that it can perform module 2
addition A 2- input. X-OR circuit is sometimes called a module 2 adder or half
adder without carry output.

EX-NOR (Exclusive NOR) gate

The Exclusive NOR gate is EX-OR gate followed by an inverter. It has two or
more inputs and one output. The output of two input EX-NOR gate assumes a
HIGH state if both the input assume the same logic state or have an even number
of its output is LOW when the input assume different logic states or have an odd
number of outputs.
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Observation Table:-

A B C Three input Three Input

X-OR X-NOR

Y=A BC Y= AʘBʘC

0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
 INTEGRAL UNIVERSITY LUCKNOW, DCS LAB (EE-306) MANUAL

Result:-

Study the X-OR Gate IC Module is completed