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313303 - Digital Techniques (Sem III)

As per MSBTE’s K Scheme
CO / CM / IF

Unit V Data Convertors and Memories Marks – 18

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1 Draw the block diagram of Programmable Logic Array. W-18 4

W-19 4

S-22 4

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2 Calculate analog output of 4 bit DAC for digital input 1101. Assume VFS = 5V W-18 4

V0 = 4.33V

3 Describe the working of successive Approximation ADC. Define Resolution and W-18 6
conversion time associated with ADC.

Circuit Diagram:

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 When the start signal goes low the successive approximation register SAR
is cleared and output voltage of DAC will be 0V. When start goes high the
conversion starts.
After starts, during first clock pulse the control circuit set MSB bit so SAR
output will be 1000 0000. This is connected as input to DAC so output of DAC is
(analog output) compared with Vin input voltage. If VDAC is more thanVin the
comparator output –Vsat, if VDAC is less than Vin, the comparator outputis +Vsat.
If output of DAC i.e. VDAC is + Vsat (i.e unknown analog input
voltage Vin> VDAC) then MSB bit is kept set, otherwise it is reset.
Consider MSB is set so SAR will contain 1000 0000.
The next clock pulse will set next bit i.e D6 a digital output of 1100 0000. The output
voltage of DAC i.e VDAC is compared with Vin, if it is + Vsatthe D6 bit iskept as it is,
but if it is –Vsat the D6 bit reset.
The process of checking and taking decision to keep bit set or to reset is
continued upto D0.
Then the DAC input will be digital data equal to analog input.
When the conversation if finished the control circuits sends out an end of conversion
signal and data is locked in buffer registerResolution: The voltage input change
necessary for a one bit change in the output is called resolution.

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Conversion Time: The conversion time is the time required for conversion from an
analog input voltage to the stable digital output

OR

Circuit Diagram:

Explanation:

DAC= Digital to Analog converterEOC=

End of conversion
SAR =Succesive approximation registerS/H=
Sample and hold circuit
Vin= input voltage Vref=
reference voltage
The successive approximation Analog to Digital converter circuit typically
consisting of four sub circuits-
1. A sample and hold circuit to acquire the input voltage Vin.
2. An analog voltage comparator that compares Vin to the output of internalDAC
and outputs the result of comparison to successive approximation register(SAR).
3. SAR sub circuits designed to supply an approximate digital code of Vin tothe
internal DAC.
4. An internal reference DAC that supplies the comparator with an analog
voltage equivalent of digital code output of SAR for comparison with Vin.

The successive approximation register is initialized so that most significant bit (MSB)
is equal to digital 1. This code is fed into DAC which the supplies the analog equivalent
of this digital code Vref/2 into the comparator circuit for the comparison with
sampled input voltage. If this analog voltage exceeds Vin the comparator causes the

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 SAR to reset the bit, otherwise a bit is left as 1. Then the

next bit is set to 1 and the same test is done continuing this binary search until
every bit in the SAR has been tested. The resulting code is the digital
approximation of the sampled input voltage and is finally output by DAC at end of
the conversion (EOC).

Resolution and conversion time associate with ADC-

Resolution:
It is the maximum number of digital output codes.
Resolution= 2^n(OR)
It is defined as the ratio of change in the value of input analog voltage requiredto
change the digital output by 1 LSB.

Conversion time:
The time difference between two instants i.e. 'to' where SOC signal is given asinput
to the ADC and 't1' where EOC signal we get as output from ADC. it should be small
as possible.

4 Compare the following (Any three points) W-18 6

(i) Volatile with Non-volatile memory

(ii) SRAM with DRAM memory

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 Parameter Volatile memory Non-Volatile memory
definition Memory required Memory that will
electrical power to keepstoring its
keepinformation informationwithout
stored is called the need of electrical
volatile memory power is called
nonvolatile
memory.
classification All RAMs ROMs, EPROM,
magnetic memories
Effect of power Stored No effect of
informationis poweron stored
retained only as information
long as power is on.
applications For For permanent
temporary storage of
storage informatio
n
2. SRAM with DRAM memory

Parameter SRAM DRAM

Circuit configurationEach SRAM cell is Each cell is one
a flip flop MOSFET & a capacitor
Bits stored In the form of In the form of charges
voltage
No of components per More Less
cell
Storage capacity Less More
Refreshing It does not require It require refreshing.
refreshing
Cost It is expensive It is cheaper
Speed It is faster It is slower
comparatively
5 List the types of DAC W-19 2

1) Binary weighted DAC

2) R –2R ladder network DAC
6 Calculate the analog output for 4 bit weighted register type DAC for inputs W-19 6

(i) 1011

(ii) 1001

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 Assume (Vfs) full scale range of voltage

Given:
VR = Vfs = 5V
Formula Used:
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 )
1. 1011
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 )

= - 5 (1*1/2 + 0 + 1*1/23 + 1 *1/24 )

= - 5 (1*1/2 + 1*1/8 + 1 *1/16)
= - 5 (0.5 + 0.125 + 0.0625) =
3.4375V Vo = 3.4375 V
2. 1001
Vo = - VR (B1.2-1 + B2.2-2 + B3.2-3 + B4.2-4 )
= - 10 (1*1/2 + 0 + 0 + 1 *1/24 )
= - 10 (1*1/2 + 0 + 0 + 1 *1/16)
= - 10 (0.5 + 0.0625) = 2.8125V Vo = 2.8125 V

7 State two specification of DAC S-19 2

1. Resolution:
Resolution is defined as the ratio of change in analog output voltage resulting from a
change of 1 LSB at the digital input VFS is defined as the full scale analog output
voltage i.e. the analog output voltage when all the digital input with all digits 1.
Resolution = VFS /(2n −1)
2. Accuracy:
Accuracy indicates how close the analog output voltage is to its theoretical value. It
indicates the deviation of actual output from the theoretical value. Accuracy
depends on the accuracy of the resistors used in the ladder, and the precision of the
reference voltage used. Accuracy is always specified in terms of percentage of the
full scale output that means maximum output voltage
3. Linearity:
The relation between the digital input and analog output should be linear.
However practically it is not so due to the error in the values of resistors used for
the resistive networks.
4. Temperature sensitivity:
The analog output voltage of D to A converter should not change due to changes in
temperature.
But practically the output is a function of temperature. It is so because the resistance
values and OPAMP parameters change with changes in temperature.
5. Settling time:
The time required to settle the analog output within the final value, after the change
in digital input is called as settling time.
The settling time should be as short as possible.

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 6. Long term drift
Long term drift are mainly due to resistor and semiconductor aging and can affect all
the characteristics.
Characteristics mainly affected are linearity, speed etc.
7. Supply rejection
Supply rejection indicates the ability of DAC to maintain scale, linearity and other
important characteristics when the supply voltage is varied.
Supply rejection is usually specified as percentage of full scale change at or near full
scale voltage at 25oe
8. Speed:
It is defined as the time needed to perform a conversion from digital to analog. It is
also defined as the number of conversions that can be performed per second.

8 Give classification of memory and compare RAM and ROM (any four points). S-19 4

classification of memory

Comparison between RAM and ROM

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10
9 Compare between PLA and PAL. S-19 4

10 Draw the circuit diagram of 4 bit R-2R ladder DAC and obtain its output voltage S-19 6
expression.

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 Therefore

output analog voltage V0 is given by,

11 State two features of ADC IC0809. W-22 2

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12 Calculate the analog output of 4 bit DAC if the digital input is 1101. Assume VFS = W-22 4
5V

13 Compare between R-2R ladder DAC and weighted resistor DAC (Four points). W-22 4

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14 Compare following (Any three points) W-22 6

i) RAM with ROM memory.

ii) EPROM with EEPROM memory

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15
15 List any two specifications of IC-DAC 0808 S-22 2

16 Compare the following: (Any two points each) S-22 4

(i) Volatile - Nonvolatile memory

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(ii) SRAM - DRAM memory

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17 Calculate analog o/p of 4 bit DAC for digital input is 1100. Assume VFS = 5V S-22 4

18 List the types of DAC. W-23 2

19 State two features of ADC IC0809. W-23 2

20 List the types of semiconductor memories. W-23 2

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21 Draw and explain the block diagram of Programmable Logic Array (PLA). W-23 4

22 Draw and explain the block diagram of dual slope ADC. Also write its W-23 8
specifications.

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Working :
Above Fig. shows the functional block diagram of a Dual-Slope ADC. It consists of
four major blocks: 1. an integrator, 2. a comparator, 3. a binary counter and 4. a
switch driver, 5.T flip-flop.
This circuit is provided with a single-pole double throw electronic switch. The
initial state of the circuit is such that:
1. The output of the integrator is small and positive, so that the output of the
comparator is low. Thus, the AND gate is disabled.
2. The counter is kept reset, so that Y output of all flip-flops in the counter are
reading
3. The toggle mode flip-flop is kept reset.
The conversion process begins at t=0 with the switch S1 position 0 thereby
connecting the analog voltage Vx to the input of the integrator.
The integrator output is:

This results in high Vcr thus enabling the AND gate and the clock pulses reach the
clock (clk) Input terminal of the counter which was initially clear. The counter counts
from 00…. 00 to 11….. 111 when 2N-1 clock pulses are applied.
At the next clock pulse 2 N, the counter is cleared and Q becomes 1. This controls the
state of S1 which now moves to position 1 at T1 thereby connecting -VR to the input
of the Integrator. The output of the Integrator now starts to move in the positive
direction. The counter continues to count until V0 < 0 As soon as V0 goes positive at
T2, Vc goes low enabling the AND gate. The counter will counting in the absence ofthe
clock pulses. The waveforms of voltages V0 and Vc are shown in below Fig.

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23 Name the types of RAM S-23 2

24 Define PLA. Draw its block diagram S-23 4

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25 A combinational circuit is defined as F1 = ∑m(3, 5, 7) and F2 = ∑m(4, 5, 7). S-23 4
Implement the circuit with a PLA having 3 inputs, 3 product terms and 2
outputs.

26 Write applications of ADC and DAC. S-23 4

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27 Explain classification of memories. What is flash memory? S-23 6

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24
28 List any two specification of IC 0809 S-24 2

Specifications of IC 0809:
1) Input voltage range: 0 to 5 V
2) Power consumption: Less than 15 mW
3) Conversion time:100 µsec
4) Power Supply voltage: 5V
5) Resolution: 28
OR

1) Resolution: It is defined as the maximum number of digital output codes.

Resolution = 2n or VFS / 2n-1
2) Conversion time: It is the total time required to convert the analog input
signal into a corresponding digital output.
Quantization error: The error due to quantization process is called asquantization
error.

29 Name the basic building block used in CPLD and state their functions. S-24 4

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 The basic building blocks used in CPLD are:
1) PAL – like blocks
2) Input /Output (I/O) blocks
3) Interconnecting wires
Their functions are as below:
1) PAL – like blocks:
 Each PAL like block is made of 16 macrocells.
 Inside each microcell there is an AND-OR combination the outputof
which is applied to an EX-OR gate, flip-flop, multiplexers and
tristate buffers.
 Every AND-OR combination contains up to about 20 AND gatesand
1 OR gate.
The OR gate output is connected to the input of a EX-OR gate.

 The EX-OR gate can invert its input if one end of it is connected to1.
 It will not invert the OR gate output if one end of it is connected to0.
 The EX-OR gate output is stored into a D FF.
 The output of this flip flop along with the output of the EX-OR gateis
applied to the inputs of a 2: 1 multiplexer. A multiplexer will connect
either the FF's output or the EX-OR gate output to the tristate buffer
depending on the state of its select input either 0 or 1.
 The tri-state buffer acts as a switch. Its output is connected to I/O
pin of the IC. This pin of the chip acts as output if the buffer is
enabled and the same pin acts as input pin if the buffer is disabled.
But if the pin is used as input pin, then the macrocell is disabled.
2) Input/output ( I/O) block: The PAL like blocks are connected to the I/O
blocks and to the interconnecting wires.
Interconnecting wires: Various blocks of CPLD are interconnected witheach
other via interconnecting wires

30 Calculate the analog output of 8-bit DAC for digital input 10011100 Assume V S-24 4
full-scale =5v

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 Analog output of 8 -Bit DAC Vo = 3.061 volts

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