EE-721 : lec2
SBP
EE, IITB
2nd Aug 2019
3 sections of a VHDL design
1. Usage declarations for library and package
2. Entity declaration
3. Architecture declaration
3 sections of a VHDL design
1. Usage declarations for library and package
2. Entity declaration
3. Architecture declaration
std_logic_1164 package of
ieee library contains std_logic
etc.
library ieee;
all declarations inside this
use ieee.std_logic_1164.all;
package
entity nand_gate is
port ( a , b : in std_logic ; c : out std_logic );
end nand_gate ;
architecture a1 of nand_gate is
begin
z <= a NAND b;
end a1;
Simulate and validate
library IEEE;
use IEEE.std_logic_1164.all; the unit under test
use ieee.numeric_std.all ; that is an instance of
testbench a nand_gate design entity
entity nand_gate_test is
end nand_gate_test ; No ports on a testbench
architecture t1 of nand_gate_test is
component nand_gate
PORT( a : IN STD_LOGIC; b : IN STD_LOGIC;
z : OUT STD_LOGIC);
end component;
signal a,b,z : std_logic ; more apt names sig_a, sig_b, sig_z
begin
uut : nand_gate port map ( a => a , b => b , z => z );
-- ...... stimulus code to be added .....
end t1 ;
arbitrary function
generator
compatible for nand_gate
oscilloscope
Most of these ideas to be discussed in later lectures ..
just making you aware that verification needs many
begin
facilities from vhdl
uut : nand_gate port map ( a => a , b => b , z => z );
test_pr : process
variable ab : std_logic_vector( 1 downto 0 ) ;
variable abz : std_logic_vector( 2 downto 0 ) ;
begin from numeric_std package
for i in 0 to 3 loop
ab := std_logic_vector( to_unsigned(i,2) ) ;
(a,b) <= ab ; convert integer to
wait for 11 ns ; 2 bit unsigned
abz := std_logic_vector’((a,b,z)) ;
report "input / outputs are " &
integer’image( to_integer( unsigned( abz ) ) )
severity Note ;
end loop ;
wait ;
end process ;
end t1 ;
prompt> ghdl -a --workdir=work nand_gate_with_test.vhd
prompt> ghdl -e --workdir=work nand_gate_test
prompt> ghdl -r --workdir=work nand_gate_test
--stop-time=200ns --vcd=wave.vcd
prompt> gtkwave wave.vcd
RUN
i=0 i=1 i=2 i=3
Figure: Caption
Design units
The VHDL models are built using different kinds of units.
There are two classes of VHDL design units :
� the primary design units : entity, configuration, package
� the secondary design units : architecture body , package body
similar to header files and the
library archives ".a", ".so",
".dll" etc of C/C++ programming
realm
� A package is a collection of logically related declarations.
� They typically are used to contain sets of type subtypes,
constants declarations etc..
� May also contain component declarations , subprograms etc..
Did not discuss this slide .. would come back
to this in later lectures
� Normally a package is defined in two parts:
� a package declaration, which defines the visible contents of a
package, and
� a package body, which provides the implementation details of
subprograms and the actual values of deferred constants.
� The body part may be omitted if there are no subprogram
implementations or deferred constants.
package simple is
constant cdiff: integer := 200 ;
subtype word is bit_vector(15 downto 0);
subtype address is bit_vector (24 downto 0);
type mem is array (0 to 31) of word;
function address2int (val : address) return integer;
function increment_word(val : word) return word;
end simple;
Package body required for definitions of the two functions
address2int and increment word.
appears to be some declarations related
to CPU design
Did not discuss .. will come up in later lectures
package body simple is
address_to_int(value : address) return integer is
-- the definition of the function OMITTED
end address2int;
function increment_word( val : word) return word is
-- the definition of the function OMITTED
end increment_word;
end simple;
use clause use ieee.numeric_std.all ;
Items declared within a package become accessible by direct
selection:
variable pc: simple.address;
-- simple is the package name
or by the use clause:
use work.simple.address;
-- work is the name of working library where
-- the package is compiled
variable pc: address;
-- direct visibility
If all of the declared names in a package are to be used in this way,
you can indicate it through special suffix all , for example:
use work.simple.all ;
variable pc: address;
variable ram: mem;
Standard packages There are two predefined packages provided
with VHDL:
standard package including various data and type definitions (e.g.
bit vector, string, ..)
textio package including basic read/write procedures (e.g. read,
readline, write, writeline, ..)
explicitely specified library
examples of implicitely specified libraries
explicitely specified library
recall
ghdl -a --workdir=work recall that work library is the directory
xyz.vhd containing compiled versions of the current design units
package standard is
type severity_level is ( note, warning, error, failure);
type boolean is ( false, true);
type bit is ( ‘0’, ‘1’) Enumerated types
type character is ( bit , boolean, character …
NUL, SOH, STX, ETX, ......, , ‘H’, ‘I’, ‘J’, ....);
type time is ...... ;
function now return time;
-- returns the current simulation time
subtype natural is integer range 0 to integer’high;
subtype positive is integer range 1 to integer’high;
type bit_vector is array (natural range <>) of bit;
type string is array (positive range <>) of character;
end standard;
More about types in later lectures
that objects of that type
can take and … operations on such values
32
patience !!!
proper details about "type" in
later lectures …
shall address any confusion
caused by this hurried discussion in later lectures properly
