Design Idea DI-124

®
LinkSwitch-TN
Ultra-wide Input Range (57-580 VAC) Flyback Power Supply

Application Device Power Output Input Voltage Output Voltage Topology

Metering / Industrial LNK304 3W 57-580 VAC 12 V, 250 mA StackFET Flyback

Design Highlights A 600 V MOSFET, Q1, and U1 are arranged in the StackFET
configuration (cascode). The drain of U1 drives the source
• StackFET flyback topology delivers full load over
TM
of Q1 while the drain of Q1 drives the transformer primary.
extremely wide input voltage range
The drain voltage of U1 is limited to 450 V by VR1-3. This
• E-ShieldTM transformer construction for reduced
extends the maximum peak composite drain voltage of U1
common-mode EMI (>10 dBµV margin)
and Q1 to 1050 V. The resistor chain R6-R8 provides startup
• 66 kHz switching frequency with jitter reduces
charge for the gate of Q1 and R9 dampens high-frequency
conducted EMI
ringing. Once the converter is operating, the gate is largely
• Simple ON/OFF controller – no feedback compensation
driven by the charge stored in the capacitance of VR1-3.
required
Zener VR4 limits the gate to source voltage of Q1. Leakage
• Auto-restart function for automatic and self-resetting
inductance energy is clamped by VR5 and D9 with R10 added
open-loop, overload and short circuit protection
to reduce ringing and thereby, EMI.
• Built-in hysteretic thermal shutdown at 135 ºC
The operation of U1 is unaffected by the StackFET
Operation configuration. When the internal MOSFET turns on, Q1 is also
The AC input is rectified and filtered and the resultant DC turned on, applying the input voltage across the transformer
applied to one end of the transformer primary winding. The primary. Once the primary current reaches the internal current
450 V input capacitors are stacked with parallel balancing limit of U1, the MOSFET is turned off and the energy stored
resistors to meet the required voltage rating. Resistors R1 to is delivered to the output. Regulation is maintained using
R4 provide fusing in case of a catastrophic failure. Inductor ON/OFF control. Switching cycles are enabled/disabled based
L1, C1 and transformer E-Shield windings allow the design on current into the FEEDBACK pin of U1. This is ideal as
to meet EN55022 B conducted limits with good margin. it results in a lowering of the effective switching frequency

C1
2.2 nF
250 VAC

D1 D2 D3 D4
1N4007 1N4007 1N4007 1N4007 VR5 D10
R6 EEL16 UF4004 L2
R13 R14 680 kΩ P6KE150A J5
475 kΩ 475 kΩ NC 4
C5 C6 0.5 W
15 µF 1% 15 µF 1% Ferrite Bead
0.5 W 0.5 W D9
J1 R1 450 V 450 V R7 UF4007 5
680 kΩ C2 C3
10 Ω 1 W C9 0.5 W 470 µF 100 µF
J2 R2 5.6 nF R10 7 16 V 16 V
1 kV R8 200 Ω 9
10 Ω 1 W R15 R16 680 kΩ 1%
475 kΩ 475 kΩ 0.5 W J6
J3 R3 C7 1% C8 1% 10 1
15 µF 0.5 W 15 µF 0.5 W
10 Ω 1 W 450 V 450 V T1
R9
J4 R4 10 Ω Q1
IRFBC20
10 Ω 1 W
R5 R11
1k VR4 330 Ω
1N5245B
D5 D6 D7 D8 VR1 15 V U2B U2A
D PC817A PC817A
1N4007 1N4007 1N4007 1N4007 L1 P6KE150A FB
1 mH U1
LNK304P BP
R12
VR2 S 1 kΩ
P6KE150A

C4 VR6
VR3 100 nF BZX79-C11
P6KE150A 50 V 11 V

PI-4487-081506

Figure 1. Schematic Diagram of 3 W Bias Supply using LinkSwitch-TN in StackFET Configuration.

DI-124 September 2006

 DI-89 DI-124

with load, scaling switching losses and maximizing efficiency. 80

PI-4493-081806
The use of LinkSwitch-TN further improves efficiency due to 75
its 66 kHz switching frequency.
70

Efficiency (%)
Key Design Points 65

60
• The input stage (to the left of C9) can be omitted in
applications that have a high-voltage DC bus. Capacitor 55
C9 is still required to provide local decoupling. 50
• Long cores (EEL) are ideal for this application to provide
45
greater bobbin width to accommodate the increased
margins required to meet safety spacings at the high 40
operating voltage. 50 150 250 350 450 550
• Zener diodes VR1-3 can be replaced with a single AC Input Voltage (V)
P6KE540 device.
Figure 3. Full Load Efficiency vs. Input Voltage.
• The value of capacitors C5 to C8 can be reduced to 10 µF
if operation down to 57 VAC is not required (100 VAC
minimum).
• Use 0.5 W resistors for R13-16 and R6-8 to provide TRANSFORMER PARAMETERS
adequate voltage rating. Core Material EEL16, gap for ALG of 70 nH/T2
• Efficiency falls at high line due to switching losses. 6+4 pin (Ying Chin YC-1604-1)
Reducing transformer capacitance by adding layers of Bobbin
with 3 mm + 3 mm tape margins
tape between the primary winding layers minimizes this.
Shield: 23T, 2 × 36 AWG
Primary: 184T, 36 AWG
80 Winding Details
Shield: 12T, 2 × 29 AWG
PI-4492-090706

EN55022B Limits
70 Secondary: 30T, 29 AWG TIW
QP
60 Shield (5-NC), tape, primary
50
AV Winding Order (7-5), tape between layers,
(pin numbers) shield (9-10), tape, 12 V / (4-1),
40 tape
dBµV

30 QP Primary: 3.5 mH ±10%

Inductance
20 Leakage: 160 µH (max)
10 AV Primary Resonant
500 kHz (min)
Frequency
0
Table 1. Transformer Design Parameters.
-10
TIW = Triple Insulated Wire, NC = No Connect, FL = Flying Lead
-20
0.15 1.0 10.0 100.0
MHz
Figure 2. Conducted EMI (230 VAC, EN55022B Limits,
AV and QP Results).

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Rev. A 09/06