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Ingenuity is our regular round-up of readers' own Oscilloscope
circuits. We pay between $16 and $80 for all material • 50MSPS Dual Channel Storage
published, depending on length and technical merit. Oscilloscope
We're looking for novel applications and circuit tips, not
• 25MHz Spectrum Analyzer
simply mechanical or electrical ideas. Ideas must be the
reader's own work and must not have been submitted • Multimeter
for publication elsewhere. The circuits shown have • Frequency Meter
NOT been proven by us. Ingenuity Unlimited is open to
• Signal Generator
ALL abilities, but items for consideration in this column
should preferably be typed or word-processed, with a If you have a novel circuit idea which
brief circuit description (between 100 and 500 words would be of use to other readers, then a
maximum) and full circuit diagram showing all relevant Pico Technology PC based oscilloscope
component values. Please draw all circuit schematics could be yours.
as clearly as possible. Every six months, Pico Technology will
Send your circuit ideas to: Alan Winstanley, be awarding an ADC200-50 digital storage
Ingenuity Unlimited, Wimborne Publishing Ltd., Allen oscilloscope for the best IU submission. In
House, East Borough, Wimborne, Dorset BH21 1PF. addition, two single channel ADC-40s will
They could earn you some real cash and a prize! be presented to the runners up.

AUDIO FREQUENCY DOUBLER — Pitch Effects

Being interested in
electronic effects for music,
I was quite intrigued by the
pitch doublers and chang-
ers found on some profess-
ional effects units. I quickly
realized that the frequency
changes were arrived at by
digital means and the
circuit diagram shown
in Fig.1 is one way this
can be achieved by the
hobbyist.
The method used is
basically that of a non-
linear mixer. Given two
sine waves of frequency f1
and f2, then the sum and
differences, i.e. f1 + f2 and f1 - f2, Fig.1. Circuit diagram for the Audio Frequency Doubler.
may be generated by arranging the
circuit to multiply the two sine waves input onto the non-inverting input second copy of the input
together. As f1 and f2 are actually (pin 3) of IC2 which, in conjunct- amplified by ICI, and applied to
the same, the result is f1 + f1 or 2f1; ion with the junction FET (field the gate (g) of TR1. The FET is
f1 - f1 is zero. effect transistor) TR1, forms a biased so as to mimic a
The multiplication is accom- variable gain amplifier. Its gain is reasonably linear resistance
plished by passing one copy of the controlled by the amplitude of a between its source and drain.
Copyright © 1998 Wimborne Publishing Ltd and EPE Online, November 1998 - www.epemag.com - 41
Maxfield & Montrose Interactive Inc
This resistance is then modulated
by the input sine wave.
The gain of IC2 equals (R5 +
PICO PRIZE WINNERS
Rds) / Rds where Rds is the FET It's time to judge the Ingenuity Unlimited submissions over the
drain-source resistance. The last six months. Three lucky entrants each win a fabulous prize of a
change in gain produces the PICO Technology (www.picotech.com) PC-based Oscilloscope!
multiplying action. EPE Editor Mike Kenward and IU host Alan Winstanley carefully
If Vout of IC2 = G × Vin where G
is the gain and G itself is a function considered all the published submissions, and prizes were finally
of Vin, then Vout = G(Vin) × Vin. awarded as follows:
Unfortunately, due to the FET WINNER − receives a superb PICO Technology ADC200-50 PC
and op-amp arrangement, G(Vin) Digital Storage Oscilloscope
mathematically resembles some-
thing like a + (b × Vin) where a and Electronic Dice − Steve Teal, Witney, Oxfordshire (July 1998).
b are constants. This gives us: Although far from a new application of electronics, in light of our
Teach-In 98 series the judges were pleased to see how the
Vout = (a + (b × Vin)) × Vin, and contributor had fulfilled the logic design requirement methodically,
Vout = a = Vin + b × Vin × Vin meeting the challenge of incorporating specific logic devices to hand.
This means we have an extra
term, a × Vin which is of course the RUNNERS-UP − each wins a PICO Technology ADC-40 Single-
original input signal multiplied by channel PC-based Oscilloscope
some constant. This must be
removed, and this is the purpose of L.E.D. Cycle Rear Lamp − Alan Bradley, Belfast, Northern
IC3, an adder circuit, or rather a Ireland (October 1998). We were impressed by this simple but
subtracter! The mixed output is effective design, which was well researched in relation to component
applied to the inverting input and choice and current UK legislation.
the original signal is applied to the
non-inverting input via potentio-
Audio Frequency Doubler − Alan Lippett, Stafford (November
meter VR2. By careful adjustment
1998). A systematically designed effects unit using a small number
of VR2 the original signal will be
of active components.
nulled out, leaving the doubled
frequency at the output of IC3.
In use, set Level control VR1
so as not to overdrive ICI. It is not
Our thanks to PICO for their on-going sponsorship
recommended exceeding 0⋅4V pk-
pk on the input. I originally used LOGIC GATE TESTER − When the
741s for the opamps, which gave
good results, but better spec types chips are down
such as LM318s improved the Anyone with lots of surplus TTL chips might find the circuit of
nulling. The circuit worked well up Fig.2 handy as a means of checking the function of a variety of TTL
to l0kHz. Note that a 9V dual split logic gates. This circuit is ideal for students and enthusiasts who
supply is required. make extensive use of AND, NAND, OR, NOR, XOR and XNOR
Alan Lippett, Stafford. gates (7408, 7400, 7432, 7402 and 7486 respectively).
ICI is a clock generator configured in the astable mode, and VR1
allows the user to set the input frequency of the network. IC2 cont-
INGENUITY UNLIMITED ains a dual J-K flip-flop that is designed to operate as a modulo-4
asynchronous counter. IC2 will generate the codes 00, 01, 10 and 11.
BE INTERACTIVE! These codes will be distributed to the IC to be tested in IC Sockets 1
IU is your forum where you and 2, and the NOR gates of IC3 and IC4 will decode and display the
can offer other readers the condition of the inputs via a simple LED display D5 to D8 (outputting
benefit of your ingenuity. Share the result similar to a Truth Table − A.R.W.).
those ideas and earn some cash
Thus, D1 to D4 display the gate output states and D5 to D8
and possibly a prize!
display the result of their truth tables. The “expected” outputs which

Copyright © 1998 Wimborne Publishing Ltd and EPE Online, November 1998 - www.epemag.com - 42
Maxfield & Montrose Interactive Inc
 +5V
are derived from Truth Tables
should be compared to the IC1
555
IC2
74LS76
IC3
74LS02
8 5 14
R1
actual outputs displayed by the 1k VCC VCC VCC
4 RST 2 4 2 I1
light-emitting diodes. An error 7 DIS 3
PR1
CLR1
J1
K1
16 3
I1 R5 220 Ohm D5 GRN
will register as a small leakage 7 PR2 J2 9 5 I2 OUT1 1
a k
00
6 THRES. OUT 3 8 12 6 I2 OUT2 4
current that will turn an LED VR1
2 TRIG CON 5 1
CLR2
CLK1
K2
Q1 11 8 I3 OUT3 10 R6 220 Ohm D6 GRN
slightly on. 500k
GND
1
6 CLK2 Q2
15 9
I3 OUT4
13
a k
01
Lin. 14 Q1 Q2 10 12 I4
GND
Since this circuit contains + 13
11 I4
GND R7 220 Ohm D7 GRN
two IC holders (the second one C1, 1u, 25V C2, 10n 7 10
0V a k
for 7402's only) it is important to R8 220 Ohm D8 GRN
know the pinouts of the IC that 11
a k
14
you would like to test. Two ICs 2 VCC IC4
I1
should not be inserted at the R1 Gate 4
220 Ohm D1 RED Output
3 I1 74LS02
5 1
same time. Also, the circuit IC
Socket 1 a k 6
I2 OUT1
OUT2 4
I2
cannot test ICs with open R2 Gate 3
220 Ohm D2 RED Output
8 I3 OUT3 10
9 13
collector outputs. a k 12
I3 OUT4
I4
Gate 2 11 I4
Mirza N. Beg, R3 D3 RED Output GND

Lenasia, South Africa. a k

Gate 1
7

IC R4 D4 RED Output
Socket 2
(7402 only) a k
COURTESY LIGHT
DELAY − Down to
Earth Fig.2. Circuit diagram for the Logic Gate Tester
The simple circuit diagram
shown in Fig.3 forms an elect-
ronically-controlled time delay
for a car's courtesy light (“dome
light”). The only connections to
the unit are an “earth” (negative
chassis), and a lead to the
courtesy light switch “live,”
on the driver's door switch,
which should be a ground-
switching type.
On closing the driver's door,
switch S1 will open and cap-
acitor C1 will charge through
transistors TR2 and TR3. These
are connected as a high-gain
Darlington pair. Diode D1
ensures that C1 is discharged
quickly when the door switch is
closed. (i.e. the door is open).
As the collector of TR3 Fig.3. Vehicle Courtesy Light Delay circuit diagram
rises, the lamp starts to dim.
When it reaches approx. 4⋅5V,
transistor TR1 will turn full on, The speed at which the lamp dims will depend on the value of C1
lowering the base volts of TR2, and the combined gains of TR2/TR3.
causing it and TR3 to turn off. Most medium gain, low power npn transistors can be used for
The collector of TR3 will rapidly TR1 and TR2, but TR3 will need to be capable of switching 1A. It
rise, causing the lamp to go out. should not require a heat sink. The whole unit can be constructed on
stripboard, enclosed in a small box, and fixed neatly under the
vehicle dashboard.

Copyright © 1998 Wimborne Publishing Ltd and EPE Online, November 1998 - www.epemag.com - 43
Maxfield & Montrose Interactive Inc