Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology

Xiongfei Meng, Karim Arabi†, and Resve Saleh

SoC Research Laboratory, Department of Electrical and Computer Engineering,
University of British Columbia, 2356 Main Mall, Vancouver, BC, V6T 1Z4, Canada
†PMC-Sierra, Inc. 100-2700 Production Way, Burnaby, BC, V5A 4X1, Canada
E-mail: xmeng@ece.ubc.ca, Karim_Arabi@pmc-sierra.com, res@ece.ubc.ca

Abstract A new cross coupled standard-cell design approach [5]

addresses the issue of ESD performance. The design
On-chip decoupling capacitors are generally used to provides certain ESD input protection to the decap, but
reduce power supply noise. Traditional decoupling does not offer any savings in gate leakage. This paper
capacitor designs using NMOS devices may no longer be suggests three modifications to the cross coupled cells
suitable for 90nm CMOS technology due to increased that trade off ESD, transient response and leakage.
concerns on thin-oxide gate leakage and electrostatic Different modifications improve different design aspects,
discharge (ESD) reliability. A cross coupled design for with certain drawbacks on others. The modifications are
standard cells has recently been proposed to address the made to be suitable for different technology nodes and
ESD issue. In this paper, three modifications of the cross processes, and the overall effect is to provide designers
coupled design are introduced and the tradeoffs among with decap design flexibility for 90nm and below.
ESD performance, transient response and gate leakage The rest of the paper is organized as follows. In
are analyzed. As shown here, the modifications offer Section 2, the necessary background on decap design,
designers greater flexibility in decoupling capacitor ESD problem, and gate leakage is briefly discussed. The
design for 90nm and below. cross coupled design is then analyzed and verified by
SPICE simulations in Section 3. Modifications are
proposed and compared with the standard and the cross
1. Introduction coupled designs in Section 4. Section 5 suggests future
directions and provides conclusions.
With increasing clock frequency and decreasing
supply voltage as technology scales, maintaining the 2. Background
quality of power supply becomes a critical issue [1].
Typically, decoupling capacitors (decaps) are used to A standard decap is usually implemented using an
keep the power supply within a certain percentage (e.g., NMOS transistor with the gate connected to VDD and both
10%) of the nominal supply voltage [2]. Decaps hold a source and drain connected to VSS (see Figure 1), or a
reservoir of charge and are placed close to the power pads PMOS device with opposite connections. The effective
and near any large drivers. When large drivers switch, the capacitance at low frequencies can be written as:
decaps provide instantaneous current to the drivers to Ceff = COX WL + COLW (1)
reduce IR drop and Ldi/dt effects [3], and hence keep the where COX is the oxide capacitance per unit area, COL is
supply voltage relatively constant. A standard decap is the overlap and fringing capacitance per unit width, and
usually made from NMOS transistors in a CMOS process
W and L are the width and length of the transistor,
[3].
respectively [3].
At the 90nm technology node, the oxide thickness of a
A standard decap also exhibits parasitic resistance of
transistor is reduced to roughly 2.0nm. The thin oxide the channel that imposes certain delay on the transient
causes two new problems: possible electrostatic discharge response of the decap [6]. The decap’s effective resistance
(ESD) induced oxide breakdown and gate tunneling at low frequencies is given by:
leakage [2][4]. Potential ESD oxide breakdown increases
L
the likelihood that an integrated circuit (IC) will be Reff = (2)
permanently damaged during an ESD event, and hence 6μ COX W (VGS − VT )
raises a reliability concern. Higher gate tunneling leakage where μ is the mobility, VGS (or VGD since source and
increases the total static power consumption of the chip. drain are tied) is the voltage across the oxide, and VT is
As technology scales further down, with a thinner oxide, the threshold voltage. From (2), Reff is proportional to the
the result is an even higher ESD risk and more gate channel length L. That is, for faster transient response, a
leakage. The standard decap design experiences these two decap design should maintain L in a reasonably small
problems and therefore becomes rather inappropriate for range to keep Reff small. To capture the transient
90nm and below. behavior, a decap can be modeled as a lumped RC circuit,
as shown in Figure 1. Both Reff and Ceff can be considered

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 constant at low or moderate operating frequencies, but
they are degraded at high frequencies [6]. A new design issue for decaps due to oxide thickness
reduction is the gate tunneling current. The current is in
the form of tunneling electrons or holes from substrate to
gate or from gate to substrate through the gate oxide,
depending on the voltage biasing conditions [7]. Two
forms of gate tunneling exist: Fowler–Nordheim (FN)
tunneling and direct tunneling. For normal operations on
short-channel devices, FN tunneling is negligible, and
Figure 1. Decap modelling as a series RC circuit direct tunneling is dominant [7]. In the case of direct
tunneling, the gate leakage current in PMOS is much less
Decaps can be used in the open areas of the chip than in NMOS, and it has been shown experimentally that
between blocks (called “white-space” decaps) or inside PMOS gate leakage is roughly 3 times smaller than
the blocks composed of standard cells. If placed inside NMOS gate leakage for same size transistors [8][9]. The
standard-cell arrays, it is more convenient to make decaps gate leakage simulations can be carried out by using
using both types of NMOS and PMOS to form a decap BSIM4 SPICE models [10]. Assuming a 90nm
cell, knowing that the n-well is already implemented technology with 2.0nm oxide thickness and 1.0V power
(Figure 2(a)) [6]. The overall impedance of two parallel supply, the gate leakage current is shown in Figure 3.
RC circuits is determined as
1 1
( Reff _ n + ) //( Reff _ p + ) , and simplified as
sCeff _ n sCeff _ p
Reff _ n Reff _ p 1
+ + higher _ order _ terms
Reff _ n + Reff _ p s(Ceff _ n + Ceff _ p )
For first-order hand calculations, the higher-order terms
are negligible. Thus, the overall effective capacitance is
the sum of the two individual decoupling capacitances,
and the overall effective resistance is the parallel
combination of the two individual effective resistances. Figure 3. Gate leakage current vs. gate area
That is:
Ceff _ overall ≈ Ceff _ n // Ceff _ p = Ceff _ n + Ceff _ p (3) The gate leakage current density J and the oxide
thickness tOX have an empirical relationship as follows if
Reff _ n Reff _ p
Reff _ overall ≈ Reff _ n // Reff _ p = (4) assuming the voltage across the oxide VOX is fixed [8]:
Reff _ n + Reff _ p J = 10( A− B⋅tOX ) (5)
Figure 2(b) illustrates a sample layout of this N+P where A and B are experimental constants and are process
configuration that uses two fingers to cut the overall Reff dependent. Equation (5) implies that the gate leakage
in half so that its transient response is maintained. current is exponentially related to the oxide thickness. A
typical J and tOX relationship for a fixed VOX is illustrated
in Figure 4.

Figure 2(a). Standard N+P decap configuration

Figure 4. Gate leakage current density vs. oxide

thickness

Figure 2(b). A sample layout of standard N+P decap It is evident that from 90nm technology, the gate
with two fingers leakage from decaps is already significant [9]. The gate
leakage contributes to the total static power consumption,
2.1 Thin-oxide Gate Tunneling Leakage and decaps usually occupy a large on-chip area. The use

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 of PMOS devices exclusively is not a viable solution for inserted within standard cells where ESD damage is a
high-frequency circuits since they have a poor frequency concern.
response relative to the NMOS devices [6].

2.2 ESD Reliability in Decap Design

Another new consideration has arisen in the form of
ESD protection due to the thin oxide in 90nm technology.
ESD is the process of static discharge that can typically
arise from human contact with any IC pin. Approximately
0.6uC of charge is carried on a body capacitance of Figure 5. Complete ESD protection scheme
100pF, generating a potential of 2KV or higher to
discharge from the contacted IC pin to ground for a Previous decap designs (before 90nm technology) did
duration of more than 100ns [4]. Under such an event, the not consider ESD performance mainly because: 1. The
peak discharge current is in the ampere range, leading to transistor’s oxide thickness is thick and the oxide
permanent damage on certain transistors in the chip if not breakdown voltage is high enough so that the transistor is
properly protected. The damage can be in one of the two likely to survive during an ESD event with adequate
forms or the combination of the two: one is thermal protection circuits. 2. Insertion of the large resistance Rin
burnout in devices or interconnects, while the other is dramatically reduces the transient response of the decap.
oxide breakdown of devices due to the high voltage However, starting from 90nm, the oxide thickness is so
across the oxide [4]. When running simulations for an thin that the designer cannot ignore the increased ESD
ESD event, the maximum current density Jmax of devices risk. A large resistance is therefore recommended to be
and interconnects is measured to check for potential placed inside the decap cells to protect from potential
thermal damage. The oxide voltage also needs to be ESD damage. As a consequence, this tradeoff between
measured to compare with the oxide breakdown voltage ESD performance and transient response becomes the
of a device for a given fabrication process. The oxide main decap design challenge in 90nm.
breakdown voltage is almost linearly proportional to the
oxide thickness [4]. For instance, assuming that a 90nm
process uses 2.0nm of oxide thickness, the corresponding 3. Cross Coupled Decap Design
oxide breakdown voltage is below 5V. If the thickness is
doubled, the oxide breakdown voltage is also doubled [4]. Knowing that the standard N+P decap design may no
An ESD event can be delivered between any two pins longer be suitable for 90nm technology due to the
of an IC. To properly protect an IC from ESD damage, an increased ESD risk, a new cross coupled decap design has
ESD circuit must shunt ESD current between these two been proposed in [5] to address the issue of ESD
pins [4]. In the case of decaps within standard cells, the reliability. The new cross coupled design (Figure 6)
only two pins that the decaps have access to are the two reconnects the terminals of the two transistors: the drain
local power rails, namely VDD and VSS. Primary and local of the PMOS connects to the gate of the NMOS, whereas
(sometimes called “secondary”) protection elements are the drain of the NMOS is tied to the gate of the PMOS
needed to protect the two rails by limiting the voltage [5].
difference between the two rails to a value below the
oxide breakdown voltage. The primary element will shunt
most of the ESD current, whereas the local element serves
to limit the voltage or current at the local circuit until the
primary element is fully operational [4]. A primary
element can be a thick oxide transistor, a silicon
controlled rectifier, an open-gate, grounded-gate or
coupled-gate NMOS transistor, or a large ESD diode [4].
A local protection element can be simply a diode formed
by a grounded-gate NMOS transistor [4].
The complete ESD protection scheme is illustrated in Figure 6. Cross coupled decap schematic [5]
Figure 5. In addition to the primary and local elements, a
resistor Rin is required to limit the maximum current flow The design can be modeled as a series connection of
to the decap and to limit the voltage seen from the gate of Reff and Ceff at low frequencies, similar to the standard
the decap. For better ESD protection, this resistance is decap. The overall Ceff is roughly the same, while the
normally large and can be in the forms of polysilicon, overall Reff increases significantly. Both transistors are
diffusion, n-well, or even channel resistance [4]. The still in the linear region, but the channel resistance is
resistance is generally not implemented together with modified. Specifically,
primary and local protection devices. It is likely to be Ceff _ overall ≈ Ceff _ n // Ceff _ p = Ceff _ n + Ceff _ p (6)

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 Reff _ overall ≈ ( Reff _ p + Ron _ n ) //( Reff _ n + Ron _ p )
Ron _ n Ron _ p
≈ Ron _ n // Ron _ p = (7)
Ron _ n + Ron _ p
where Ceff_n, Ceff_p, Reff_n and Reff_p are the intrinsic
effective capacitances and resistances, respectively, and
Ron_p and Ron_n are the channel resistance of the two
transistors. Since Ron_p and Ron_n are at least one order of
magnitude larger, Reff_p and Reff_n can be rounded off from Figure 7. Simulation setup for ESD analysis [4]
the overall Reff calculation. Ceff_n, Ceff_p, Reff_n and Reff_p
can be obtained from (1) and (2). Both Ron_p and Ron_n can Since the primary elements are designed to handle
be computed as follows [3]: large current flow, the maximum current density Jmax is
L assumed to be within the safe range and is not measured
Ron ≈ Req (8) again for simplicity. HBM generation raises the voltage
W level at node VDD, and hence turns on the primary
where Req is the process-dependent square resistance elements to discharge. For device protection from oxide
(kȍ). It is important to realize that (6) - (8) are first-order, breakdown, the voltage differences across gate and source
low-frequency approximations only. The real transistor (VGS) and across gate and drain (VGD) of the two
channel resistance by nature is nonlinear and depends transistors are simulated. The VGS and VGD voltages are
strongly on applied voltages, operating frequency, and desired to be kept as low as possible, knowing that the
geometry [3]. The only reason for providing these oxide breakdown voltage for a typical 90nm process is
formulae is to give designers useful information when below 5V. From simulation measurements, for the
making design tradeoffs. standard decap design, VGD_p = VGS_p = VGD_n = VGS_n =
This cross coupled design improves the ESD 4.2V. For the cross coupled design, VGD_p = 4.0V, VGS_n =
performance of the decap by making the overall effective 3.2V, and VGS_p = VGD_n = 3.0V. Clearly, the cross
resistance larger without adding additional area. The coupled design provides better ESD performance.
tradeoff of the design is a reduced transient response. The For transient response, to demonstrate how the decaps
larger Reff corresponds to a longer RC delay. Assuming perform, a normal operating condition is set: the VDD
that the cell area is fixed and that only the terminal node is connected to the nominal supply of 1V (for
connections are swapped, this design provides no savings 90nm), and VSS is tied to a common ground. When there
in gate leakage as compared to the standard decap. is no activity the current flow from VDD to VSS is solely
To quantitatively measure ESD performance, RC treated as gate leakage. At 1ns, VDD starts to drop linearly
delay in transient response, and gate leakage, a number of from 1V to 0.9V, reaches 0.9V at 2ns, and then remains
simulations were carried out. The layouts were created in constant. By definition, an ideal capacitor responds to a
Virtuoso™ Layout Editor, verified by Calibre™ DRC voltage change as a current source if it is fully charged, as
checker, and then extracted by Calibre™ XRC parasitic follows:
extraction tool. The extracted data were simulated with
dV ΔV
HSPICE™ for different simulation setups. For fairness, I = Cideal ≈ Cideal (9)
the same cell area was used for all the designs. dt Δt
The ESD simulation requires an ESD generation If the voltage change is a ramp, the current provided by
model. Among all the existing models, the human body the ideal capacitor should be a pulse. In practice, due to
model (HBM) was adopted for simplicity. Following the the presence of the effective resistance associated with the
standard MIL-STD-883x method 3015.7, a human body decap designs, a certain amount of RC delay exists. Good
can be simulated as a series of 1.5Kȍ resistance RHBM and transient response should have sharp rise and fall edges
100pF capacitance CHBM. The capacitor CHBM is initially (at 1ns and 2ns in this case), while it can also provide a
charged to 2KV that needs to be discharged through some large average current Iavg during the time period from 1ns
primary elements [4]. The primary element is arbitrarily to 2ns. The sharpness of rise and fall is measured from the
chosen to be an ESD diode plus a gate-coupled NMOS rise/fall slopes with a unit of A/s. The average capacitance
device (GCNMOS) with an n-well resistor Rnwell (~15Kȍ) Cavg is calculated from Iavg from (9). Figure 8 illustrates
and an NMOS bootstrap capacitor Cb [4]. Two identical the curves for the two designs in transient analysis, and
primary elements are used to protect the circuit placed in indicates that the standard decap can provide much better
between the HBM generation and the elements, as shown transient response. The two designs also have almost
in Figure 7 [4]. For simplicity, no secondary element is identical gate leakage: 53.8nA for the standard decap and
used. 53.7nA for the cross coupled design.

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 6.0000

Standard Decap
5.0000

4.0000
Current (uA)

3.0000

2.0000

Cross Coupled Decap

1.0000

0.0000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

-1.0000

Time (ns)
Figure 9. A sample layout of Mod 1 (Basic circuit
without fingering)
Figure 8. Simulation results for RC delay

4. Modified Cross Coupled Decap Designs

Three modifications are made to address different
goals of decap design: ESD performance, transient
response, and gate leakage. It is difficult to
simultaneously make improvements on all the three goals,
but trying to balance them and to make tradeoffs is Figure 10. A sample layout of Mod 2 (Replace
certainly feasible and indeed achievable. Each NMOS with PMOS)
modification is compared to the basic cross coupled
design to show advantages and disadvantages. Again, the
total cell area is fixed for all the designs.
The first modification (Mod1) attempts to improve
ESD performance by making the channel lengths of the
two resistors longer (Figure 9). The two fingers are
combined into one. As a result, the overall Reff is almost
doubled, while the overall Ceff remains roughly the same.
The disadvantage of this design is reduced transient
Figure 11. A sample layout of Mod 3 (Replace
response and slightly larger gate leakage since the gate
NMOS with PMOS, and use smallest NMOS)
area increases a little.
The second modification (Mod2) attempts to reduce
Following the same simulation procedures outlined
gate leakage while maintaining ESD performance and
earlier, Table I lists the comparison for all the designs on
transient response at the same level (Figure 10). One
ESD performance, transient response, and gate leakage.
NMOS is replaced by a PMOS with the n-well expanded
The bold numbers indicate the best results in the
to accommodate the new PMOS. The effect of this change
comparison. One can see clearly the improvements and
is then increased Ron_p and Ceff_p. To match ESD
the tradeoffs from the simulation results.
performance, Ron_n needs to be reduced. One simple
change to obtain a small Ron_n is to reduce the channel
Table I. Comparison on ESD performance, transient
length of the NMOS. By the same token, Ceff_n is also
reduced. The result is comparable ESD performance and response and gate leakage
transient response if carefully designed. Knowing that the ESD performance with Transient
new same-area PMOS leaks 3 times less than the replaced 2 primary elements response Gate
NMOS, extra saving in gate leakage is realized. leak
The third modification (Mod3) (Figure 11) follows the VGS_p
Rise Avg age
similar approach as of Mod2. It further increases the new VGD_p VGS_n = (nA)
slope cap
PMOS area and further reduces the NMOS channel (V) (V) VGD_n
(A/s) (fF)
length. Indeed, the minimum length NMOS is used to (V)
have the smallest possible Ron_n so that it dominates and Decap 4.2 4.2 4.2 2.8e5 54.3 53.8
makes the overall Reff smaller. Since the overall Reff is Cross
4.0 3.2 3.0 8.2e4 33.1 53.7
greatly decreased while the overall Ceff is somewhat Coupled
increased, the transient response dramatically improves. Mod1 3.8 2.9 2.8 8.7e4 21.4 59.7
An even larger PMOS and smaller NMOS lead to Mod2 4.0 3.7 3.4 7.0e4 35.8 33.6
additional savings in gate leakage as well. The only Mod3 4.1 3.9 3.8 1.1e5 47.5 31.8
downside is reduced ESD protection capability due to the
reduced overall Reff. There is no single design that suits all the possible
situations. The reason for having several possible designs
is to provide designers with different solutions so that

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 they can make a suitable choice for a specific process at a of gate leakage, and will eventually limit the use of the
specific technology node. For 90nm technology, the cross coupled design and its modifications. The
standard decap still seems to be acceptable in ESD anticipation at this stage would be the use of high-k
reliability, assuming the power rails have protection dielectrics as the oxide material so that the electrical
elements. However, Mod3 is more suitable because it has thickness and the physical thickness can be differentiated
better ESD performance and saves roughly 41% on gate to completely eliminate the concerns on ESD reliability
leakage. The only tradeoff then is a slightly reduced and gate leakage. Another approach would be to utilize
transient response. As technology further scales, or as a high-voltage thick-oxide transistors as decaps, as
different process increases the transistor speed, the oxide discussed earlier. In any case, solutions that properly
thickness will probably become thinner and the oxide balance ESD, gate leakage, transient response and area
breakdown voltage will occur. Under that scenario, the will be required.
standard design or the Mod3 will no longer be appropriate
any more. For improved ESD performance, Mod2 will be 6. Acknowledgments
suggested instead of the basic cross coupled design. The
reason is that Mod2 has similar ESD numbers and similar
transient response compared to the basic cross coupled The authors would like to thank NSERC and PMC-
design but saves approximately 40% on gate leakage. Sierra for providing support to this work.
When technology scales down to a point that the oxide
thickness makes the ESD reliability a more serious 7. References
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As technology further scales to 65nm or below, the
ultra thin oxide will increase the ESD risk and the amount

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