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Department of ECE
IV B.Tech I Semester
VLSI DESIGN
 1
UNIT-III
DAY-21
Syllabus:
Basic Circuit Concepts: Sheet Resistance, Sheet Resistance concept applied to
MOS transistors and Inverters, Area Capacitance of Layers, Standard unit of
capacitance, The Delay Unit, Inverter Delays, Propagation Delays, Wiring
Capacitances, Fan-in and fan-out characteristics, Choice of layers, Transistor
switches, Realization of gates using NMOS, PMOS and CMOS technologies.
Scaling Of MOS Circuits: Scaling models, Scaling factors for device parameters,
Limits due to sub threshold currents, current density limits on logic levels and
supply voltage due to noise.
Topics to be covered: Circuit Concepts, Sheet resistance
1. What is sheet resistance? find out the expression for the resistance of
rectangular sheet in terms of sheet resistance.
The sheet resistance is defined as the resistance per unit area of a sheet of
material.
Consider a rectangular sheet of material with

Resistivity= ρ,
Width = W,
Thickness = t
and Length = L
Then the resistance between the two
ends is
ρL ρL ρ
R AB= = ohm For L=W R s= =R ohm
t .W A t
Where Rs is defined as the sheet
resistance
2. What are the standard sheet resistance values?

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In the above mentioned table values are for 5um Technology.

3. Find the Sheet resistance of MOS transistor

Figure nmos depletion inverter

Pull up to pull down ratio = 4.In this case when the nmos is on, both the devices
are simultaneous, Hence there is an on resistance Ron = 40+10 =50k. It is this
resistance that leads the static power consumption which is the disadvantage of
nmos depletion mode devices
4. Calculate the Complementary Metal Oxide Semiconductor Inverter sheet
resistance.

5. Problem: A particular layer of MOS circuit has a resistivity _ of 1 ohm –cm.

The section is 55um long,5um wide and 1 um thick. Calculate the resistance
and also find Rs
Sol: R= RsxL/W, Rs= _/t
Rs=1x0.01/1U=0.01x1KX1K=10Kohm
R= 10Kx55xU/5U=110k
Home Work
1. What happens when width of transistor increases with respect to resistance
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and capacitance.
2. How the name has got for MOSFET.
3. Whether the length and width of transistor is technology specific or not.

Important and previous JNTU exam questions:

1) What is sheet resistance? Derive the Expression for RS?(May-2015-Set2-
7M).
2) Calculate the ON resistance from VDD to GND for the nMOS and CMOS
Inverter?( May-2015-Set2-8M).
3) Explain the concepts of sheet resistance?( Dec-2015-Set1-7M(Supply)).

Day 22
Topics to be covered: MOS Capacitor, Delay
1. Find out the Capacitance for any layer
The capacitance of a parallel plate capacitor is given by

Where A is the Area of the plates

D is the thickness of the insulator between the plates.
2. How Capacitance estimation in MOS Layers?
CAPACITANCE ESTIMATION
Parasitic capacitances are associated with the MOS device due to different layers
that go into its formation. Interconnection capacitance can also be formed by
the metal, diffusion and polysilicon (these are often called as runners) in
addition with the transistor and conductor resistance. All these capacitances
actually define the switching speed of the MOS device.
Understanding the source of parasitic and their variation becomes a very
essential part of the design specially when system performance is measured in
terms of the speed. The various capacitances that are associated with the CMOS
device are
1) Gate capacitance - due to other outputs connected to input of the device
2) Diffusion capacitance - Drain regions connected to the output
3) Routing capacitance- due to connections between output and other inputs
Since the silicon dioxide is the insulator knowing its thickness we can calculate
the capacitance

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C= εoεinsA/D farads
εo = 8.85 x 10-14 F/cm (permittivity of free space)
εins= relative permittivity of sio2=4.0
D= thickness of the dioxide in cm
A = area of the plate in cm2
The gate to channel capacitance formed due to the sio2 separation is the most
profound of the mentioned three types. It is directly connected to the input and
the output. The other capacitance like the metal, poly can be evaluated against
the substrate. The gate capacitance is therefore standardized so as to enable to
move from one technology to the other conveniently.
The standard unit is denoted by Cg. It represents the capacitance between gate
to channel with W=L=min feature size. Here is a figure showing the different
capacitances that add up to give the total gate capacitance
Cgd, Cgs = gate to channel capacitance lumped at the source and drain
Csb, Cdb = source and drain diffusion capacitance to substrate
Cgb = gate to bulk capacitance
Total gate capacitance Cg = Cgd+Cgs+Cgb
Since the standard gate capacitance has been defined, the other capacitances
like polysilicon, metal, diffusion can be expressed in terms of the same standard
units so that the total capacitance can be obtained by simply adding all the
values.
3. What is Delay?
DELAY The concept of sheet resistance and standard unit capacitance can be
used to calculate the delay. If we consider that a one feature size poly is charged
by one feature size diffusion then the delay is Time constant 1T= Rs (n/p
channel)x 1Cg secs. This can be evaluated for any technology. The value of Cg
will vary with different technologies because of the variation in minimum
feature size.
5u using n diffusion=104X0.01=0.1ns safe delay 0.03nsec
2um = 104x0.0032=0.064 nsecs safe delay 0.02nsec
1.2u= 104x0.0023 = 0.046nsecs safe delay =0.1nsec
4. Find out the expression for delay time of a CMOS inverter
The delay time td is given by the expression

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Where C is the load capacitance

Vdd is the supply voltage
Vt is the threshold voltages of the MOS transistors.
Home Work
1.what are the parasitics.
2.what is threshold voltage.
3.Give the equation for power consumption in CMOS.
Important and previous JNTU exam questions:
1. Explain the model for deviation of time delay.?(May-2015-Set4-7M).
2. Define and explain standard units of capacitance.?(Dec-2015-Set1-
8M(Supply)).

DAY-23
Topics to be covered: Inverter delay
1. Calculate Inverter Delay
INVERTER DELAYS
We have seen that the inverter is associated with pull up and pull down
resistance values. Specially in nmos inverters. Hence the delay associated with
the inverter will depend on whether it is being turned off or on. If we consider
two inverters cascaded then the total delay will remain constant irrespective of
the transitions.
NMOS Inverter delay

Let us consider the input to be high and hence the first inverter will pull it down.
The pull down inverter is of minimum size nmos. Hence the delay is 1T. Second
inverter will pull it up and it is 4 times larger, hence its delay is 4T.
The total delay is 1T +4T= 5T.
Hence for nmos the delay can be generalized as T=(1+Zpu/Zpd) T
CMOS INVERTER

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Let us consider the input to be high and hence the first inverter will pull it down.
The nmos transistor has Rs = 10k and the capacitance is 2Cg. Hence the delay is
2T. Now the second inverter will pull it up, job done by the pmos. Pmos has
sheet resistance of 25k i.e 2.5 times more, everything else remains same and
hence delay is 5T.
Total delay is 2T +5T = 7T.
The capacitance here is double because the input is connected to the common
poly, putting both the gate capacitance in parallel. The only factor to be
considered is the resistance of the p gate which is increasing the delay. If you
want to reduce delay, we must reduce resistance. If we increase the width of p
channel, resistance can be reduced but it increases the capacitance. Hence some
trade off must be made to get the appropriate values.
2. What are the various ways to reduce the delay time of a CMOS Inverter
Various ways for reducing the delay time are given below:
1. The width of the MOS transistors can be increased to reduce the delay. This is
known as gate sizing.
2. The load capacitance can be reduced to reduce delay. This is achieved by
using transistors of smaller dimensions as provided by future generation
technologies of the MOS transistors.
3. Delay can also be reduced by increasing the supply voltage Vdd and /or
reducing the threshold voltage Vt
3. What is Fan-in and Fan-out? Explain
Fan In: The Fan-in defined as the maximum number of inputs that a logic gate
can accept. If number of input exceeds, the output will be undefined or
incorrect. It is specified by manufacturer and is provided in the data sheet.
Fan-in = number of inputs to a gate
Examples:
1.Nand g1 (outg1, in1, in2, in3, in4); fan-in = 4
2.Nor g2 (outg2, in1, in2); fan-in = 2
Fan Out: The Fan-out is defined as the maximum number of inputs (load) that
can be connected to the output of a gate without degrading the normal
operation. Fan Out is calculated from the amount of current available in the
Raghu Engineering College Dept. of ECE VLSI DESIGN Unit-III
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output of a gate and the amount of current needed in each input of the
connecting gate. It is specified by manufacturer and is provided in the data
sheet. Exceeding the specified maximum load may cause a malfunction because
the circuit will not be able supply the demanded power.
Fan-out = number of inputs that a gate's output drives
Examples:
1. Nand g1 (outg1, a, b, c, d);
2. Nor g2 (outg2, a, e);
3. Not g3 (a, f); fan- out = 2
4. Explain Rise time and Fall time estimation in CMOS Inverter
The inverter either charges or discharges the load capacitance CL. We could also
estimate the delay by estimating the rise time and fall time theoritically.
Rise time estimation
Assuming that the p device is in saturation we have the current given by the
equation Idsp=ßp(Vgs-|Vtp|)2/2

The above current charges the capacitance and it has a constant value therefore
the model can be written as shown in figure above. The output is the drop
across the capacitance, given by
Vout =Idsp x t/CL
Substituting for Idsp we have Vout=ßp(Vgs-|Vtp|)2t/2CL.
Therefore the equation for t=2CLVout/ßp(Vgs-|Vtp|).Let t=Tr and Vout=Vdd,
therefore we have Tr = 2VddCL/ßp(Vgs-|Vtp|)2.
If consider Vtp=0.2Vdd and Vgs=Vdd we have Tr =3CL/ßpVdd
On similar basis the fall time can be also be written as Tf = 3CL/ßnVdd whose
model can be written as shown next

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5. Explain Propagation Delay
 Raising-up and Fall-down times (tr,tf) are defined using ratios of signal
amplitude (0.1 and 0.9)
 Propagation times (delay) (tpHL tpLH) are defined for the input/output
signal amplitudes
 Average propagation time: tpd=(tpHL+tpLH)/2

Home Work
1.If there are 4 number of NMOS inverters in cascade what is the worst case
delay.
2.If there are 4 number of CMOS inverters in cascade what is the worst case
Delay.
3.Whether Fan-in and Fan-out should be limited.
4.Differentiate between Transition Time Delay and Propagation Time Delay.

Important and previous JNTU exam questions:

1. What do you mean by inverter delay?(Nov-2016-Set1-7M(Supply)).
2. What is inverter delay? How delay is calculated for multiple stages.(May-
2015-Set1-7M).

DAY-24
Topics to be covered:
 Sources of Capacitor
 Choice of Layers
 Realization of gates
1. What are the Other sources of Capacitance Explain Wiring capacitance
1. Fringing field 2. Interlayer capacitance 3. Peripheral capacitance

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The capacitances together add upto as much capacitance as coming from the
gate to source and hence the design must consider points to reduce them. The
major of the wiring capacitance is coming from fringing field effects. Fringing
capacitances is due to parallel fine metal lines running across the chip for power
connection. The capacitance depends on the length l, thickness t and the
distance d between the wire and the substrate. The accurate prediction is
required for performance estimation.
Hence Cw=Carea+Cff.
Interlayer capacitance is seen when different layers cross each and hence it is
neglected for simple calculations. Such capacitance can be easily estimated for
regular structures and helps in modeling the circuit better.
Peripheral capacitance is seen at the junction of two devices. The source and
the drain n regions form junctions with the pwell (substrate) and p diffusion
form with adjacent nwells leading to these side wall (peripheral) capacitance
The capacitances are profound when the devices are shrunk in sizes and hence,
must be considered.
Now the total diffusion capacitance is Ctotal = Carea + Cperi
sss2. Explain Choice of Layers
CHOICE OF LAYERS
1.Vdd and Vss lines must be distributed on metal lines except for some
exceptions

2.Long lengths of poly must be avoided because they have large Rs,it is not
suitable for routing Vdd or Vss lines.
3.Since the resistance effects of the transistors are much larger, hence the
wiring effects due to voltage dividers and are not that profound Capacitance
must be accurately calculated for fast signal lines usually those using high Rs
material. Diffusion areas must be carefully handled because they have larger
capacitance to substrate.
With all the above inputs it is better to model wires as small capacitors which
will give electrical guidelines for communication circuits.
3. For a complex/compound CMOS logic gate, how do you realize the pull-up
and the pull-down networks
A CMOS logic gate consists of a nMOS pull-down network and a pMOS pull-up
network. The nMOS network is connected between the output and the ground,
whereas the pull-up network is connected between the output and the power
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supply. The nMOS network corresponds to the complement of the function
either in sum-of-product or product-of-sum forms and the pMOS network is dual
of the nMOS network .
4. Give two possible topologies AND-OR-INVERT (AOI) and OR-AND-INVERT
(OAI) to realize CMOS logic gate. Explain with an example.
The AND-OR-INVERT network corresponds to the realization of the nMOS
network in sum-of-product form. Where as the OR-AND-INVERT network
corresponds to the realization of the nMOS network in product-of-sum form. In
both the cases, the pMOS network is dual of the nMOS network .
5. Give the AOI and OAI realizations for the sum and carry functions of a full
adder.
AOI form of realization is

6. How do you realize pseudo nMOS logic circuits. Compare its advantage and
disadvantages with respect to standard static CMOS circuits.
In the pseudo-nMOS realization, the pMOS network of the static CMOS
realization is replaced by a single pMOS transistor with its gate connected to
GND. An n-input pseudo nMOS requires n+1 transistors compared to 2n
transistors of the corresponding static CMOS gates. This leads to substantial
reduction in area and delay in pseudo nMOS realization. As the pMOS transistor
is always ON, it leads to static power dissipation when the output is LOW.
Home Work
1.What are power rails.
2.Whether number of metal layers is Technology specific.
3.To have efficient routing number of metal layers should be more or less.
4.If 2 metal wires of same layer cross each other will they form open or short.
5.What is the difference between Designing and implementing technology.
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6.Why pull-up network has only PMOS and pull-down has only NMOS Devices.
7.What do you mean by logic level degradation.
8. Whether in AOI and OAI Design takes less number of Transistors or in SOP
and POS.
Important and previous JNTU exam questions:
1) Draw the structure of a dynamic CMOS gate and explain.(May-2015-Set4)

DAY-25
Topics to be covered: AOI and OAI Concepts
1. Compare the area, in terms of number of transistors, for the three different
implementations of a full adder using (i) static CMOS, (ii) domino CMOS, and
(iii) complementary pass transistor logic (CPL).
The full adder block diagram is given below:

The full adder realization using static CMOS is given below

It requires 28 transistors

The realization using Dynamic CMOS requires 20 transistors

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The pass transistor realization of the full adder is given below. It requires 16 (8 +
8) transistors.

2. What are the key characteristics of MOS dynamic circuits?

The advantage of low power of static CMOS circuits and smaller chip area of
nMOS circuits are combined in dynamic circuits leading to circuits of smaller
area and lower power dissipation. Smaller area due to lesser number of
transistors (n+2) compared to static CMOS realization requiring 2n transistors to
realize a n-variable function. Dynamic CMOS circuits have Lower static power
dissipation because of smaller capacitance. There is no short circuit power
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dissipation and no glitching power dissipation. Dynamic CMOS circuits are also
faster because the capacitance is about half that of the static CMOS circuits.
3. What makes dynamic CMOS circuits faster than static CMOS circuits?
As MOS dynamic circuits require lesser number of transistors and lesser
capacitance is to be driven by it. This makes MOS dynamic circuits faster.
4. Compare the sources of power dissipation between static CMOS and
dynamic CMOS circuits?
In both the cases there is switching power and leakage power dissipations.
However, the short circuit and glitching power dissipations, which are present in
static CMOS circuits, are not present in dynamic CMOS circuits.
Home Work
1.Do you have power rails in PTL.
2.Will you be having both PULL-UP and PULL-DOWN networks in Dynamic
CMOS.
3.What do you mean by glitch.
Important and previous JNTU exam questions:
1) Explain the basic operation of CMOS logic gate.(Dec-2015-Set1Supply)

DAY-26
Topics to be covered: Scaling, Technology scaling
1. What is Scaling?
Proportional adjustment of the dimensions of an electronic device while
maintaining the electrical properties of the device, results in a device either
larger or smaller than the un-scaled device this process is called scaling.
2. Why Scaling?...
Scale the devices and wires down, Make the chips ‘faster’ – functionality,
intelligence, memory – and – faster, Make more chips per wafer – increased
yield, Make the end user Happy by giving more for less and therefore, make
MORE MONEY!!
3. Scaling impact
Impact of scaling is characterized in terms of several indicators:
o Minimum feature size
o Number of gates on one chip
o Power dissipation
o Maximum operational frequency
o Production cost
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Many of the above can be improved by shrinking the dimensions of transistors
and interconnections. Shrinking the separation between features on transistors
and wires adjusting doping levels and supply voltages.
Technology Scaling
Goals of scaling the dimensions by 30%
Reduce gate delay by 30% (increase operating frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power savings @ 43% increase in
frequency)
Die size used to increase by 14% per generation
Technology generation spans 2-3 years
Figure 1 to Figure 5 illustrates the technology scaling in terms of minimum
feature size, transistor count, propagation delay, power dissipation and density
and technology generations.

Fig 1.Technology scaling (1)

Fig 2. Technology Scaling (2)

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Fig 3. Technology scaling (3)

Fig 4. Technology Scaling(4)

Fig 5. Technology Generation

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Home Work
1. Whether Technology scaling corresponds to Length or width of a
transistor.
2. Whether Technology is scaling up or down from time to time.
Important and previous JNTU exam questions:

1. Discuss the limits of scaling. Why scaling is necessary for VLSI circuits?
(May-2015-Set3(15M)).
2. Write the scaling factors for different types of device parameters.
(Dec-2015-Set1(8M)).
DAY-27
Topics to be covered: Scaling Models, Scaling factors
1. Scaling Models
 Full Scaling (Constant Electrical Field)
Ideal model – dimensions and voltage scale together by the same scale factor
 Fixed Voltage Scaling
Most common model until recently – only the dimensions scale, voltages remain
constant
 General Scaling
Most realistic for today’s situation – voltages and dimensions scale with
different factors
2. Scaling Factors for Device Parameters
Device scaling modeled in terms of generic scaling factors: 1/α and 1/β
1/β: caling factor for supply voltage VDD and gate oxide thickness D
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1/α: linear dimensions both horizontal and vertical dimensions
3. Why is the scaling factor for gate oxide thickness different from other linear
horizontal and vertical dimensions?
Conider the cross section of the device as in Figure 6,various parameters derived
are as follows.

Fig. Technology generation

4. Limits due to sub threshold currents
 Major concern in scaling devices.
 I sub is directly proportional exp (Vgs – Vt ) q/KT
 As voltages are scaled down, ratio of Vgs-Vt to KT will reduce-so that
threshold
current increases.
 Therefore scaling Vgs and Vt together with Vdd .
 Maximum electric field across a depletion region is Emax = 2{Va+Vb}/d
5. Limits on supply voltage due to noise
 Decreased inter-feature spacing
 Greater switching speed –result in noise problems
6. What are the difficulties arising due to MOSFET scaling
Producing MOSFETs with channel lengths much smaller than a micrometer is a
challenge, and the difficulties of semiconductor device fabrication are always a
limiting factor in advancing integrated circuit technology. In recent years, the
small size of the MOSFET has created operational problems. they are
1. Higher sub-threshold condition
2. Increased gate-oxide leakage
3. Increased junction leakage
4. Interconnect capacitance
5. Lower output resistance
6. Heat production.
Important and previous JNTU exam questions:
Raghu Engineering College Dept. of ECE VLSI DESIGN Unit-III
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1. For a CMOS inverter calculate the shift in transfer characteristic curve when
Beta n/ Beta p ratio isvaried from 1/1 to 10/1.(May-2015-Set1(7M)).
DAY-28
Topics to be covered: Scaling Parameters
1. Explain Scaling Parameters
Gate area:
Ag=L X W
Ag(Scaled)=L’ X W’
L W
= α X α =Ag/α2
Gate capacitance per unit area:
€
C0= D
C0(scaled)= €/(D/β)
Gate capacitance:
Cg=C0 X Ag
Cg(scaled)=C0(scaled) X Ag(Scaled)
=βC0 X (Ag/α2)=Cg(β/α2)
Charge in channel( When MOSFET is turned on)
Qon(charge/unit area) =C0 X VGS
Qon(scaled)=βC0 X (VGS/β)
Channel resistance Ron
Ron=(L/W) *(1/σt)
T is the channel thickness
(L/W)*(1/σt)=(L/W)*(1/Qon.μ)
W
Ron(scaled)=¿)/( α ))*(1/Qon.μ)
=Ron
Transistor delay:
Td=Ron * Cg
Td(scaled)=Ron * Cg *(β/α2)
=(β/α2)* Td
Maximum operating frequency:
fmax α (1/ Td)
fmax(scaled)=(α2/β)* fmax
Transistor current:
C 0∗μ∗W
IDS= 2 L (VGS-Vt)2

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W
βC 0∗μ∗( )
α VGS Vt 2
IDS(scaled)= L ( β −β¿
2( )
α
=IDS/β
Switching Energy:
E=(1/2)*Cg*VDD2
E(scaled)=(1/2)*(β/α2)*Cg*¿)2
=(1/α2β)*E
Power dissipation per gate:
-Static power
-dynamic(switching) power
Static:
Ps=VDD2/R
Ps(scaled)=(VDD2/β2)*(1/R)=Ps/β2
Dynamic:
Psw=f*(1/2)*cg*VDD2
Psw(scaled)=(α2/β)*f*((1/2)*(β/α2))Cg*(VDD2/β2)
=(1/β2)Psw
Power dissipation per unit area α (P/Ag)
P
( )
β2
Scales to= Ag
( )
α2
Scaling Factor is α2/β2
Power-delay product scales by (1/β2)*(β/α2)=1/α2β
Note: For constant field scaling α=β and for constant voltage scaling β=1
2. List the limitations of Scaling
Effects, as a result of scaling down- which eventually become severe enough to
prevent
further miniaturization.
Substrate doping
Depletion width
Limits of miniaturization
Limits of interconnect and contact resistance
Limits due to sub threshold currents
Limits on logic levels and supply voltage due to noise
Important and previous JNTU exam questions:

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1. Discuss the limits due to sub threshold currents?(Nov-2016-Set1-7M(Supply)

Raghu Engineering College Dept. of ECE VLSI DESIGN Unit-III