EE 4253/6253 Lecture Notes

October 6, 1998

page 96

SPICE Computation of MOS Capacitance

Definitions:
AS AD PS PD = = = = area of Source area of Drain perimeter of Source perimeter of Drain

The TOX parameter allows computation of Cox Cg = Cg (intrinsic) + Cg (extrinsic) Cg (intrinsic) = Cox W Leff ( only 3 if in saturation )
2

Extrinsic Cg caused by overlap of gate with source/drain and channel

W source L drain

Cgbo caused by poly extension past channel Cgso, Cgdo caused by overlap of poly with source/drain

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October 6, 1998

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Cgbo multiplied by channel length; Cgso, Cgdo multiplied by channel width Typically, gate capacitance will tend to dominate drain, source capacitance but can vary significantly with process. Example from book:
Cg(intrinsic) = W L Cox = 4 1 17 10-4 [pF] = 0.0068 [pF] In this example, the extrinsic gate capacitance for a typical MOS transistor is Cg(extrinsic) = (W Cgso) + (W Cgdo) + (2L Cgbo) = (4 6 10-4) + (4 6 10-4) + 2 (1 2 10-4) [pF] = 0.0052 [pF] In SPICE the capacitance of a source or drain diffusion is calculated as follows: VJ -MJ VJ -MJSW Cj = Area C J 1 + + Periphery CJSW 1 + PB PB where CJ = the zero-bias capacitance per junction area CJSW = the zero-bias junction capacitance per junction periphery MJ = the grading coefficient of the junction bottom MJSW = the grading coefficient of the junction sidewall VJ = the junction potential PB = the built-in voltage (~ 0.4 to 0.8 [V]) Area = AS or AD, the area of the source or drain Periphery = PS or PD, the periphery of the source or drain PB, CJ, CJSW, MJ, and MJSW are specified in the model card. AS, AD, PS, and PD are specified by the element card. VJ depends on circuit conditions. At VJ = 2.5 [V] (half rail (VDD = 5 [V])), Cjdrain = (15 10 -12 2 10 -4 (1 + 2.5/0.7) -0.5) + (11.5 10 -6 4 10 -4 (1 + 2.5/0.7) -0.3) [pF] = (15 2 10-4 0.47) + (11.5 4 10-4 0.63) [pF] = 0.0014 + 0.0029 [pF] = 0.0043 [pF] = 4.3 [fF] Summarizing these capacitances then, Cgtotal = 0.0068 + 0.0052 [pF] = 12 [fF] Cdrain = Csource = 0.0043 [pF] (@ 2.5 [V]).

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October 6, 1998

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Routing Capacitance
fringing field capacitance metal interconnect capacitance to adjacent conductor

parallel capacitance

SiO2 substrate

Fringing Field Capacitance occurs at edge of the conductor and is due to the conductor's finite thickness. Fringing Field Capacitance will cause effective capacitance to increase. Use empirical formulas to estimate. Also have inter-layer capacitances (from p. 196 of text):
A B C D E
20k pass.

m2 m2 m2 C C C
poly

Very computationally intensive to calculate Requires 3-D CAD

m2

12k 6k

m1 C

6k

C m1

m2 m2 m1 C

6k C poly 3k 6k

Substrate

diffusion thin oxide (200)

Typically, just use substrate capacitance multiplied by a C "fudge" factor of ~1.1, ~1.3, or even ~2.0

CONDITION
A B C D E E F G

LAYER
Poly-substrate Metal2-substrate Poly-metal2 Metal1-substrate Metal1-poly Metal1-metal2 Metal1-diffusion Metal2-diffusion

LINE-to-GROUND EQUATION # (see text)

LINE-to-LINE EQUATION # (see text)

EE 4253/6253 Lecture Notes

October 6, 1998

page 99

Delay
Long wire distributed RC line
R C

First-order approximation: r .c .l delay = where r = resistance per unit length c = capacitance per unit length l = length of the wire Important fact interconnect delay does not scale with lambda, it is constant. When lambda decreases, R increases and C decreases, resulting in delay constant Inserting a buffer in a long resistance line can be advantageous. For a poly run = 2mm length, r = 20 /m c = 4 10-4 pF/m 2mm delay = 20 4 10 -4 (2) 2 = 16 ns 2 2
2

If broken into two 1mm sections, then delay of each section = 4ns. Add a buffer with delay = 1ns and total delay becomes 4 + 1 + 4 = 9ns.

EE 4253/6253 Lecture Notes

October 6, 1998

page 100

Typically, resistive effects of interconnect much more important than capacitive effects since capacitance tends to be dominated by the gate capacitances.
Load

Driver

Load

Load

Resistance/Capacitance of interconnect

Capacitance of MOSFET load

MOSFET load capacitance >> wire capacitance [unless DSM (deep submicron ( 0.25m) CMOS technology] So, if we decrease interconnect resistance, then we reduce overall propagation delay between driver and load. Reduce interconnect resistance by using metal, increasing the width of the interconnect. Usually just want delay (RC), where R is the resistance of the interconnect and C is the total of all the capacitive loads.

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October 6, 1998

page 101

Example (from text) A register that fits in data-path is 25m tall (the direction of repetition). A metal2 clock line runs vertically to link all registers in an n-bit register. The register has 30m of 1m metal1, 20m of 1m poly (over field oxide), and 16m of 1m gate capacitance. 1. Calculate the per-bit clock load and the load for a 16-bit register. 2. What would be the RC delay of the register from a clock buffer using 5mm of 1m metal2 (0.05/sq.)? 3. How wide would the clock line have to be to keep the skew below 0.5ns if a register file containing 32 16-bit registers was fed with the same 5mm metal2 wire? Solution: [Capacitance values found in Table 4.6, page 202 of text.] 1. The parasitics are as follows: Cm1 = 30 30 [aF] = 900aF Cpoly = 20 50 [aF] = 1000aF = 1fF Cgs = 16 1800 [aF] = 28,800aF Creg1 = 900 + 1000 + 28,800 [aF] = 30fF Creg16 = 16 Creg1 = 480fF 2. Rmetal2 = 5000 0.05 [/sq.] = 250 Because the capacitance load is at the end of the wire, we approximate the RC delay by adding the metal2 track capacitance to the load capactiance and performing a simpe R C calculation. Ctotal = 0.48 + Cmetal2 [pF] = 0.48 + (5000 20 10-6) [pF] = 0.58pF RC = 250 0.58 10-12 seconds = 0.145ns 3. We now have 32 registers, so the load capacitance of the registers is Cregfile = 32 Creg16 = 15.36pF.

5mm

metal 2 clock line 25m

Bit0 Bit1 Bit2

Bit15 The RC for a 1m-wide clock feed is 250 15.36pF = 3.84ns. Delay of 3.84ns too big, widen the wire to reduce R; will increase C somewhat but capacitance is dominated by cell capacitance. The clock line has to be widened by 3.84/0.5 or 7.68. To be conservative, one might choose a 10m wire. Now Ctotal = 15.36 + Cmetal2 [pF] = 15.36 + (5000 10 20 10-6) [pF] = 16.36pF Note: R reduced by 10x, Ctotal slightly increased RC = 25 16.36 10-12 seconds = 0.41ns

Overall delay went down!

EE 4253/6253 Lecture Notes

October 6, 1998

page 102

For short and lightly loaded wire lengths, can ignore the R and just model wires as lumped capacitances. How short? w << g r .c .l w = 2
2

l << Minimum width (1m) Aluminum wire, gate delay = 200ps

2g rc

Guidelines for ignoring RC wire delays: LAYER MAXIMUM LENGTH () Metal3 10000 Metal2 8000 Metal1 5000 Silicide 600 Polysilicon 200 Diffusion 60

l <<

2 0.2 10 -9 ( g ) 2 0.05[r] 30 10 -18 [c] 16000

So conservatively, l < 5000.

If lambda = 0.5m, ignore RC delay for < 2.5mm metal runs. Do NOT ignore for heavily loaded lines like clock lines!

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October 6, 1998

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Gate Delay Models for Rise/Fall Time

V Input

V Input 50% time tpd Output

time

tdelay,50-50 (or tpd) = time between input reaching 50% point and output reaching 50% point One advantage of using 50% points for measurement is that it does not matter if output is rising or falling (gate inverting or non-inverting). One problem with 50% propagation delays is that you can end up with a negative propagation delay for slowly rising/falling inputs.
V
Input Output

50% pt. time Output begins changing before input reaches 50% point

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October 6, 1998

page 104

Can also define delay at 30% - 70% points, 10% - 90% points, etc. For non-inverting gates, if we use 30% - 70% points: tpdlh - prop delay low to high (measure between 30% input, 30% output)
V

30% time tpdlh

tpdhl - prop delay high to low (measure between 70% input, 70% output)
V

70%

time tpdhl

EE 4253/6253 Lecture Notes

October 6, 1998

page 105

For inverting gates, if we use 30% - 70% points: tpdlh - measure 70% input to 30% output
V input 70% 30% time tpdlh output

tpdhl - measure 30% input to 70% output