Wires

6.884 – Spring 2005 2/11/05 L04 – Wires 1

 Wires are an Old Problem
Cray-1, 1976

Cray-1 Wiring

Cray-3, 1993
Cray-3 wiring

6.884 – Spring 2005 2/11/05 L04 – Wires 2

 Interconnect Problems
ƒ A lot of circuit designers are very worried
about what’s happening with wires in CMOS
technology
ƒ Device technology has been scaling well, with
gate performance increasing linearly with
decreasing feature size
ƒ Wires scale differently, and long wires have
been getting relatively slower over time
ƒ Wire delay is a function of wire resistance and
capacitance

6.884 – Spring 2005 2/11/05 L04 – Wires 3

 Modern Interconnect Stack
Metal 6

Via 5-6

Metal 5

Metal 4

Metal 3
Metal 2
Via 1-2
Metal 1

© IBM
Tungsten local interconnect

IBM CMOS7 process

6 layers of copper wiring © IBM

1 layer of tungsten local interconnect

6.884 – Spring 2005 2/11/05 L04 – Wires 4

 Wire Resistance

resistance =
(length × resistivity )
Height Length (height × width )
• bulk aluminum 2.8x10-8 Ω-m
Width • bulk copper 1.7x10-8 Ω-m
• bulk silver 1.6x10-8 Ω-m

• Height (Thickness) fixed in given manufacturing process

• Resistances quoted as Ω/square
• TSMC 0.18µm 6 Aluminum metal layers
– M1-5 0.08 Ω/square (0.5 µm x 1mm wire = 160 Ω)
– M6 0.03 Ω/square (0.5 µm x 1mm wire = 60 Ω)

6.884 – Spring 2005 2/11/05 L04 – Wires 5

 Local Interconnect
• Use contact material (tungsten) to provide extra layer of
connectivity below metal 1
• Can also play same trick with silicided poly to connect
gates to diffusion directly in RAMs
• Typically used to shrink memory cells or standard cells
• Contacts directly to poly gate or diffusion

Contact plug

Local Wire

6.884 – Spring 2005 2/11/05 L04 – Wires 6

 Via Resistance
• Via resistance significant
• TSMC 0.18µm 6-Al
Vias made from Tungsten Diff-M1 11.0 Ω
in Aluminum processes. Poly-M1 10.4 Ω
Vias are Copper in Copper M2-M1 4.5 Ω
processes M3-M1 9.5 Ω
M4-M1 15.0 Ω
M5-M1 19.6 Ω
M6-M1 21.8 Ω

• Resistance of two via stacks at each end of M1 wire

equivalent to about 0.1 mm wire (~20 Ω)
• Resistance of two via stacks at each end of M6 wire about
the same as 1 mm narrow M6 wire (~60 Ω)!!!
• Use multiple vias in parallel to reduce effective contact
resistance
• Copper processes have lower via resistance

6.884 – Spring 2005 2/11/05 L04 – Wires 7

 Wire Capacitance

H2
ε2
ε12 W2 D12

ε1 H1

εD1 W1 S1 DD1

• Capacitance depends on geometry of surrounding wires and

relative permittivity, εr,of insulating dielectric
– silicon dioxide, SiO2 εr = 3.9
– silicon flouride, SiOF εr = 3.1
– SiLKTM polymer, εr = 2.6
• Can have different materials between wires and between
layers, and also different materials on higher layers

6.884 – Spring 2005 2/11/05 L04 – Wires 8

 IBM Experimental 130nm Process

Al

E. Barth, IBM Microelectronics

6.884 – Spring 2005 2/11/05 L04 – Wires 9

 Capacitance Scaling
width
parallel plate capacitance ∝ × length
spacing

spacing
length

width

ƒ Capacitance/unit length ~constant with feature

size scaling (width and spacing scale together)
– Isolated wire sees approx. 100 fF/mm
– With close neighbors about 160 fF/mm
ƒ Need to use capacitance extractor to get
accurate values

6.884 – Spring 2005 2/11/05 L04 – Wires 10

 RC Delay Estimates

R1 R2 Ri
CN
C1 C2 Ci

Penfield-Rubenstein model estimates:

⎛ j= i ⎞
Delay = ∑⎜ ∑ R j ⎟C i
i ⎝ j=1 ⎠

6.884 – Spring 2005 2/11/05 L04 – Wires 11

 Wire Delay Models
Rdriver R R R
Cload
C C C

ƒ Wire has distributed R and C per unit length

– wire delay increases quadratically with length
– edge rate also degrades quadratically with length
ƒ Simple lumped Π model gives reasonable approximation
– Rw is lumped resistance of wire
– Cw is lumped capacitance (put half at each end)

Rdriver Rw
Cload

Cw/2 Cw/2

Cw ⎛ Cw ⎞
Delay = Rdriver × + (Rdriver + Rw ) × ⎜ + Cload ⎟
2 ⎝ 2 ⎠
6.884 – Spring 2005 2/11/05 L04 – Wires 12
 Wire Delay Example
• In 0.18µm TSMC, 5x minimum inverter with effective
resistance of 3 kΩ, driving FO4 load (25fF)
• Delay = Rdriver x Cload = 75 ps

• Now add 1mm M1 wire, 0.25µm wide

– Rw = 320Ω wire + 22Ω vias = 344Ω
– Cw = 160fF

Cw ⎛ Cw ⎞
Delay = Rdriver× + (Rdriver + Rw) × ⎜ + Cload⎟
2 ⎝ 2 ⎠
= 3kΩ × 80fF + (3kΩ + 344Ω) × (80fF + 25fF)
= 591ps

6.884 – Spring 2005 2/11/05 L04 – Wires 13

 Wire Delay Scaling, Local Wires

ƒ For wire crossing same amount of circuitry

– Resistance stays roughly constant
• length decreases by same amount as width, height stays
large and/or change material to copper
– Capacitance decreases by scaling factor
• cap/unit length constant, length decreases
ƒ Wire delay tracks improvement in gate delay

[ From Mark Horowitz, DAC 2000 ]

6.884 – Spring 2005 2/11/05 L04 – Wires 14

 Wire Delay Scaling, Global Wires

ƒ For wire crossing whole chip

– Resistance grows linearly
– Capacitance stays fixed
ƒ Wire delay increases relative to gate delay

[ From Mark Horowitz, DAC 2000 ]

6.884 – Spring 2005 2/11/05 L04 – Wires 15

 Fewer Gates per Clock Cycle
ƒ Processors in Intel 386 generation, around 50
FO4 gate delays per clock cycle

ƒ Pentium-4 around 16 FO4 in normal clock,

around 8 FO4 delays in fast ALU section

ƒ Fastest 64-bit adder around 7 FO4 delays

ƒ As measured in distance per clock cycle, wires

are getting much slower

6.884 – Spring 2005 2/11/05 L04 – Wires 16

 Process Technology Fixes
ƒ Reduce R
– use copper instead of aluminum, 40% reduction
– provide upper layers with thicker metal for long range
wires
– provide more layers to improve density, makes wires
shorter
ƒ Reduce C
– use low-k dielectric, >2x reduction possible
– increase inter-layer spacing (limited effect, problems with
via formation)
– provide more layers to improve density, makes wires
shorter

6.884 – Spring 2005 2/11/05 L04 – Wires 17

 Layout Fixes
ƒ Reduce R
– make wires wider, increase in C is less than increase in
C because of fringing fields
– use parallel vias at contacts
– floorplanning to keep wires short
– careful routing to avoid unnecessary layer changes
(vias)
ƒ Reduce C
– space wires further apart than minimum
– avoid parallel wiring

6.884 – Spring 2005 2/11/05 L04 – Wires 18

 Circuit Fixes - Repeaters
Rw

Cw

Rw/2 Rw/2

Cw/2 Cw/2

ƒ Use repeaters
ƒ Converts quadratic dependence into linear
dependence on length (but watch the constants)
ƒ Can determine optimal repeater sizing for
minimum delay

6.884 – Spring 2005 2/11/05 L04 – Wires 19

 Repeater Issues

ƒ Repeater must connect to transistor layers

ƒ Blocks other routes with vias that connect down
ƒ Requires space on active layers for buffer transistors and
power connections
ƒ Repeaters often grouped in preallocated repeater boxes
spread around chip
– repeater location might not give ideal spacing

6.884 – Spring 2005 2/11/05 L04 – Wires 20

 Repeater Staging In and Out

Stage up to Cross chip Stage up to

optimal using optimal drive final load
repeater size repeater size

ƒ For minimum delay, must stage up to repeater

size at start of wire, and stage up to load at
end of wire

6.884 – Spring 2005 2/11/05 L04 – Wires 21

 Architectural Fixes: Pentium-4
1
TC Next IP
2 Pipeline stages
3
4
TC Fetch dedicated to driving
5 Drive signals across chip
6 Alloc
7
Rename
8
9 Queue
10 Schedule 1
11 Schedule 2
12 Schedule 3
13 Dispatch 1
14 Dispatch 2
15 Register File 1
16 Register File 2
17 Execute
18 Flags
19 Branch Check
20 Drive
6.884 – Spring 2005 2/11/05 L04 – Wires 22
 Scalable Layout

Wire RC
dominated
path

Gate
dominated
path

ƒ Design such that critical paths are gate

dominated not interconnect dominated on first
target process
ƒ This helps ensure feature size shrinks give
frequency improvements
ƒ If critical path contains too much interconnect
RC, then shrink won’t see much frequency gain

6.884 – Spring 2005 2/11/05 L04 – Wires 23

 Coupling Capacitances
A

CAB
B

CB

ƒ Most capacitance is to neighboring wires

ƒ If A switches, injects voltage noise on B
– magnitude depends on capacitive divider formed:
CAB/(CAB+CB)
ƒ If A switches in opposite direction while B switches,
coupling capacitance effectively doubles – Miller effect
ƒ If A switches in same direction while B switches, coupling
capacitance disappears
ƒ These effects can lead to large variance in possible delay
of B driver, possibly factor of 5 or 6 between best and
worst case

6.884 – Spring 2005 2/11/05 L04 – Wires 24

 Fixing Coupling Problems
A

CAB
B

CB

ƒ Avoid placing simultaneously switching signals

next to each other for long parallel runs
ƒ Reroute signals which will be quiet during
switching inbetween simultaneous switching
signals
ƒ Route signals close to power rails to provide
capacitance ballast
ƒ Tough problem to solve – moving one wire can
introduce new problems
– “timing closure” causes many real-world schedule slips

6.884 – Spring 2005 2/11/05 L04 – Wires 25

 Electromigration
ƒ The electrons from a DC current
flow will tend to push metal atoms
out of place (AC current flow OK)
ƒ Main problem is power lines, but
some signal lines have unidirectional
current
ƒ Manufacturers place a current
density limit for metal to guarantee
small resistance increase after ~10
years operation
ƒ TSMC 0.18µm
– 1mA/µm (metal wires 0.4µm thick)
– 0.28 mA/via

6.884 – Spring 2005 2/11/05 L04 – Wires 26