RF7234

3V TD-SCDMA/W-CDMA LINEAR PA MODULE

BAND 1 AND 1880MHz TO 2025MHz
Package Style: Module, 10-Pin, 3mmx3mmx1.0mm

Features VBAT 1
10 VCC
 TD-SCDMA and HSDPA Com- RF IN
pliant 2 9 RF OUT
 Low Voltage Positive Bias VMODE1
Supply (3.4V to 4.2V) 3 8 CPL IN
Bias Control &
 +28dBm Linear Output VMODE0 PA/VMODE Enable
Power W-CDMA 4 7 GND
(+26.5dBm HSDPA)
VEN
 +27.5dBm Output Power 5 6 CPL OUT
TD-SCDMA
 High Efficiency Operation
35% at POUT =+27.5dBm
(TD-SCDMA)
 20% at POUT =+19.0dBm Functional Block Diagram
(Without DC/DC Converter)
Product Description
 Low Quiescent Current in Low
Power Mode: 17mA The RF7234 is a high-power, high-efficiency, linear power amplifier
designed for use as the final RF amplifier in 3V, 50 TD-SCDMA mobile
 Internal Voltage Regulator cellular equipment and spread-spectrum systems. This PA is developed for
Eliminates the Need for Exter- TD-SCDMA 1880MHz to 1920MHz and 2010MHz to 2025MHz frequency
nal Reference Voltage (VREF)
band, plus W-CDMA Band 1. The RF7234 has two digital control pins to
 3-Mode Power States with select one of three power modes to optimize performance and current
Digital Control Interface drain at lower power levels. The part also has an integrated directional
 Supports DC/DC Converter coupler which eliminates the need for an external discrete coupler at the
Operation output. The RF7234 is fully TD-SCDMA/W-CDMA/HSDPA-compliant and is
assembled in a 10-pin, 3mmx3mm module.
 Integrated Power Coupler
 Integrated Blocking and Col-
lector Decoupling Capacitors
Applications Ordering Information
RF7234 3V TD-SCDMA/W-CDMA Linear PA Module Band 1 and
 TD-SCDMA/HSDPA/W-CDMA 1880MHz to 2025MHz
Wireless Handsets and Data
Cards RF7234PCBA-410 Fully Assembled Evaluation Board

 Dual-Mode UMTS Wireless

Handsets

Optimum Technology Matching® Applied

GaAs HBT SiGe BiCMOS GaAs pHEMT GaN HEMT
GaAs MESFET Si BiCMOS Si CMOS RF MEMS
 InGaP HBT SiGe HBT Si BJT LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.

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RF7234
Absolute Maximum Ratings
Parameter Rating Unit Caution! ESD sensitive device.
Supply Voltage in Standby Mode 6.0 V Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Supply Voltage in Idle Mode 6.0 V Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
Supply Voltage in Operating Mode, 6.0 V tions is not implied.

50 Load RoHS status based on EUDirective2002/95/EC (at time of this document revision).

Supply Voltage, VBAT 6.0 V The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
Control Voltage, VMODE0, 3.5 V license is granted by implication or otherwise under any patent or patent rights of
VMODE1 RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
Control Voltage, VEN 3.5 V
RF - Input Power +6 dBm
RF - Output Power +30 dBm
Output Load VSWR (Ruggedness) 10:1
Operating Ambient Temperature -30 to +110 °C
Storage Temperature -55 to +150 °C

Specification
Parameter Unit Condition
Min. Typ. Max.
T=25°C, VCC =VBATT =3.4V, VEN =1.8V, 50,
Recommended Operating
TD-SCDMA or W-CDMA-GTC1 Modulation,
Conditions unless otherwise specified.
Operating Frequency Range 1880 1920 MHz TD-SCDMA
1920 1980 MHz W-CDMA
2010 2025 Hz TD-SCDMA
VBAT +3.21 +3.4 +4.2 V
VCC +3.21 +3.4 +4.2 V
VEN 0 0.5 V PA disabled.
1.4 1.8 3.0 V PA enabled.
VMODE0, VMODE1 0 0.5 V Logic “low”.
1.4 1.8 3.0 V Logic “high”.
POUT
Maximum Linear Output (HPM) 282 dBm High Power Mode W-CDMA (HPM)
Maximum Linear Output 27.52 dBm High Power Mode (HPM) TD-SCDMA
(HPM)
Maximum Linear Output 19.02 dBm Medium Power Mode (MPM)
(MPM)
Maximum Linear Output 8.02 dBm Low Power Mode (LPM)
(LPM)
Ambient Temperature -25 +25 +85 °C
Notes:
1
Minimum VCC for max POUT is indicated. VCC down to 0.5V may be used for backed-off power when using DC/DC converter to conserve battery
current.
2
For operation at below VCC =3.4V, derate POUT by 1.0dB.

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 RF7234
Specification
Parameter Unit Condition
Min. Typ. Max.
T=+25C, VCC =VBAT =+3.4V, VEN =+1.8V,
Electrical Specifications -
50, W-CDMA modulation unless otherwise
W-CDMA specified.
Gain 25 26.5 dB HPM, POUT =28.0dBm, W-CDMA
15 17.5 dB MPM, POUT 19.0dBm
111 14.5 dB LPM, POUT 8.0dBm
Gain Linearity ±0.2 dB HPM, 19.0dBmPOUT 28.0dBm
ACLR - 5MHz Offset -40 dBc HPM, POUT =28.0dBm
-46 dBc MPM, POUT =19.0dBm
-44 dBc LPM, POUT =8.0dBm
ACLR - 10MHz Offset -55 dBc HPM, POUT =28.0dBm
-60 dBc MPM, POUT =19.0dBm
-64 dBc LPM, POUT =8.0dBm
PAE Without DC/DC Converter 40 % HPM, POUT =28.0dBm
20 % MPM, POUT =19.0dBm
Current Drain 80 mA MPM, POUT =16.0dBm
37 mA LPM, POUT =8.0dBm
20 mA LPM, POUT =0.0dBm
Quiescent Current 85 mA HPM, DC only
20 mA MPM, DC only
17 mA LPM, DC only
Enable Current 0.3 1.0 mA Source or sink current. VEN =1.8V.
Mode Current (IMODE0, IMODE1) 0.3 1.0 mA Source or sink current. VMODE0, VMODE1 =1.8V.
Leakage Current 1.0 10.0 A DC only. VCC =VBAT =3.7V,
VEN =VMODE0 =VMODE1 =0.5V.
Input Impedance 2.0:1 VSWR No ext. matching, POUT 28dBm, all modes.
Harmonic, 2FO -28 dBm POUT 28.0dBm
Harmonic, 3FO -35 dBm POUT 28.0dBm
Spurious Output Level -70 dBc All spurious, POUT 28dBm, all conditions, load
VSWR6:1, all phase angles.
Insertion Phase Shift -30 +30 ° Phase shift at 19dBm when switching from
HPM to MPM and MPM to LPM at 8dBm.
DC Enable Time 10 S DC only. Time from VEN =high to stable idle cur-
rent (90% of steady state value).
RF Rise/Fall Time 6 S POUT 28.0dBm, all modes. 90% of target, DC
settled prior to RF.
Coupling Factor -19.5 dB POUT 28.0dBm, all modes.
Coupling Accuracy - Temp/Voltage ±0.5 dB POUT 28.0dBm, all modes. -30°CT85°C,
3.0VVCC & VBAT 4.2V, referenced to 25°C,
3.4V conditions.
Coupling Accuracy - VSWR ±0.5 dB POUT 28dBm, all modes, load VSWR=2:1,
±0.5dB accuracy corresponds to 15dB direc-
tivity.
Note: 1Excludes DC/DC converter operation. Gain may be lower when using DC/DC converter to conserve battery current.
Note: 2Unless otherwise marked , each spec is equivalent for W-CDMA or TD-SCDMA operation.

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RF7234
Specification
Parameter Unit Condition
Min. Typ. Max.
T=+25C, VCC =VBAT =+3.4V, VEN =+1.8V,
Electrical Specifications -
50, TD-SCDMA modulation unless otherwise
TD-SCDMA specified.
Gain 26.5 dB HPM, POUT =27.5dBm
15 17.5 dB MPM, POUT 19.0dBm
111 14.5 dB LPM, POUT 8.0dBm
Gain Linearity ±0.2 dB HPM, 19.0dBmPOUT 27.5dBm
ACLR - 1.6MHz Offset -40 dBc HPM, POUT =27.5dBm
-42 dBc MPM, POUT =19.0dBm
-42 dBc LPM, POUT =8.0dBm
ACLR - 3.2MHz Offset -56.0 -57.5 dBc HPM, POUT =27.5dBm
-60 dBc MPM, POUT =19.0dBm
-63 dBc LPM, POUT =8.0dBm
PAE Without DC/DC Converter 35 % HPM, POUT =27.5dBm
20 % MPM, POUT =19.0dBm
4.5 % LPM, POUT =8.0dBm
Current Drain 425 mA HBM, POUT =27.5dBm (during active timeslot)
120 mA LPM, POUT =19dBm (during active timeslot)
40 mA LPM, POUT =8.0dBm (during active timeslot)
Quiescent Current 85 mA HPM, DC only
20 mA MPM, DC only
17 mA LPM, DC only
Enable Current 0.3 1.0 mA Source or sink current. VEN =1.8V.
Mode Current (IMODE0, IMODE1) 0.3 1.0 mA Source or sink current. VMODE0, VMODE1 =1.8V.
Leakage Current 1.0 10.0 A DC only. VEN =VMODE0 =VMODE1 =0.5V.
Input Impedance 2.0:1 VSWR No ext. matching, POUT 27dBm, all modes.
Harmonic, 2FO -28 dBm POUT 27.5dBm, HPM.
Harmonic, 3FO -35 dBm POUT 27.5dBm, HPM.
SEM Margin 3 dB POUT =27.5dBm, HPM
Spurious Output Level -70 dBc All spurious, POUT 27.5dBm, all conditions,
load VSWR6:1, all phase angles.
Insertion Phase Shift -30 +30 ° Phase shift at 19dBm when switching from
HPM to MPM and MPM to LPM at 8dBm.
DC Enable Time 10 S DC only. Time from VEN =high to stable idle cur-
rent (90% of steady state value).
RF Rise/Fall Time 6 S POUT 27.5dBm, all modes. 90% of target, DC
settled prior to RF.
Coupling Factor -19.5 dB POUT 27.5dBm, all modes.
Coupling Accuracy - Temp/Voltage ±0.5 dB POUT 27.5dBm, all modes. -25°CT85°C.
See W-CDMA condition notes.
Coupling Accuracy - VSWR ±0.5 dB POUT 27.5dBm, all modes, load VSWR=2:1.
EVM 1.8 % POUT =27.5dBm, VCC =3.4V
Note: 1Excludes DC/DC converter operation. Gain may be lower when using DC/DC converter to conserve battery current.
Note: 2Unless otherwise marked , each spec is equivalent for W-CDMA or TD-SCDMA operation.

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 RF7234
Pin Function Description
1 VBAT Supply voltage for bias circuitry and the first stage amplifier.
2 RF IN RF input internally matched to 50 and DC blocked.
3 VMODE1 Digital control input for power mode selection (see Operating Modes truth table).
4 VMODE0 Digital control input for power mode selection (see Operating Modes truth table).
5 VEN Digital control input for PA enable and disable (see Operating Modes truth table).
6 CPL_OUT Coupler output.
7 GND This pin must be grounded.
8 CPL_IN Coupler input used for cascading couplers in series. Terminate this pin with a 50 resistor if not connected to
another coupler.
9 RF OUT RF output internally matched to 50and DC blocked.
10 VCC Supply voltage for the second stage amplifier which can be connected to battery supply or output of DC-DC con-
verter.
Pkg GND Ground connection. The package backside should be soldered to a topside ground pad connecting to the PCB
ground plane with multiple ground vias. The pad should have a low thermal resistance and low electrical imped-
Base ance to the ground plane.

VEN VMODE0 VMODE1 VBAT VCC Conditions/Comments

Low Low Low 3.4V to 3.8V 3.4V to 3.8V Power down mode
Low X X 3.4V to 3.8V 3.4V to 3.8V Standby Mode
High Low Low 3.4V to 3.8V 3.4V to 3.8V High power mode
High High Low 3.4V to 3.8V 3.4V to 3.8V Medium power mode
High High High 3.4V to 3.8V 3.4V to 3.8V Low power mode
High High High 3.4V to 3.8V 0.5V Optional lower VCC in low power mode

Package Drawing

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RF7234
Preliminary Application Schematic
VBAT
VCC
1
10
C5 C72
4.7uF 10nF C82 C6 C4
J1 J2 10nF 4.7uF
2 9 22uF
RF IN RF OUT

VMODE1 3 8
Bias Control &
C92 R23
VMODE0 PA/VMODE Enable
10nF 4 7 50 
C102
10nF
VEN 5 6
J3
C112 CPL OUT
10nF

NOTES:
1 VCC and VBAT are connected together if DC-DC converter is not used.
2 Place these capacitors as close to PA as possible.
3 50  resistor will be removed if pin 8 is connected to another coupler.

P1
1 GND

P1-2 2 VEN

P1-3 3 VMODE0

P1-4 4 VMODE1

P1-5 5 VCC1

6 GND

P1-7 7 VCC2

P1-8 8 VCC2S

9 GND
CON9

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 RF7234
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch
to 8inch gold over 180inch nickel.

PCB Land Pattern Recommendation

PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown
has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate
lead and package tolerances. Since surface mount processes vary from company to company, careful process development is
recommended.

PCB Metal Land Pattern

Figure 1. PCB Metal Land Pattern (Top View)

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RF7234
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB
metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The
center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be
provided in the master data or requested from the PCB fabrication supplier.

Figure 2. PCB Solder Mask Pattern (Top View)

Thermal Pad and Via Design

The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device.

Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been
designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing
strategies.

The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a
0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the
quantity of vias be increased by a 4:1 ratio to achieve similar results.

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