1Gb DDR3 SDRAM

1Gb DDR3 SDRAM

Lead-Free&Halogen-Free
(RoHS Compliant)
H5TQ1G83DFR-xxC
H5TQ1G83DFR-xxI
H5TQ1G83DFR-xxL
H5TQ1G83DFR-xxJ
H5TQ1G63DFR-xxC
H5TQ1G63DFR-xxI
H5TQ1G63DFR-xxL
H5TQ1G63DFR-xxJ

*Hynix Semiconductor reserves the right to change products or specifications without notice

Rev. 1.8 /June. 2013

1
Revision History

Revision No. History Date Remark

1.0 Added IDD Value Aug. 2010

1.1 Corrected Typo Error Sep. 2010

1.2 Corrected Typo Error(Ordering Information) Oct. 2010

1.3 Added 1866/2133 Speed Support Dec. 2010

1.4 Added IDD Specification(1866/2133 Speed) Dec. 2010

1.5 Modified OPERATING FREQUENCY Table Dec. 2010

1.6 Added J and L-part support Jun. 2011

1.7 Updated 1866/2133 x8 IDD Specification Sep. 2011

and 1866 Frequency downbinning

1.8 Commercial Temperature Range update June. 2013 0oC ~ 85 oC --> 0oC ~ 95 oC

Rev. 1.8 /June. 2013 2

Description
The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and
high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-
width.

Device Features and Ordering Information

FEATURES
• DQ Power & Power supply : VDD & VDDQ = 1.5V +/- • Programmable BL=4 supported (tCCD=2CLK) for Digi-
0.075V tal consumer Applications.
• DQ Ground supply : VSSQ = Ground • Programmable ZQ calibration supported
• Fully differential clock inputs (CK, CK) operation • BL switch on the fly
• Differential Data Strobe (DQS, DQS) • 8banks
• On chip DLL align DQ, DQS and DQS transition with CK  • Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
transition
- 7.8 µs at -0oC ~ 85 oC
• DM masks write data-in at the both rising and falling  - 3.9 µs at 85oC ~ 95 oC
edges of the data strobe o o
Commercial Temperature ( 0 C ~ 95 C)
• All addresses and control inputs except data,  Industrial Temperature ( -40oC ~ 95 oC)
data strobes and data masks latched on the 
• Auto Self Refresh supported
rising edges of the clock
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13
and 14 supported • Driver strength selected by EMRS
• Programmable additive latency 0, CL-1, and CL-2  • Dynamic On Die Termination supported
supported • Asynchronous RESET pin supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, • TDQS (Termination Data Strobe) supported (x8 only)
10
• Write Levelization supported
• Programmable burst length 4/8 with both nibble 
• On Die Thermal Sensor supported
sequential and interleave mode
• 8 bit pre-fetch
• Programmable PASR(Partial Array Self-Refresh) for
Digital consumer Applications.

* This product in compliance with the RoHS directive.

Rev. 1.8 /June. 2013 3

ORDERING INFORMATION

Part No. Configuration Power Consumption Temperature Package

H5TQ1G83DFR-*xxC Commercial
Normal Consumption
H5TQ1G83DFR-*xxI Industrial
128M x 8 78ball FBGA
H5TQ1G83DFR-*xxL Low Power Consumption Commercial

H5TQ1G83DFR-*xxJ (IDD6 Only) Industrial

H5TQ1G63DFR-*xxC Commercial
Normal Consumption
H5TQ1G63DFR-*xxI Industrial
64M x 16 96ball FBGA
H5TQ1G63DFR-*xxL Low Power Consumption Commercial

H5TQ1G63DFR-*xxJ (IDD6 Only) Industrial

* xx means Speed Bin Grade

OPERATING FREQUENCY

Speed Frequency [MHz]

Remark
Grade
(CL-tRCD-tRP)
(Marking) CL5 CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 CL14

-G7 O O O O DDR3-1066 7-7-7

-H9 O O O O O O DDR3-1333 9-9-9

-PB O O O O O O O DDR3-1600 11-11-11

-RD O O O O O O O DDR3-1866 13-13-13

-TE O O O O O O O O O O DDR3-2133 14-14-14

Rev. 1.8 /June. 2013 4

Package Ballout/Mechanical Dimension
x8 Package Ball out (Top view): 78ball FBGA Package (no support balls)

1 2 3 4 5 6 7 8 9

A VSS VDD NC NU/TDQS VSS VDD A

B VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B
C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C
D VSSQ DQ6 DQS VDD VSS VSSQ D
E VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E
F NC VSS RAS CK VSS NC F
G ODT VDD CAS CK VDD CKE G
H NC CS WE A10/AP ZQ NC H
J VSS BA0 BA2 NC VREFCA VSS J
K VDD A3 A0 A12/BC BA1 VDD K
L VSS A5 A2 A1 A4 VSS L
M VDD A7 A9 A11 A6 VDD M
N VSS RESET A13 NC A8 VSS N

1 2 3 4 5 6 7 8 9

1 2 3 7 8 9

A
B
C
D
E (Top View: See the balls through the Package)
F
G Populated ball
H Ball not populated
J
K
L
M
N

Rev. 1.8 /June. 2013 5

x16 Package Ball out (Top view): 96ball FBGA Package (no support balls)

1 2 3 4 5 6 7 8 9

A VDDQ DQU5 DQU7 DQU4 VDDQ VSS A

B VSSQ VDD VSS DQSU# DQU6 VSSQ B
C VDDQ DQU3 DQU1 DQSU DQU2 VDDQ C
D VSSQ VDDQ DMU DQU0 VSSQ VDD D
E VSS VSSQ DQL0 DML VSSQ VDDQ E
F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F
G VSSQ DQL6 DQSL# VDD VSS VSSQ G
H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H
J NC VSS RAS# CK VSS NC J
K ODT VDD CAS# CK# VDD CKE K
L NC CS# WE# A10/AP ZQ NC L
M VSS BA0 BA2 NC VREFCA VSS M
N VDD A3 A0 A12/BC# BA1 VDD N
P VSS A5 A2 A1 A4 VSS P
R VDD A7 A9 A11 A6 VDD R
T VSS RESET# NC NC A8 VSS T

1 2 3 4 5 6 7 8 9

1 2 3 7 8 9

A
B
C
D
E
F (Top View: See the balls through the Package)
G
H Populated ball
J Ball not populated
K
L
M
N
P
R
T

Rev. 1.8 /June. 2013 6

Pin Functional Description
Symbol Type Function

Clock: CK and CK are differential clock inputs. All address and control input signals are
CK, CK Input
sampled on the crossing of the positive edge of CK and negative edge of CK.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank).
CKE, (CKE0),
Input CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable
(CKE1)
during the power on and initialization sequence, they must be maintained during all
operations (including Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power-
down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS, (CS0), Chip Select: All commands are masked when CS is registered HIGH.
(CS1), (CS2), Input CS provides for external Rank selection on systems with multiple Ranks.
(CS3) CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
ODT, (ODT0), NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8
Input
(ODT1) configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL,
DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable
ODT.
RAS. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input
CAS. WE
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM, (DMU), DM is sampled HIGH coincident with that input data during a Write access. DM is sampled
Input
(DML) on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by
Mode Register A11 setting in MR1.
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge
BA0 - BA2 Input command is being applied. Bank address also determines if the mode register or extended
mode register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for Active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective
A0 - A15 Input
bank. (A10/AP and A12/BC have additional functions, see below).
The address inputs also provide the op-code during Mode Register Set commands.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
A10 / AP Input
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank
addresses.
Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst
A12 / BC Input chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Rev. 1.8 /June. 2013 7

 Symbol Type Function

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation.
RESET Input
RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e.
1.20V for DC high and 0.30V for DC low.
Input /
DQ Data Input/ Output: Bi-directional data bus.
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
DQU, DQL,
centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential
DQS, DQS, Input /
signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the
DQSU, DQSU, Output
system during reads and writes. DDR3 SDRAM supports differential data strobe only and
DQSL, DQSL
does not support single-ended.
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
TDQS, TDQS Output function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11
= 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x16
DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
NC No Connect: No internal electrical connection is present.
NF No Function
VDDQ Supply DQ Power Supply: 1.5 V +/- 0.075 V
VSSQ Supply DQ Ground
VDD Supply Power Supply: 1.5 V +/- 0.075 V
VSS Supply Ground
VREFDQ Supply Reference voltage for DQ
VREFCA Supply Reference voltage for CA
ZQ Supply Reference Pin for ZQ calibration
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.

Rev. 1.8 /June. 2013 8

ROW AND COLUMN ADDRESS TABLE
1Gb
Configuration 128Mb x 8 64Mb x 16
# of Banks 8 8
Bank Address BA0 - BA2 BA0 - BA2
Auto precharge A10/AP A10/AP
BL switch on the fly A12/BC A12/BC
Row Address A0 - A13 A0 - A12
Column Address A0 - A9 A0 - A9
Page size 1 1 KB 2 KB

Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers 
when an ACTIVE command is registered. Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG  8
where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

Rev. 1.8 /June. 2013 9

Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,3
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V 1
TSTG o
Storage Temperature -55 to +100 C 1, 2
Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

DRAM Component Operating Temperature Range

Temperature Range
Symbol Parameter Rating Units Notes
oC
Normal Operating Temperature Range 0 to 85 1,2
Extended Temperature Range 85 to 95 oC
TOPER 1,4
-40 to 95 oC 1,3,4
Industrial Temperature Range
Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between -40 - 85oC under all operating condi-
tions.
4. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Man-
ual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).

Rev. 1.8 /June. 2013 10

AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions

Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.500 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.500 1.575 V 1,2
Notes:

1. Under all conditions, VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

Rev. 1.8 /June. 2013 11

IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-
rents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:

• ”0” and “LOW” is defined as VIN <= VILAC(max).

• ”1” and “HIGH” is defined as VIN >= VIHAC(min).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}

Rev. 1.8 /June. 2013 12

 IDD IDDQ (optional)

VDD VDDQ
RESET
CK/CK
DDR3
SDRAM
CKE DQS, DQS RTT = 25 Ohm
CS DQ, DM, VDDQ/2
RAS, CAS, WE TDQS, TDQS

A, BA
ODT
ZQ
VSS VSSQ

Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]

Application specific IDDQ

memory channel Test Load
environment

Channel
IDDQ IDDQ
IO Power
Simulation Simulation
Simulation

Correction

Channel IO Power
Number

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement

Rev. 1.8 /June. 2013 13

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Symbol Unit
7-7-7 9-9-9 11-11-11 13-13-13 14-14-14
tCK 1.875 1.5 1.25 1.07 0.935 ns
CL 7 9 11 13 14 nCK
nRCD 7 9 11 13 14 nCK
nRC 27 33 39 45 50 nCK
nRAS 20 24 28 32 36 nCK
nRP 7 9 11 13 14 nCK
1KB page size 20 20 24 26 27 nCK
nFAW
2KB page size 27 30 32 33 38 nCK
1KB page size 4 4 5 5 6 nCK
nRRD
2KB page size 6 5 6 6 7 nCK
nRFC -512Mb 48 60 72 85 97 nCK
nRFC-1 Gb 59 74 88 103 118 nCK
nRFC- 2 Gb 86 107 128 150 172 nCK
nRFC- 4 Gb 160 200 240 281 321 nCK
nRFC- 8 Gb 187 234 280 328 375 nCK

Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol Description
Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT
and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO:
IDD0
MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see

Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 3.
Operating One Bank Active-Read-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between
ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to
IDD1
Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table

4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 4.

Rev. 1.8 /June. 2013 14

 Symbol Description
Precharge Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID-LEVEL; DM: stable at 0; Bank

Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;
Pattern Details: see Table 5.
Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2NT Bank Address Inputs: partially toggling according to Table 6; Data IO: MID-LEVEL; DM: stable at 0; Bank

Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling
according to Table 6; Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2P0 Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down

Mode: Slow Exitc)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2P1 Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down

Mode: Fast Exitc)

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD2Q
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD3N Bank Address Inputs: partially toggling according to Table 5; Data IO: MID-LEVEL; DM: stable at 0; Bank

Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;
Pattern Details: see Table 5.

Rev. 1.8 /June. 2013 15

 Symbol Description
Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address,
IDD3P
Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command,
Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst
IDD4R
with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer

and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command,
Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst
IDD4W
with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buf-

fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current

CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com-
IDD5B mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID-LEVEL; DM:
stable at 0; Bank Activity: REF command every nREC (see Table 9); Output Buffer and RTT: Enabled in

Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9.

Self-Refresh Current: Normal Temperature Range

TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6 CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address,
Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out-

put Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL

Self-Refresh Current: Extended Temperature Range

TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-

IDD6ET ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command,
Address, Bank Address Inputs, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Extended Tempera-

ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-
LEVEL

Rev. 1.8 /June. 2013 16

 Symbol Description
Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a)f); AL: CL-1;
CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according
IDD7 to Table 10; Data IO: read data burst with different data between one burst and the next one according
to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with

different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 10.

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Rev. 1.8 /June. 2013 17

Table 3 - IDD0 Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE
Datab)

CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High

1*nRC+3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling

... repeat pattern nRC+1...4 until 1*nRC + nRAS - 1, truncate if necessary

1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC+1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Rev. 1.8 /June. 2013 18

Table 4 - IDD1 Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE
Datab)

CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High

1*nRC+3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling

... repeat pattern nRC + 1,...4 until nRC + nRCD - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until 2* nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.8 /June. 2013 19

Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE
Datab)

CS
0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High

1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead

toggling

2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead

3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-27 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE

Datab)
CS

0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High

1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

toggling

2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2

3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-27 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Rev. 1.8 /June. 2013 20

Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE
Datab)

CS
0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1 D 1 0 0 0 0 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5 D 1 0 0 0 0 0 00 0 0 F 0 -
Static High

6,7 D,D 1 1 1 1 0 0 00 0 0 F 0 -
toggling

1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1

2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.8 /June. 2013 21

Table 8 - IDD4W Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE
Datab)

CS
0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1 D 1 0 0 0 1 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5 D 1 0 0 0 1 0 00 0 0 F 0 -
Static High

6,7 D,D 1 1 1 1 1 0 00 0 0 F 0 -
toggling

1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1

2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

Table 9 - IDD5B Measurement-Loop Patterna)

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

WE

Datab)
CS

0 0 REF 0 0 0 1 0 0 0 0 0 0 0 -
1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
Static High

9...12 repeat cycles 1...4, but BA[2:0] = 2

toggling

13...16 repeat cycles 1...4, but BA[2:0] = 3

17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.

Rev. 1.8 /June. 2013 22

Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9

Command
Number
Sub-Loop

A[15:11]
BA[2:0]

A[9:7]

A[6:3]
CK, CK

A[2:0]
A[10]
Cycle

ODT
RAS

CAS
CKE

Datab)

WE
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
1
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
2 2*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
3 3*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
4*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
4
Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Static High

9
toggling

Assert and repeat above D Command until 2* nFAW - 1, if necessary

2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
10
D 1 0 0 0 0 0 00 0 0 F 0 -
2*nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
11
D 1 0 0 0 0 1 00 0 0 0 0 -
2*nFAW+nRRD+2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
D 1 0 0 0 0 3 00 0 0 0 0 -
14 2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
D 1 0 0 0 0 7 00 0 0 0 0 -
19 3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.8 /June. 2013 23

IDD Specifications
IDD values are for full operating range of voltage and temperature unless otherwise noted.
IDD Specification
Speed Grade DDR3 - 1066 DDR3 - 1333 DDR3 - 1600 DDR3 - 1866 DDR3 - 2133
Bin 7-7-7 9-9-9 11-11-11 13-13-13 14-14-14 Unit Notes
Symbol Max. Max. Max. Max. Max.
IDD0 45 45 50 55 65 mA x8
55 58 60 65 75 mA x16
IDD1 50 55 60 65 75 mA x8
65 68 70 75 85 mA x16
IDD2N 30 30 30 30 30 mA x8/x16
40 40 mA x8
IDD2NT 30 30 35
40 40 mA x16
IDD2P0 10 10 10 10 10 mA x8/x16
IDD2P1 20 20 20 20 20 mA x8/x16
IDD2Q 30 30 30 30 35 mA x8/x16
IDD3N 45 45 45 45 50 mA x8/x16
IDD3P 25 25 25 25 30 mA x8/x16
80 90 105 130 140 mA x8
IDD4R
130 140 160 175 185 mA x16
80 90 105 130 140 mA x8
IDD4W
130 140 160 175 185 mA x16
110 115 120 125 135 mA x8
IDD5B
120 130 150 155 165 mA x16
IDD6 10 10 10 10 10 mA x8/x16
IDD6ET 12 12 12 12 12 mA x8/x16
IDD6TC 12 12 12 12 12 mA x8/x16
IDD6 Low Power 6 6 6 6 6 mA x8/x16
130 140 150 190 210 mA x8
IDD7
180 200 210 230 250 mA x16

Notes:

1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC.

2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC.

Rev. 1.8 /June. 2013 24

 Input/Output Capacitance
DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133
Parameter Symbol Units Notes
Min Max Min Max Min Max Min Max Min Max
Input/output capacitance
(DQ, DM, DQS, DQS, CIO 1.5 2.7 1.5 2.5 1.5 2.3 1.4 2.2 1.4 2.1 pF 1,2,3
TDQS, TDQS)
Input capacitance, CK
CCK 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF 2,3
and CK
Input capacitance delta
CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4
CK and CK
Input capacitance delta,
CDDQS 0 0.20 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,5
DQS and DQS
Input capacitance
CI 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF 2,3,6
(All other input-only pins)
Input capacitance delta CDI_CTR
-0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 2,3,7,8
(All CTRL input-only pins) L
Input capacitance delta
C
(All ADD/CMD input-only DI_ADD -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4 pF 2,3,9,10
_CMD
pins)
Input/output capacitance
delta CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11
(DQ, DM, DQS, DQS)
Input/output capacitance
CZQ - 3 - 3 - 3 - 3 - 3 pF 2,3,12
of ZQ pin
Notes:
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK 
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, 
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK.

5. Absolute value of CIO(DQS)-CIO(DQS).

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTR applies to ODT, CS and CKE.

8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance an ZQ pin: 5 pF.

Rev. 1.8 /June. 2013 25

Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-1066 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-1066

Unit Note
CL - nRCD - nRP 7-7-7
Parameter Symbol min max
Internal read command to first
tAA 13.125 20 ns
data

ACT to internal read or write

tRCD 13.125 — ns
delay time

PRE command period tRP 13.125 — ns

ACT to ACT or REF command

tRC 50.625 — ns
period

ACT to PRE command period tRAS 37.5 9 * tREFI ns

1,2,3,4,6,
CWL = 5 tCK(AVG) 3.0 3.3 ns
CL = 5 10,11
CWL = 6 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6
CL = 6
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5 tCK(AVG) Reserved ns 4
CL = 7
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,4
CWL = 5 tCK(AVG) Reserved ns 4
CL = 8
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3
Supported CL Settings 5, 6, 7, 8 nCK 13
Supported CWL Settings 5, 6 nCK

Rev. 1.8 /June. 2013 26

DDR3-1333 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-1333

Unit Note
CL - nRCD - nRP 9-9-9
Parameter Symbol min max
Internal read command to first
tAA 13.5 20 ns
data

ACT to internal read or write

tRCD 13.5 — ns
delay time

PRE command period tRP 13.5 — ns

ACT to ACT or REF command

tRC 49.5 — ns
period

ACT to PRE command period tRAS 36 9 * tREFI ns

1,2,3,4,7,
CWL = 5 tCK(AVG) 3.0 3.3 ns
CL = 5 10,11
CWL = 6, 7 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7
CL = 6 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7
CWL = 7 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
1.875 < 2.5
CL = 7 CWL = 6 tCK(AVG) (Optional) ns 1,2,3,4,7
Note 5,11
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5 tCK(AVG) Reserved ns 4
CL = 8 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,7
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5, 6 tCK(AVG) Reserved ns 4
CL = 9
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4
CWL = 5, 6 tCK(AVG) Reserved ns 4
CL = 10 1.5 <1.875 ns 1,2,3
CWL = 7 tCK(AVG)
(Optional) ns 5
Supported CL Settings 5,6,(7),9,(10) nCK
Supported CWL Settings 5, 6, 7 nCK

Rev. 1.8 /June. 2013 27

DDR3-1600 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-1600

Unit Note
CL - nRCD - nRP 11-11-11
Parameter Symbol min max
Internal read command to first
tAA 13.75 20 ns
data
ACT to internal read or write
tRCD 13.75 — ns
delay time

PRE command period tRP 13.75 — ns

ACT to ACT or REF command

tRC 48.75 — ns
period

ACT to PRE command period tRAS 35 9 * tREFI ns

1,2,3,4,8,
CWL = 5 tCK(AVG) 3.0 3.3 ns
CL = 5 10,11
CWL = 6, 7, 8 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8
CL = 6 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 7, 8 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
1.875 < 2.5
CWL = 6 tCK(AVG) (Optional) ns 1,2,3,4,8
CL = 7
Note 5,11
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 8 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,8
CL = 8
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5, 6 tCK(AVG) Reserved ns 4
1.5 <1.875
CL = 9 CWL = 7 tCK(AVG) (Optional) ns 1,2,3,4,8
Note 5,11
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5, 6 tCK(AVG) Reserved ns 4
CL = 10 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8
CWL = 8 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5, 6,7 tCK(AVG) Reserved ns 4
CL = 11
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3

Supported CL Settings 5,6,(7),8,(9),10,11 nCK

Supported CWL Settings 5, 6, 7, 8 nCK

Rev. 1.8 /June. 2013 28

DDR3-1866 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.

Speed Bin DDR3-1866

Unit Note
CL - nRCD - nRP 13-13-13
Parameter Symbol min max
13.91(13.125)
Internal read command to
tAA (Optional Note 5,11) 20 ns
first data
Note 5,
ACT to internal read or write 13.91(13.125)
tRCD — ns
delay time (Optional Note 5,11)
13.91(13.125)
PRE command period tRP — ns
(Optional Note 5,11)
ACT to PRE command
tRAS 34 9 * tREFI ns
period
ACT to ACT or PRE 47.91(47.125)
tRC - ns
command period (Optional Note 5,11)
CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4, 9
CL = 5
CWL = 6,7,8,9 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3, 9
CL = 6 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 7,8,9 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
1, 2, 3, 4,
CL = 7 CWL = 6 tCK(AVG) 1.875 (Optional) < 2.5 (Optional) ns
9,11
CWL = 7,8,9 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3, 9
CL = 8
CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 8,9 tCK(AVG) Reserved ns 4
CWL = 5, 6 tCK(AVG) Reserved ns 4
1, 2, 3, 4,
CWL = 7 tCK(AVG) 1.5 (Optional) <1.875 (Optional) ns
CL = 9 9,11
CWL = 8 tCK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 9 tCK(AVG) Reserved ns 4
CWL = 5, 6 tCK(AVG) Reserved ns 4
CL = 10 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1, 2, 3, 9
CWL = 8 tCK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 5,6,7 tCK(AVG) Reserved ns 4
1, 2, 3, 4,
CL = 11 CWL = 8 tCK(AVG) 1.25 (Optional) <1.5 (Optional) ns
9,11
CWL = 9 tCK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CL = 12
CWL = 9 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CL = 13
CWL = 9 tCK(AVG) 1.07 <1.25 ns 1, 2, 3

Rev. 1.8 /June. 2013 29

 Supported CL Settings 6, (7), 8, (9), 10, (11), 13 nCK
Supported CWL Settings 5, 6, 7, 8, 9 nCK

DDR3-2133 Speed Bins

For specific Notes see “Speed Bin Table Notes” on page 31.
Speed Bin DDR3-2133
CL - nRCD - nRP 14-14-14 Unit Note
Parameter Symbol min max
Internal read command to
tAA 13.09 20.0 ns
first data
ACT to internal read or write
tRCD 13.09 — ns
delay time
PRE command period tRP 13.09 — ns
ACT to PRE command period tRAS 33.0 9 * tREFI ns
ACT to ACT or PRE
tRC 46.09 - ns
command period
CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4, 10
CL = 5
CWL = 6,7,8,9,10 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3, 10
CL = 6 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4, 10
CWL = 7,8,910 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3, 10
CL = 7
CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4, 10
CWL = 8,9,10 tCK(AVG) Reserved ns 4
CWL = 5 tCK(AVG) Reserved ns 4
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3, 10
CL = 8
CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4, 10
CWL = 8,9,10 tCK(AVG) Reserved ns 4
CWL = 5, 6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1, 2, 3, 10
CL = 9
CWL = 8 tCK(AVG) Reserved ns 1, 2, 3, 4, 10
CWL = 9,10 tCK(AVG) Reserved ns 4
CWL = 5, 6 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1, 2, 3, 9
CL = 10 CWL = 8 tCK(AVG) Reserved ns 1, 2, 3, 4, 9
CWL = 9 tCK(AVG) Reserved ns 4
CWL = 10 tCK(AVG) Reserved ns 4
CWL = 5,6,7 tCK(AVG) Reserved ns 4
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1, 2, 3, 10
CL = 11
CWL = 9 tCK(AVG) Reserved ns 1, 2, 3, 4, 10
CWL = 10 tCK(AVG) Reserved ns 1, 2, 3, 4
CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CL = 12
CWL = 9 tCK(AVG) Reserved ns 1,2,3,4, 10
CWL = 10 tCK(AVG) Reserved ns 4
CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CL = 13 CWL = 9 tCK(AVG) 1.07 <1.25 ns 1, 2, 3, 10
CWL = 10 tCK(AVG) Reserved 1, 2, 3, 4

Rev. 1.8 /June. 2013 30

 CWL = 5,6,7,8,9 tCK(AVG) Reserved ns 4
CL = 14
CWL = 10 tCK(AVG) 0.935 <1.07 ns 1, 2, 3
Supported CL Settings 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 nCK
Supported CWL Settings 5, 6, 7, 8, 9, 10 nCK

Speed Bin Table Notes

Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to Hynix DIMM data sheet and/or the DIMM SPD information if and how this set-
ting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
11. Hynix DDR3 SDRAM devices supporting optional down binning to CL=7, 9 and CL=11, and tAA/tRCD/
tRP must be 13.125 ns. SPD settings must be programmed to match. For example, DDR3-1866 RD
devices supporting down binning to DDR3-1600K or DDR3-1333 H9 or 1066 G7 should program
13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP
(Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly.
For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333 H9 and 48.125ns
(tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600 PB.
12. For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not manda-
tory in SPD coding.

Rev. 1.8 /June. 2013 31

Package Dimensions
Package Dimension(x8): 78Ball Fine Pitch Ball Grid Array Outline
7.500  0.100
A1 CORNER
INDEX AREA (1.875)
1.100  0.100
0.340  0.050
(2.750)

11.000  0.100
3.0 X 5.0 MIN
FLAT AREA

TOP

SIDE
0.800 X 8 = 6.400

2.100  0.100
0.800
0.550  0.100
A1 BALL MARK
9 8 7 3 2 1

A
B
C
0.150  0.050

2-R0.130 MAX
D
0.800

E
0.800 X 12 = 9.600

F
G
H
J
K
L
M
N
0.700  0.100

78 x 0.450  0.050
1.600 1.600

BOTTOM

Rev. 1.8 /June. 2013 32

Package Dimension(x16): 96Ball Fine Pitch Ball Grid Array Outline
7.500  0.100
A1 CORNER
INDEX AREA (1.875) 1.100  0.100
0.340  0.050
(3.250)

13.000  0.100
3.0 X 5.0 MIN
FLAT AREA

TOP

0.800 X 8 = 6.400
SIDE
2.100  0.100
0.800
0.550  0.100

A1 BALL MARK
9 8 7 3 2 1
A
B
C
D
E
0.400

F
0.150  0.050

2-R0.130 MAX
0.800 X 15 = 12.000

G
H
J
K
L
M
N
P
R
T
0.500  0.100

96 x 0.450  0.050
1.600 1.600

BOTTOM

Rev. 1.8 /June. 2013 33