Code: UR19-PE-PG-EC206 H.T.No.
:
USHA RAMA COLLEGE OF ENGINEERING AND TECHNOLOGY
(An Autonomous College in the jurisdiction of JNTUK, Kakinada)
I M. Tech II Semester Regular Examinations, July-2021
LOW POWER VLSI DESIGN
(VLSI & Embedded Systems)
Time: 3 hours Max. Marks: 5x14 = 70
Answer either A or B from each Question. All Questions carry equal marks
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1.A. i) Write a brief note about the need of low power VLSI design? 7M (BL2)
ii) Discuss about transistor sizing and optimal gate oxide thickness? 7M (BL2)
OR
1.B. Explain different types of power dissipation in CMOS circuits and discuss any 7M (BL2)
three methods in detail ?
2.A. i) List High performance Approaches in low power circuit techniques ? 7M (BL3)
ii) Explain about chip and package co-design of clock network ? 7M (BL2)
OR
2.B. i) Explain about Versus distributed buffers in detail ? 7M (BL4)
ii) Write a short note on Reversible pipelines ? 7M (BL2)
3.A. Write in detail about Power minimization techniques ? 14M (BL5)
OR
3.B. Explain about circuit design styles, adders, multipliers ? 14M (BL6)
4.A. i) Explain sources of power dissipation in DRAM and SRAM ? 7M (BL4)
ii) Write about low-power DRAM circuits ? 7M (BL2)
OR
4.B. i) Explain the reduction of power dissipation in memory subsystem ? 7M (BL3)
ii) Write about techniques at memory design to low power SRAM circuits ? 7M (BL3)
5.A. i) Discuss about architectural trade-offs for power? 7M (BL3)
ii) Explain about low-power clocking ? 7M (BL2)
OR
5.B. i) Explain about Power management support in microprocessor design system ? 7M (BL2)
ii) Discuss about implementation problem for low power ? 3M (BL3)
iii) Compare the microprocessors for power and performance? 4M (BL4)
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