A

PROJECT REPORT

on

DESIGN OF LOW AREA LOW POWER

COMBINATIONAL CIRCUITS USING CNTFET’S

Submitted in partial fulfillment of the requirements for the award

of the degree of
MASTER OF TECHNOLOGY

In

VLSI DESIGN

by

KOTHURI . SRAVANI

(Roll No: 19JD1D7210)

Under the esteemed guidance of
Miss M.PRIYANKA M.Tech
Assistant Professor of ECE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY

DUGGIRALA (V), PEDAVEGI (M), ELURU-534004

APPROVED BY AICTE-NEW DELHI&AFFILIATED TO JNTUK-KAKINADA

2019 -2022
 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

ELURU COLLEGE OF ENGINEERING AND TECHNOLOGY

DUGGIRALA (V), PEDAVEGI (M), ELURU-534004

APPROVED BY AICTE-NEW DELHI&AFFILIATED TO JNTUK-KAKINADA

2019 -2022

CERTIFICATE
This is to certify that the project entitled “Design of low area low power combinational circuits
using CNTFET’s” being submitted by K. SRAVANI (19JD1D7210), in view of academic
curriculum, Degree of Bachelor of Technology in Electronic and Communication Engineering during
2019 – 2022 and is a bonfide work carried out by them under my guidance and supervision.

PROJECT GUIDE HEAD OF THE DEPARTMENT

Mis M.PRIYANKAM.Tech Dr. B.RAJA RAO M.Tech.,Ph.D

Assistant Professor Professor & HOD of ECE

EXTERNAL EXAMINER
 ACKNOWLEDGEMENT

In the beginning I want to elucidate that this project would have been a distant dream
without the grace of Almighty God who has blessed us with a drop of knowledge from his
mighty ocean.
I am very grateful to my project guide M.PRIYANKA M.Tech for his inspiration, adroit
guidance, constant supervision and constructive criticism in successful completion of this
project. he provided organization, supported enthusiastic discussions, in depth reviews and
valuable references.
I am very grateful to the head of the ECE Department Dr.B.RAJARAO Ph.D Professor
for his valuable guidance, motivation and endless supply of new ideas and technical
support for this project.
I am thankful to our Principal Dr. P. BALAKRISHNA PRASAD Ph.D for permitting
and encouraging me in doing this project.

I extend my sincere thanks to Sri V. Raghavendra Rao, Chairman of our college for
providing sufficient infrastructure and good environment in the college to complete my
course.
Great acknowledgement is expressed to Coordinator, Teaching and Non- Teaching Staff
Members whose guidance cannot be ignored in completing this project in time

KOTHURI.SRAVANI

(19JD1D7210)
 DECLARATION

I here by declaring that the project work entitled “Design of low area low power
combinational circuits using CNTFET’s” submitted to JNTU Kakinada, is a record of
original work done by me.

This project work is submitted in the partial fulfillment for the degree of Master of
Technology in Very large scale integration Circuit Design.

The results embedded in this thesis have not been submitted to any other University
or Institute for the award of any degree or Diploma.

KOTHURI.SRAVANI

(19JD1D7210)
 INDEX

TABLE OF CONTENT`

DESCRIPTION Page No.

LIST OF FIGURES i

LIST OF TABLES iii

LIST OF ACRONYMS iv
ABSTRACT V
CHAPTER 1: INTRODUCTION 1
1.1 VLSI 2
1.2 Basic Concepts of VLSI 2
1.3 History of VLSI 3
1.4 Applications of VLSI 4

1.5 Approach for design of CNTFET’S in VLSI 5

1.6 logic design styles in VLSI 9
CHAPTER 2: LITERATURE SURVEY 11
Literature Survey 12
CHAPTER 3: EXISTING SYSTEM 17
3.1 Unary Operators 18
3.2 Multi-Trit Multiplier 20
3.3Ternary Half Adder 20
CHAPTER 4: PROPOSED SYSTEM 23
4.1 Proposed Unary operators 24
4.2 Proposed Ternary Half Adder 25
4.3 Ternary Multiplier 27
CHAPTHER 5: SIMULATION RESULTS 32
5.1 Simulation 32
5.1.1 Results for THA 33
5.1.2 Results for TMUL 37
5.3 Results for process variations 42
5.4 Results for Noise signal 44

CHAPTER 6 CONCLUSON 46
6.1 Advantages 47
6.2 Applications 47
6.3 Future Scope 47

REFERENCES 48
APPENDIX 51
A1: ABOUT SIMULATION TOOL 51
A2: JOURNAL PUBLICATION
 LIST OF FIGURES
Fig No. Figure Name Page No.

1.5.1 Complete CNTFET device model 5

1.5.2 Schematic diagram of ternary half adder 7
1.5.3 Block diagram of TMUL 9
2.1 108-Transistors THA circuit 12

2.2 THA with 85-transistors 12

2.3 TMUL with 61-transistors 13
2.4 Proposed designs for ternary NAND and NOR 13
2.5 THA with 90 transistors using proposed TMUX 14
2.6 TMUX having 15 CNTFET’s 15

2.7 TMUL with 60-transistors 15

3.1.1 CNTFET-based circuits for unary operators 18

3.1.2 Block diagram of multiplexer 19

3.2.1 Single-trit multiplier CNTFET- based realization 20
3.3.1 CNTFET-based realization of ternary half adder 21

4.1.1 Proposed unary operators 24

4.2.1 Proposed THA design 26

4.3.1 Proposed ternary multiplier 27
5.1.1.1 Schematic diagram of ternary half adder 33
5.1.1.2 Test bench circuit for ternary half adder 34

5.1.1.3 Transient analysis of the ternary half adder 35

5.1.1.4 Power results of ternary half adder 36
5.1.1.5 Delay results for ternary half adder 37
5.1.2.1 Schematic design of TMUL 38
5.1.2.2 Test bench circuit of ternary multiplier 39
5.1.2.3 Transient analysis of ternary multiplier 40
5.1.2.4 Power results for ternary multiplier 41

5.1.2.5 Delay results for ternary multiplier 42

i
5.3.1 Voltage variations 43
5.3.2 Temperature variations 44
5.4.1 Noise signal 45

ii
 LIST OF TABLES

Table No. Table name Page No.

19
3.1.1 Truth table of multiplexer
3.3.1 Truth table of ternary half adder 21

4.1.1 CNTFET operation 25

4.1.2 Truth table for unary operators 25
4.2.1 Truth table for ternary half adder 26
4.3.1 Truth table for proposed TMUL 28
4.3.2 Truth table for carrier version 2 28
4.3.3 Truth table for carrier version 3 29
4.3.4 Truth table for carrier version 4 29
4.3.5 THA’s comparison 30
4.3.6 TMUL’s comparison 31

iii
 LIST OF ACRONYMS
ACRONYM DESCRIPTION

THA Ternary Half Adder

TMUL Ternary Multiplier

S-edit Schematic edit

T-spice Tanner spice

W-edit Waveform edit

PTL Pass Transistor Logic

CPL Complementary Pass transistor Logic

Nm Nano Meter

CMOS Complementary Metal Oxide Semiconductor

C-CMOS Complementary CMOS

PDP Power Delay Product

TG Transmission Gate

TGA Transmission Gate Adder

LPHS Low Power High Speed

iv
 ABSTRACT
Embedded systems, Internet of Things (IoT) gadgets, and portable
electronic devices have all become highly popular in recent years. The majority of
them run on batteries. The major goal of this project is to reduce battery usage
while also providing an energy-efficient solution for low-power portable
electronics and embedded systems.
Using 32nm CNFET’s, the project proposes ternary combinational circuits.
This study employs a power supply that provides two voltage supplies (Vdd and
Vdd/2) and so reduces the overall energy consumption in the circuit to reduce
energy consumption by exploiting the unary operator of ternary systems. This
proposed design show the improvements in the 25% in transistor count and 98% in
energy consumption reduction’s.

Keywords: CNTFET’s, Unary operators, Ternary combinational circuit

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 DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S

CHAPTER-1
INTRODUCTION
1. INTRODUCTION
Now a days, in our day to day life every electronic gadget is compressed of
the combinational circuits in which FET’S plays a vital role. In microprocessors
these adders requires high power and where delay will also be high. so, in order
to reduce that a high speed and low power combinational circuit’s is designed
through very largescale integrated circuits.

1.1 VLSI

Very-large-scale integration (VLSI) is the process of creating an integrated

circuit (IC) by combining thousands of transistors into a single chip. VLSI began
in the 1970s when complex semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device. The term is no longer as
common as it once was, as chips have increased in complexity into the hundreds of
millions of transistors.

1.2 BASIC CONCEPT OF VLSI

The first semiconductor chips held one transistor each. Subsequent
advances added more and more transistors, and, as a consequence, more
individual functions or systems were integrated over time. The first integrated
circuits held only a few devices, perhaps as many as ten diodes, transistors,
resistors and capacitors, making it possible to fabricate one or more logic gates
on a single device. Now known retrospectively as "small-scale integration"
(SSI), improvements in technique led to devices with hundreds of logic gates,
known as large-scale integration (LSI), i.e. systems with at least a thousand
logic gates. Current technology has moved far past this mark and today's
microprocessors have many millions of gates and hundreds of millions of
individual transistors.
At one time, there was an effort to name and calibrate various levels of
largescale integration above VLSI. Terms like Ultra-large-scale Integration
(ULSI) were used. But the huge number of gates and transistors available on
common devices.

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Terms suggesting greater than VLSI levels of integration are no longer in

widespread use. Even VLSI is now somewhat quaint, given the common
assumption that all microprocessors are VLSI or better.

As of early 2008, billion-transistor processors are commercially available,

an example of which is Intel's Montecito itanium chip. This is expected to
become more commonplace as semiconductor fabrication moves from the
current generation of 65 nm processes to the next 45 nm generations (while
experiencing new challenges such as increased variation across process
corners). Another notable example is NVIDIA’s 280 series GPU.
This microprocessor is unique in the fact that its 1.4 Billion transistor count,
capable of a teraflop of performance, is almost entirely dedicated to logic
(Itanium's transistor count is largely due to the 24MB L3 cache). Current
designs, as opposed to the earliest devices, use extensive design automation and
automated logic synthesis to lay out the transistors, enabling higher levels of
complexity in the resulting logic functionality. Certain high-performance logic
blocks like the SRAM cell, however, are still designed by hand to ensure the
highest efficiency (sometimes by bending or breaking established design rules
to obtain the last bit of performance by trading stability).

1.3 HISTORY OF VLSI

1. Late 40s transistors invented at Bell Labs
2. early 60s Small Scale Integration (SSI)
3. 10s of transistors on a chip
4. late 60s Medium Scale Integration (MSI)
5. 100s of transistors on a chip
6. early 70s Large Scale Integration (LSI)
7. 1000s of transistor on a chip
8. early 80s VLSI 10,000s of transistors on a
9. chip (later 100,000s & now 1,000,000s)
10. Ultra LSI is sometimes used for 1,000,000s
11. SSI - Small-Scale Integration (0-102)
12. MSI - Medium-Scale Integration (102-103)
13. LSI - Large-Scale Integration (103-105)
14. VLSI - Very Large-Scale Integration (105-107)

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1.4APPLICATIONS OF VLSI:
Electronic systems now perform a wide variety of tasks in daily life.
Electronic systems in some cases have replaced mechanisms that operated
mechanically, hydraulically, or by other means; electronics are usually smaller,
more flexible, and easier to service. In other cases electronic systems have
created totally new applications. Electronic systems perform a variety of tasks,
some of them visible, some more hidden:

1. Personal entertainment systems such as portable MP3 players and DVD

players perform sophisticated algorithms with remarkably little energy.

2. Electronic systems in cars operate stereo systems and displays; they also
control fuel injection systems, adjust suspensions to varying terrain, and perform the
control functions required for antilock braking (ABS) systems.

3. Digital electronics compress and decompress video, even at highdefinition

data rates, on-the-fly in consumer electronics.

4. Low-cost terminals for Web browsing still require sophisticated electronics,

despite their dedicated function.

5. Personal computers and workstations provide word-processing, financial

analysis, and games. Computers include both central processing units (CPUs) and special-
purpose hardware for disk access, faster screen display, etc.

6. Medical electronic systems measure bodily functions and perform complex

processing algorithms to warn about unusual conditions.

7. The availability of these complex systems, far from overwhelming

consumers, only creates demand for even more complex systems.

The growing sophistication of applications continually pushes the design

and manufacturing of integrated circuits and electronic systems to new levels of
complexity. And perhaps the most amazing characteristic of this collection of
systems is its variety-as systems become more complex, we build not a few
general-purpose computers but an ever wider range of special-purpose systems.
Our ability to do so is a testament to our growing mastery of both integrated
circuit manufacturing and design, but the increasing demands of customers
continue to test the limits of design and manufacturing.

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1.5 APPROACH FOR DESIGN OF CNTFET’S IN VLSI

A combinational circuit can be designed by using FET’s, they are many

types of FET’s are there, But CNTFET’s are more prominent among them,
Complete CNFET device model is implemented with hierarchical three levels.
Level 1, CNFET_L1, models the intrinsic behaviour of CNFET. The second
level, CNFET_L2, includes the device nonidealities.
The first two levels deal with only one CNT under the gate. The top level,
CNFET_L3, model deals with the interface between the CNFET device and
CNFET circuits. This level deals with multiple CNTs per device and includes the
parasitic gate capacitance and screening due to adjacent CNTs As shown in Fig
1.5.2.

Fig 1.5.1: complete CNTFET device model

Carbon nano tube with multiple diameter is placed between source and drain
terminals, Due to the applied voltage to the gate terminal integrates the current
flow in CNT which helps in easy flow of current from source to drain. Threshold
voltage depends on the diameter of the carbon nano tube, Switching depends on
the diameter of the carbon nano tube. Ternary half adders and Ternary
multipliers can be designed by using CNTFET’s

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MULTI VALUED LOGIC (MVL):

In terms of circuit design, it is important to note that MVL methods are not
germane only to implementations that encode logic values as more than two
discrete voltage or current signals, but that MVL methods are also important as
models for the initial design of logic circuits whether they are implemented with
binary or MVL signal levels.

The issue of whether the ultimate realization of a logic circuit is binary or

not depends on the underlying technology and is independent of the use of
MVL. As an example, complementary metal oxide semiconductor (CMOS)-
based logic circuitry is generally implemented in binary logic since technology
issues make binary the best choice.

The point here is that this is merely an issue of the encoding of logic values
and, as the following circuit examples indicate, the use of MVL concepts in the
design stage often leads to circuits that exhibit better characteristics than would
be obtained if only binary-valued logic were utilized.

There are two kinds of MVL circuits based on MOS technology, namely the
current-mode MVL circuits and the voltage mode MVL circuits. Voltage-mode
MVL circuits have been achieved in multi threshold CMOS design. The carbon
nanotube (CNT) FET (CNTFET) is a promising alternative to the bulk silicon
transistor for low-power and high-performance design due to its ballistic
transport and low OFF-current properties.

A multi threshold CMOS design relies on body effects using different bias
voltages to the base or the bulk terminal of the transistors. In a CNTFET, the
threshold voltage of the transistor is determined by the diameter of the CNT.
Therefore, a multi threshold design can be accomplished by employing CNTs
with different diameters (and, therefore, chirality) in the CNTFETs. A resistive-
load CNTFET-based ternary logic design.

However, in this configuration, large OFF-chip resistors (of at least 100

MΩ values) are needed due to the current requirement of the CNTFETs. The
MVL relies on and eliminates the large resistors by employing active load with
p-type CNTFETs in the ternary logic gates.

TERNARY HALH ADDER(THA):

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A THA is a combinational digital circuit that accepts two1-bit ternary inputs and provides two outputs SUM
and CARRY. A new technique was introduced for voltage mode MVL using CNFETs with resistive pull-
ups. A sum gate was designed to perform ternary addition on two inputs IN1 andIN2 to provide the sum
output was carried out using CNFET switch pull-up resistors. and ternary full adder, and multiplier designs
and analysis are presented as examples of the application of these ternary gates design technique.
For the arithmetic circuit design, a modified ternary logic circuit design
technique is used to speed up and reduce power consumption of the circuits.
Themodified ternary logic design uses both ternary logic gates and binary logic
gates based on the previous ternary logic design structures to take advantage of

the two logic design styles’ merits.

Figure 1.5.2 shows the schematic diagram and the symbol of sum
operator. SUM output for different combination of two 1-bitternary inputs can
be obtained

Fig 1.5.2: schematic diagram of ternary half adder

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 DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S
TERNARY MULTIPLIER(TMUL):
Integrated Circuit (IC) technologies, implemented using binary logic
systems have been dominating the hardware for many decades. From the
Moore’s Law, it can be understood that we cannot shrink the transistor sizes
perpetually. Hence, have to come up with new technologies i.e. beyond CMOS
technologies.
since, in submicron and nano range, the CMOS devices have reliability
issues. It is also noted that for a particular circuit, ternary logic system,
theoretically requires lesser chip area, reduced interconnects and it has faster
operating speeds when compared to the radix-2 system. Carbon Nanotube Field
Effect Transistor (CNFET) has been widely used for the implementation of the
ternary logic circuits.

CNFET uses a single carbon nanotube (CNT) or an array of carbon

nanotubes which are analogous to bulk silicon in MOSFETs. The single-walled
CNT behaves as conducting or semi-conducting path/channel depending on the
chirality vector, which is given by the atom arrangement angle along the tube.

Using CMOS devices, ternary logic circuits it has been shown that the
performance of CMOS-based circuit designs can be improved by adding MVL
blocks to binary designs. A 2-bit ternary ALU design is designed, where
negative voltage levels were used to indicate the third state. Various intriguing
designs for single trit addition and single trit multiplication. A ternary logic
system is a multi valued logic (MVL) system with three logic levels which
correspond to logic 0, logic1 and logic 2. In a balanced or ternary neutral system,
the three logic levels are identified as -1, 0 and 1.

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Fig 1.5.3: Block diagram of TMUL
In fig 1.5.3 block diagram of the ternary multiplier with unary operators as
shown above unary operators are the one input and the one output logic devices
out will be fixed in this work 5 unary operators are used.

1.6 LOGIC DESIGN STYLES IN VLSI

In VLSI, adder can be designed through three logic styles which are CMOS logic
style, transmission gate and pass transistor logic.

CMOS logic style is a combination of the pMOS and nMOS.it provides the
delay of the adder. the main advantage of the CMOS style is voltage scaling and
transistor sizing. but the disadvantage is usage of more transistors leads to
greater area. another one is weak driving capability which can be corrected by
adding buffers at the output terminal.

In transmission gate style the pMOS and nMOS are connected in parallel
and control signals are given to separately to both the channels. It performs
better compared to the CMOS logic style because of its decrease in no of
transistors and in terms of delay.

Pass transistor logic is used to reduce the number of the transistors in the
logic function. In this design style the primary inputs drives drain and source
terminals which leads to reduce number of transistors. due to decrease of the
transistors count the capacitance becomes low. It reduces number of transistors
compared to CMOS and TG styles.

Here, the full adder can be realized through hybrid approach for four different circuits.
Transmission gate, CMOS style and using inverters two designs.

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CHAPTER-2
LITERATURE SURVEY

In 2020, H. Chowdary [12] was presented a design of Ternary Half Adder

using the GNRFET’s with hundred and eight transistors as shown in fig 2.1.
Multi Valued Logic with conventional design technique is used, the fundamental
approach is to control the threshold voltage and other electrical properties of
GNRFETs by changing the width of the GNRs to obtain different output levels.

Fig 2.1: 108-transistors THA circuit [12]

It has high PDP and large memory is required and high transistor count.

In 2019, ABDALLAH KASSEM[13] was presented a design of ternary

combinational circuits using CNTFET’s , THA with 85-transistors and TMUL
with 61-transistors as shown in fig 2.1 and fig 2.2 respectively

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Fig 2.2: THA with 85-transistors [13]

MVL with two voltage supplies were used in this design to reduce the transistor count

Fig 2.3: TMUL with 61-transistors [13]

The drawback of this design is it has medium Transistor count and medium PDP

In 2020, FURQAN ZAHOOR[14] was presented a design of ternary logic

circuits using CNTFET’s using RRAM(Resistive Random Access Memory) with
the transistor count of 62 as shown in the fig 2.4

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Fig 2.4: Proposed designs for ternary NAND and NOR [14]

It has medium transistor count and medium PDP and the design of the circuit is
complex as well.

In 2020, Ramzi A. Jaber [16] was presented a design of ternary half adder with
novel decoder less design.
Using unary operator by cascading TMUX”s technique , without using the
decoder. MVL reduces the Interconnections and energy consumption in the
circuit. THA with 90-transistors as shown in fig 6.

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Fig 2.5: THA with 90 transistors using proposed TMUX. [16]

Fig 2.5 shows the TMUX with 15 CNTFET’s using cascading multiplexers
technique without using the decoder in the design, MVL reduces the
interconnections in the circuit and also PDP

Fig 2.6: TMUX having 15 CNTFET’s[16]

In 2020 Abdallah Kassem[17] was presented a design of Ternary Multiplier using

Only Multiplexers using cascading of multiplexers technique with the 60
CNTFET’s as shown in the figure 10

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Fig 2.7: TMUL with 60-transistors [17]

It has the medium PDP and less number of transistor count compared to the
previous work Ternary Multiplier using a ternary multiplexer based on 32 nm
channel CNTFET, which intends to enhance performance and energy efficiency.
The TMUL had higher robustness and noise tolerance among other designs.

Five different designs of combinational circuits using CNTFET’s are

presented. It shows improvement in terms of power delay product (PDP) and
transistor count.

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CHAPTER-3
EXISTING SYSTEM

A multi ternary digit (trit) multiplier design by B. Srinivasu and K. Sridharan

[18] in Carbon Nanotube Field Effect Transistor (CNTFET) technology using
unary operators of multivalued logic. Is based on the classical Wallace multiplier
and includes a novel ternary multiplexer design requiring only a small number of
CNTFETs. Two ternary full-adder configurations are also proposed based on an
examination of the multiplier structure.

3.1 UNARY OPERATORS:

Two ternary full-adder configurations are also existed based on an
examination of the multiplier structure. we present a low-CNTFET count design
of a multi ternary digit (trit) multiplier based on the classical Wallace multiplier.
The existing multiplier includes a novel ternary multiplexer design requiring only
a small number of CNTFETs. This is achieved using unary operators of
multivalued logic.

Fig 3.1.1: CNTFET-based circuits for unary operators[18]

In fig 3.1.1 three different unary operators are shown, Unary operators are
the single input single output logic devices which helps in the reduce the logic
gates in the circuit, Unary operators along with the Multi Valued Logic is used to
design the existing design of multiplexer
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In terms of circuit design, it is important to note that MVL methods are not
germane only to implementations that encode logic values as more than two
discrete voltage or current signals, but that MVL methods are also important as
models for the initial design of logic circuits whether they are implemented with
binary or MVL signal levels.

Fig 3.1.2: Block diagram of multiplexer [18]

Table3.1.1: truth table of multiplexer [18]

In fig 3.1.2 block diagram and table 3.1.1 shows truth table of multiplexer is
shown and the adders are connected in the multi-trit(3-trit) multiplier. The inputs
of the traditional multiplexer having the 3 inputs 0,1 and 2 as they use the
multivalued logic. NCNTFET will be ON for high input, PCNTFET will be on for
Low input.

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3.2 MULTI-TRIT MULTIPLIER:

A single-trit multiplier can be realized with 26 CNTFETs. The select signal
B for carry and product, requires 9 CNTFETs while 8 CNTFETs are required for
the internal logic of the two multiplexers. The complete circuit. The overall
CNTFET requirement is therefore 26. the existed multiplier is based on the
classical Wallace tree structure. The multiplier includes ternary half-adders and
two custom full-adder configurations, named F A1 and F A2 which are
modifications of the traditional ternary full adder.

fig 3.2.1: single-trit multiplier CNTFET-based realization [18]

In fig 3.2.1 represents the single trit multiplier based on the CNTFET
realisation using 26- transistors which lesser compared to the previous works and
it do have low PDP and transistor count

3.3 TERNARY HALF ADDER:

The motivation for developing special full-adder configurations is as
follows. The inputs to a traditional ternary full-adder have three logic levels
namely, 0, 1 and 2. However, the carry output of the proposed single-trit
multiplier is restricted

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to 0 or 1. we note that the sum and carry outputs need two MUXs each with select
signal B and one MUX with select signal C.

Altogether, the 6 MUXs require 32 CNTFETs (each MUX requires 4

CNTFETs while 8 CNTFETs are required for the control signals Each single-trit
multiplier requires 26 CNTFETs while F A1, F A2 and the half-adder take 59, 46
and 35 CNTFETs respectively. Hence, the single-trit multipliers together take 234
CNTFETs while the adders take 650 CNTFETs. Therefore, the proposed design is
realized with 884 CNTFETs

Fig 3.3.1: CNTFET-based realization of the ternary half-adder [18]

Table 3.3.1: Truth for ternary half adder [18]

In the fig 3.3.1 shows ternary half adder and table2 shows truth table of the ternary
half adder is shown

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A ternary multiplexer requiring only 15 CNTFETs can be realized utilizing unary

operators for the seleced signal. The truth table for a ternary multiplexer is given where

S is the select signal and D0, D1 and D2 are the data lines. where SP is the output of a
positive ternary inverter and SN is the output of a negative ternary inverter. It is worth
noting that the select signals SP and SN are the positive and negative ternary
inverters, each of which requires
The main drawback of the existing model is due use of single voltage
source the heat is increased within the circuit called JOULE POWER effect. In
proposed model two voltages are used to reduce the JOULE POWER effect.

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CHAPTER-4
PROPOSED SYSTEM

4.1 : PROPOSED UNARY OPERATORS

This project uses CNTFET transistors and unbalanced ternary logic system
(Low: 0, Middle: 1, High: 2) that is equivalent to (0, Vdd /2, Vdd ). The circuit’s total
power consumption is divided into two types: static power and dynamic power. This
project uses a power supply that generates two voltage supplies Vdd and Vdd /2 to
remove these two transistors and accordingly decrease the overall energy
consumption in the circuit.

A ternary multiplexer requiring only 15 CNTFETs can be realized utilizing

unary operators for the select signal. The truth table for a ternary multiplexer is
given. where S is the select signal and D0, D1 and D2 are the data lines. where SP is
the output of a positive ternary inverter and SN is the output of a negative ternary
inverter. It is worth noting that the select signals SP and SN are the positive and
negative ternary inverters, each of which requires 2 CNTFETs.

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Fig 4.1.1: Proposed unary operators

Table 4.1.1: CNTFET operation

In fig 4.1.1 and table 4.1.1shows proposed five unary operators with D1 and D2 diameter
and CNTFET operation for D1 and D2 is shown

Table 4.1.2: Truth table for unary operators

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In table 4.1.2 the unary operators shown which shows the on and off conditions
of the transistors.

4.2 PROPOSED TERNARY HALF ADDER:

Half adders and 1-trit multipliers are employed in bigger structures like arithmetic
processing units and are critical components in VLSI circuits. As a result, increasing the
efficiency of these circuits can increase the performance of bigger processing units. Two
input variables and two output variables comprise a half-adder circuit. The cumulative
number is used as an input variable, while sum and carry are used as output variables. The
author devised a novel method that did not require the use of a decoder in order to solve
the problem. THA's design the use of a decoder is no longer necessary. Unary functions
are created. The computation of the unary functions transistor-level circuits The ternary
output from these routines is provided by low-power encoders.

A one-trit THA combines two ternary inputs and produces two ternary values (Sum and
Carry).
Based on unary operators, TGs, and two voltage supplies (Vdd, Vdd /2), this research
presents a THA with 36 CNFETs. From the input "A" to the output "Sum," the maximum
propagation delay exists in this. When the input "A" moves from 1 to 2, "B" = 2, and the
Sum changes from 0 to 1, this route is referred to as the critical path (red dotted line).

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Fig 4.2.1: proposed THA design

In fig 4.2.1 the ternary half adder design for the proposed design is shown with red dotted
line called Critical path

Table 4.2.1: truth table for ternary half adder

In table 4.2.1 the ternary half adder is given shows the on and off conditions the
transistors input “A” changes from 1 to 2, “B” = 2, and the sum changes from 0 to 1

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4.3 TERNARY MULTIPLIER

Fig 4.3.1: Proposed ternary multiplier

Fig 4.3.1 represents the proposed ternary multiplier with 23 transistors with lower
power and low PDP compared to the existing work

The base multiplier is based on the classic Wallace approach. Uses 3: 1

multiplexer and ternary unary operator logic. This article describes the design of a
low power single trit multiplier Describes the use of CNFETs. The simulation data
for this design shows that the power delay product (PDP) is significantly lower
With a new design of single trit multiplier. 1-trit TMUL multiplies two ternary
inputs and two outputs. 3 values (Product & Carry).

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This proposed TMUL with 23 CNFETs. Use unary operator, TG, and two
power supplies (Vdd, Vdd / 2) In the figure 4.2.2 The red dotted line is the critical
path between the input `` A`` and output `` Product``. Occurs when `` A`` Change
state from 1 to 2, "B" = 1 and product It changes from 1 to 2. Two cascade TGs that
create more propagation delay.

Table 4.3.1: Truth table for proposed TMUL

Product = 0 · B0 + A · B1 + ¯A2B2

Table 4.3.1 represents the truth table for the proposed TMUL which provides
the sufficient information for the on and off conditions of the transistor

Table 4.3.2: Truth table for carrier version 2

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Table 4.3.3: truth table of carrier version 3

Table 4.3.4: truth table of carrier version 4

Table 4.3.2, 4.3.3and 4.3.4 represents the truth tables of carrier with different
versions. As there are different voltages are used to reduce the Joule power effect
and also total power consumption in the circuit.

Table 4.3.5: THA’s comparison

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Table 4.3.5 compares the proposed ternary half adder with different existing
models [12], [13], [16], [18], [19], [22], [23], [24], [25], [26], [27], [28] and [29]. As
it shows that proposed design consumes low power for switching and also very less
transistor count and low PDP.

Table 4.3.6: TMUL’s comparisons

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Table 4.3.6 compares the proposed ternary multiplier with different existing models
[13], [14], [17], [18], [19], [20], [22], [24] and [29]. As it shows that proposed
design consumes low power for switching and also very less transistor count and
low PDP

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CHAPTER-5
SIMULATION RESULTS

5.1 SIMULATION

5.1.1 RESULTS FOR THA

Ternary half adder is designed using Tanner tool designed in the s-edit tool as
shown in the figure 5.1.1.1.

Fig 5.1.1.1: schematic diagram of ternary half adder

Ternary Half adder is designed by 36-transistors using CNTFET’s based on

unary operators, TG’s and two voltage supplies (vdd, vdd/2). The maximum
propagation delay in this design takes place from the input “A” to the output “sum”.
This is referred as the critical path.
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Fig 5.1.1.2: test bench circuit for ternary half adder

In this test bench circuit interconnections are done and the measuring devices are
connected externally to find the power, delay and internal noise in the circuit.

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Temperature sweep is added to find the parameters with respect to the desire
temperature. Measure inverting delay component’s one is connect to the input side of
the test bench and another is connected to the output side. Print power is used to print
the power consumed by the circuit with respect to temperature as shown in the figure
5.1.1.2.

Fig 5.1.1.3: transient analysis of the ternary half adder

Transient analysis of the ternary half adder is observed in w-edit tool to obtain
the two inputs and sum, carry, four print voltage components are used connect to the
output side of the test bench hence the “A”, “B”
“sum” and “carry” are observed in the w-edit tool interface as shown in the
figure 5.1.1.3

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Fig 5.1.1.4: power results of ternary half adder

To find the power, Print Power measuring device is added to the test bench and
when we run the simulation power values with respect to the different temperatures
were obtained because temperature sweep is included in the circuit. Average power
consumed at temp 0 is 1.393995e+001 watts and max and min are 2.411675e+001
and 0 respectively at time 1.1e-008 for max power as shown in the figure 5.1.1.4.

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Fig 5.1.1.5: delay results for ternary half adder

To find the delay, Measure inverting delay component is connect to the test
bench the simulated output waveforms are obtained with respect to the temperature
and the total delay in the design is 8.7ps. And the simulated result obtained is lesser
compared to the existing design and the Powe Delay Product is 0.78 (*10^-18 j).
which is much lesser than any existing designs mentioned in the above as shown in
the figure 5.1.1.5.

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5.1.2 RESULTS FOR TMUL:
Ternary multiplier is designed using Tanner tool designed in the s-edit tool as
shown in the figure 5.1.2.1.

Fig 5.1.2.1: schematic design of TMUL

Ternary Multiplier is designed by 23-transistors using CNTFET’s based on

unary operators, TG’s and two voltage supplies (vdd, vdd/2). The maximum
propagation delay in this design takes place from the input “A” to the output “sum”.
This is referred as the critical path.

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Fig 5.1.2.2: test bench circuit for ternary multiplier

In this test bench circuit interconnections are done and the measuring devices are
connected externally to find the power, delay and internal noise in the circuit.
Temperature sweep is added to find the parameters with respect to the desire
temperature. Measure inverting delay component’s one is connect to the input side of
the test bench and another is connected to the output side. Print power is used to print
the power consumed by the circuit with respect to temperature as shown in the figure
5.1.2.2.

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Fig 5.1.2.3: transient analysis of the ternary multiplier

Transient analysis of the ternary multiplier is observed in w-edit tool to obtain

the two inputs and sum, carry, four print voltage components are used connect to the
output side of the test bench hence the “A”, “B”
“product” and “carry” are observed in the w-edit tool interface as shown in the
figure 5.1.2.3

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Fig 5.1.2.4: power results for ternary multiplier

To find the power, Print Power measuring device is added to the test bench and
when we run the simulation power values with respect to the different temperatures
were obtained because temperature sweep is included in the circuit. Average power
consumed at temp 0 is 7.772772e+001 watts and max and min are 1.344613e+001
and 0 respectively at time 1.10206e-008 for max power as shown in the figure 5.1.2.4.

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Fig 5.1.2.5: delay results for ternary multiplier

To find the delay, Measure inverting delay component is connect to the test
bench the simulated output waveforms are obtained with respect to the temperature
and the total delay in the design is 5.14ps. And the simulated result obtained is lesser
compared to the existing design and the Powe Delay Product is 0.21 (*10^-18 j).
which is much lesser than any existing designs mentioned in the above as shown in
the figure 5.1.2.5.

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5.3 RESULTS FOR PROCESS VARIATIONS:
During the producing technique of integrated circuits (ICs), errors in the
dimensions of transistors (oxide width, length,. .. ) referred to as technique versions
occur, which notably influences the robustness and conduct of nanoscale circuits.
This has a look at employs Monte Carlo analysis, a version that plays records with the
subsequent assumptions: a Gaussian distribution of ±5%, ±10%, and ±15% with
fluctuations at the three sigma degree and one hundred strolling simulations.

Fig 5.3.1: Voltage variations with T = 27 ◦C and F = 1 GHz

Figure 5.2.3.1 shows the voltage variation compared to existing THA and
TMUL of [13], [16], [17], [19], [24], [28], [29] regarding the energy consumption
PDP. These parameters used are temperature set with the value 27 ◦C, frequency
value at 1 GHz, and supply voltages varying from 0.8 V to 1 V.

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Fig 5.3.2: Temperature variation with Vdd = 0.9 V and F = 1 GHz:

(a) THAs, (b) TMULs

Figure 5.3.2 shows the temperature variation compared to existing THA and
TMUL of [13], [16], [17], [19], [24], [28], [29] regarding the energy consumption
PDP. The parameters are frequency value set at 1 GHz, power supply at 0.9 V, and
temperatures varying within the range 10 ◦C to 70 ◦C.

Figures 5.3.1 and 5.3.2 show that the proposed designs resulted in the lowest
PDP compared to other designs regarding voltage and temperature variations.

5.4 RESULTS FOR NOISE SIGNAL:

Noise indicators of excessive width and massive amplitude have an effect on
digital circuits. The noise sign with amplitude (Vn) and pulse width (Wn) proven in
Figure 5.4.1 is injected into the inputs of each THAs and TMULs. The Noise
Immunity Curve (NIC) defines how noisy inputs have an effect on all circuits. Every
factor sketched on the NIC curve has a noise width Wn and a noise amplitude Vn.
Over that value, an output mistakes could be generated. As a result, a circuit with a
better NIC way a circuit has greater noise tolerant [34]. The proposed THA and
TMUL display better noise immunity as compared to the alternative designs, as
proven in Fig 5.4.1.

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Fig 5.4.1: Noise signal

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CHAPTER 6
CONCLUSION
.

CONCLUSION
This project proposed novel 32 nm channel CNFET-based designs of eight
Unary Operators to layout a Ternary Half Adder with 36 transistors and a Ternary
Multiplier with 23 transistors. To obtain the objective, the layout system hired
specific strategies to lower the general strength intake withinside the circuit via way
of means of the use of unary operators, voltage resources Vdd and Vdd /2, and
transmission gates.

After simulating the proposed design the use of TANAR T-SPICE, the
proposed circuits performed a decrease PDP towards all the checkout circuits for
distinctive simulation parameters, PVT variations, and noise outcomes studies. In
addition, the proposed designs proved to have a better noise tolerance and better
robustness to technique variations.

This is aligned with the primary motive of this work to lessen battery
consumption, offer an energy-green implementation for low-electricity transportable
electronics and embedded devices

6.1 ADVANTAGES:
1. Better control over channel formation

2. Better threshold voltage

3. High electron mobility.

4. Minimising the delay 5. lower power consumption

6.2 APPLICATIONS:
1. Arithmetic circuits like adder, multiplier etc., are the most important
circuits in digital signal processing and many more applications.

2. Portable electronic gadgets such as cellular phones, personal digital

assistants, notebooks and phone.
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6.3 FUTURE SCOPE:
By using CNTFET’s we reduce the power consumption. By decreasing the
diameter of CNTFET we can reduce the total energy consumed in the circuit.

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nanotube and resistive random access memory based unbalanced ternary logic
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arithmetic circuits,’’ IEEE Access, vol. 8, pp. 104701–104717, 2020. [Online].
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4https://link.springer.com/article/10.1007%2Fs00034-019-01318-4
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24. S. Kim, S.-Y. Lee, S. Park, K. R. Kim, and S. Kang, ‘‘A logic synthesis
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ieee.org/document/7809029

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APPENDIX

A.INTRODUCTION OF TANNER TOOL

Tanner tool is a Spice Computer Analysis Programmed for Analogue

Integrated Circuits. Tanner tool consists of the following Engine machines.

1. S-EDIT (Schematic Edit)

2. T-EDIT (Simulation Edit)

3. W-EDIT (Waveform Edit)

Using these engine tools, spice program provides facility to the use to design & simulate
new ideas in Analogue Integrated Circuits before going to the time consuming & costly
process of chip fabrication.

A.1 S-EDIT (SCHEMATIC EDIT):

S-Edit is hierarchy of files, modules & pages. It introduces symbol & schematic modes.
S-Edit provides the facility of:
1. Beginning a design.

2. Viewing, drawing & editing of objects.

3. Design connectivity.

4. Properties, net lists & simulation.

5. Instance & browse schematic & symbol mode.

S-Edit has two viewing modes:

1. Schematic Mode: To create or view a schematic, we operate in schematic mode.

2. Symbol Mode: It represents symbol of a larger functional unit such as

operational amplifier.

To launch S-Edit, double-click on the S-Edit icon.

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The user interface consists of the elements shown below. Unless you explicitly retrieve a
setup file, the position, docking status and other display characteristics are saved with a design
and will be restored when the design is loaded as shown in figure A.1.1.

Fig A.1.1: Interface of the Tanner s-edit tool

PARTS OF THE USER INTERFACE

Title Bar
The title bar shows the name of the current cell and the view type (symbol, schematic,
etc.) shown in figure A.1.2

Menu Bar
The menu bar contains the S-Edit menu titles. The menu displayed may vary depending
on the view type that is active. See “Shortcuts for Cell and View Commands” on for the
various methods S-Edit provides for executing commands.

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Fig A.1.2: title bar of tanner s edit tool

Menu List Filtering

Most S-Edit menus and dialogs allow for filtering to speed the process of selecting
from a drop-down list. So, when you enter a character, S-Edit will jump to the first list item that
begins with that character. For example, typing g highlights the first list item beginning with
that letter and filters the display to show only items that begin with g. Typing a u after the g
highlights the first list item beginning with gu, and filters the display to show only items that
begin with gu, and so on. The search procedure is case-insensitive.

Toolbars
You can display or hide individual toolbars using the View > Toolbars command, or by
right-clicking in the toolbar region. Toolbars can be relocated and docked as you like. For
added convenience, S-Edit displays a tool tip when the cursor hovers over an icon.

Standard Toolbar
The Standard toolbar provides buttons for commonly used file and editing commands, as
well as operations specific to S-Edit such as “View Symbol” as shown in figure A.1.3.

Fig A.1.3: standard tool of s-edit tool

Draw Toolbar
The Draw toolbar provides tools used to create non-electrical objects, such as rectangles,
circles, and lines, for illustrating and documenting a design shown in figure A.1.4.

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Fig A.1.4: draw tool bar of s-edit

Segment Toolbar
The Segment toolbar provides tools with which you limit the degree of angular freedom
allowed when you are drawing wires as shown in fig A.1.5.

Fig A.1.5: segment toolbar of s-edit

Electrical Toolbar
The Electrical toolbar provides the tools used to create wires, nets, and ports, and to add
properties as shown in figure A.1.6.

Fig A.1.6: electrical toolbar of s-edit

SPICE Simulation Toolbar

The SPICE Simulation toolbar lets you extract connectivity, select and probe nets, launch
T-Spice and select evaluated properties as shown in figure A.1.7

Fig A.1.7: SPICE simulation Toolbar of s-edit

Locator Toolbar
The Locator toolbar displays the coordinates of the mouse cursor and allows you to quickly
change the units of measurement application-wide as shown in fig A.1.8.

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Fig A.1.8: locator toolbar of s-edit

Mouse Buttons Toolbar

The Mouse Buttons toolbar shows the current functions of the mouse buttons as shown in
figure A.1.9.

Fig A.1.9: mouse buttons toolbar of s-edit

Mouse buttons vary in function according to the tool that is active. The Shift, Ctrl and Alt
keys can further change the function. For two-button mice, the middle-button function is
accessed by clicking the left and right buttons at the same time, or by pressing Alt while
clicking the left mouse button.

Customizing Toolbars
You can add buttons for existing commands to existing S-Edit toolbars, add entirely new
toolbars, and add new buttons for entirely new commands to either new or existing toolbars. To
customize toolbars, right-click anywhere in the toolbar area and click on Customize in the
context-sensitive menu as shown in figure A.1.10.

Fig A.1.10: customised toolbar in s-edit

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This opens the Customize dialog, to the Toolbars tab. Note that in this dialog the
checkmarks control only whether or not a toolbar is displayed. The buttons apply only to the
toolbar that is highlighted, and will be applied even if a toolbar is not currently displayed as
shown in figure A.1.11.

Fig A.1.11: toolbars in s-edit

Reset returns an existing toolbar to the default display settings for aspects such as icon
size, tooltips, etc. – see “Menu and Toolbar Display Options” and its original button contents.

The New, Rename and Delete functions apply only to custom toolbars.

Adding a Command to a Toolbar:

Use the Commands tab to add a button for an existing command to any toolbar as shown
in fig A.1.12

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Fig A.1.12: adding command to a toolbar

1. Right-click in the toolbar area, select Customize and then the Commands tab.

2. Pick the desired command from the Categories list (or use All Commands for a
complete list of available commands), then simply click-and-drag the command from the right
column to the desired toolbar.

3. S-Edit will insert a button displaying the command text, or an icon if one is
already defined.

Adding a New Menu

1. You can also use the Commands tab to add a new menu category to the menu

2. In the Commands tab, scroll down to New Menu at the end of the Categories

3. Click-and-drag New Menu from the right column to the Menu bar in the interface
as shown in figure A.1.13.

Fig A.1.13: adding a new menu in s-edit

4. Right-click on the New Menu button you have just placed to open the control
menu, where you can rename it, then check Begin a Group to populate the menu with pull-
down commands.

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5. Select the new menu button in the interface to open the pull-down group, then
clickand-drag from the Commands tab to add the desired command(s). Make sure to drop the
commands within the group area as shown in fig A.1.14.

Fig A.1.14: print statement in s-edit tool

Adding a New Toolbar

1. Right-click in the toolbar area, select Customize and click on the New button.

2. Enter the desired name in the New Toolbar window and click OK to display

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Fig A.1.15: adding a new toolbar in s-edit

3.Note that although it has a name, the new toolbar is small and blank when first placed –
you may have to search a bit to find it as shown in fig 5.1.1.15.

Fig A.1.16: commands pane to new tool bar

4.If you have just added the toolbar, you can click-and-drag from the Commands pane to
add an existing command. Otherwise, right-click in the toolbar area, select Customize,
highlight a menu in the Categories pane then click-and-drag the desired command from the
Commands pane to your new toolbar as shown in fig A.1.16

Adding a New Command Button

There are two important requirements for adding a new command to S-Edit. You must
write and execute a TCL function to perform the desired command, and you must create a
custom button for the command that has the same name as the TCL function.

As long as the TCL function is loaded into S-Edit during the current editing session,
SEdit will run the function when you press the custom button to execute the operation. Lastly,
if you want a button to work in subsequent sessions, you will need to save it to an S-Edit start
up folder.

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Example: Adding a Button to Toggle Snap Grid Size
Please follow the steps in this example to learn how to add a new command button. In
this example we will add a toolbar with two new buttons; one that doubles the size of the
current snap grid and another that halves it.

1. Enter and execute each of these TCL functions separately in the S-Edit command
window. Note that they must be entered in one unbroken line:

proc Grid Double {} {setup schematic grid set -snap grid size [expr 2*[setup
schematic grid get -snap grid size]] -units iu} proc Grid Half {} {setup schematic grid set -snap
grid size

[expr .5*[setup schematic grid

get -snap grid size]] -units iu}

1. Create a new toolbar named “Custom Snap Grid” (see “Adding a New Toolbar”,
above).
2. If you have just added the toolbar you can click on the Commands tab, scroll
down to the bottom of the list and select Custom. If not, right-click in the toolbar area, select
Customize, highlight the “Custom Snap Grid” menu, click on the Commands tab, and scroll
down to the bottom of the list and select Custom.
3. Grab the text “Execute button text as Tcl” from the right pane and drag it to the
newly created toolbar as shown in figure A.1.17.

Fig A.1.17: Adding a Button to Toggle Snap Grid Size in s- edit

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4. For custom buttons you must replace “Execute button text as Tcl” with the name
of the TCL function you want to use. With the “Execute button text as Tcl” button highlighted,
right-click and enter the function name “GridDouble” in the name field.

Fig A.1.18: execute button text as tcl in s-edit

1. Repeat step 4 to add a second “Execute button text as Tcl” button to the toolbar.
Right-click on the new button and name it “Grid Half.”
2. With a schematic view open, launch Setup > Technology > Schematic Grids. Note
the current snap grid size, then press Grid Double and Grid Half a few times to confirm that the
buttons are working.
3. The scripts will execute for the duration of the current session. To execute them
each time S-Edit launches you must save the TCL commands, as Grid Half tcl and Grid
Double. tcl, in the S-Edit start up directory (typically C:/Documents and Settings//Application
Data/Tanner EDA/scripts /start up for Windows XP or C:/Users//AppData/Roaming/Tanner
EDA/ scripts/start up for Windows 7 as shown in figure A.1.18

Customizing a Command Button

Right-click on a toolbar button with the toolbar Customize dialog open to access the button
controls shown below in fig 5.1.1.19

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Fig A.1.19: customizing a command window

Reset:Returns standard buttons to their default shipping text and icon .

Delete:Deletes the selected button.

Name: Use this field to edit the button name when it is displayed as text, or to enter the
name of the TCL command to issue. The tooltip will not be affected.

Copy Button Image:Copies the selected button image.

Paste Button Image: Pastes the selected button image.

Reset Button Image: Resets all changes to the button image and text.

Edit button Image: Opens the Button Editor where you can perform.

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Fig A.1.20: change the colour of the button in s-edit

Change Button Image: Opens a small palette of clip art from which you can choose
an icon as shown in fig A.1.21

Fig A.1.21: change button image in s-edit

Default Style:Displays the default (image only) for the selected toolbar.

Text Only:Displays just the contents of the Name field for the selected.

Image and Text:Displays both the icon and the text from the Name field.

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Begin a Group:Inserts a fine line denoting a toolbar group to the left.
Adding or Editing a Keyboard:
Shortcut Customize > Keyboard lets you add or change shortcut key assignments for
menu commands.

Fig A.1.22: adding or editing a keyboard in s-edit

Category:Select the menu to which the command belongs.

Commands:Select the command for which you want to add or change a keyboard
shortcut. As shown in the fig A.1.22.

Key assignments:Displays existing key assignments. If blank, no shortcut is

assigned. It is possible to have more than one shortcut for a command. Highlight a command
and click on Remove to remove a shortcut. To restore the default settings click on Reset All.
Click on Assign to save a shortcut.

Press new shortcut key:Highlight a command in the Commands pane, then use
this field to enter the key(s) that will be the shortcut. You can use any combination of the Alt,
Shift and Ctrl keys with any of the character keys. S-Edit will warn you if your entry is already
in use. (Since this field interprets any key you press literally, you cannot delete a value in this
field—simply enter a different value.)

Click on Assign to save your shortcut.

Description:This display-only field shows the tooltip.

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Menu and Toolbar Display Options:
Customize > Options lets you set default display settings for menus and toolbars as
shown in fig A.1.23.

Fig A.1.23: menu and toolbar display options in s-edit

Always show full menus:

Menus and toolbars will automatically adjust based on how often you use commands so
that only the commands you use most often are displayed. If you prefer, you can choose the

Always show full menus option so that all commands are displayed on the menu. Show full
menus after a short delay:(Not operational.) Reset menu and toolbar
usagedata:
Deletes the record of all the commands used in S-Edit (for short menu display) and
restores the default set of visible commands to the menus and toolbars. However, explicit
changes you have made in the current or earlier sessions will remain.

Large icons:
Check this box to display large toolbar buttons.

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Show Screen tips on toolbars:
Check this box to display screen tips (also called “tooltips”) for the toolbar buttons. (A
tooltip is a brief reminder of the related command. It is displayed when your mouse hovers over
a toolbar button.)

Show shortcut keys in Screen tips:

Check this box to add shortcut keys to the tooltip display.

Menu animations:
You can choose from the list to add animation to the open menu operation.

Status Bar:
The Status Bar display varies with the type and number of objects selected and the tool in
use. You can use View > Status Bar to toggle display on and off.

Design Area:
The region in Tanner tools where you create, view and edit objects is called the Design
Area. The portion of the design area currently visible is called the Work Area. You can move
or resize design windows as you would in any other application window. Refer to “The Work
Area” on page 38 for further information as shown in fig A.1.24.

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Fig A.1.24: design area in s-edit

T-SPICE PRO CIRCUIT ANALYSIS:

An introduction to the integrated components of the T- Spice Pro circuit analysis

Schematic data files (.sdb):describes the circuits to be analyzed in graphical

form, for display and editing by S- Edit" Schematic Editor.

Simulation input files (.sp): describes the circuits to be analyzed in textual

form, for editing and simulation by T- Spice" Circuit Simulator.

Simulation output files (.out): containing the numerical results of the circuit
analyses, for manipulation and display by W- Edit" Waveform Viewer.

A.1.2 CIRCUIT SIMULATOR (T-SPICE):

T-Spice Pro’s waveform probing feature integrates S- Edit, T- Spice, and W- Edit to
allow individual points in a circuit to be specified and analyzed. A few analyses are described
below:
The heart of T-Spice operation is the input file (also known as the circuit description, the
net list & the input deck). This is a plain text file that contains the device statement &
simulation commands, drawn from the SPICE circuit description language with which T-Spice

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constructs a

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model of the circuit to be simulated. Input files can be created and modified with any text
editor. T-Spice is a tool used for simulation of the circuit. It provides the facility of
1. Design Simulation

2. Simulation Commands

3. Device Statements

4. User-Designed External Models

5. Small Signal & Noise Models

A.1.3 WAVEFORM EDIT:

The ability to visualize the complex numerical data resulting from VLSI circuit
simulation is critical to testing, understanding & improving these circuits. W-Edit is a
waveform viewer that provides ease of use, power & speed in a flexible environment
designed for graphical data representation.

The advantages of W Edit include:

1. Tight Integration with T-spice, Tanner EDA_s circuit level simulator. W-Edit
can chart data generated by T-spice directly, without modification of the output text data
files. The data can also be charted dynamically as it is produced during the simulation.
2. Charts can automatically configure for the type of data being presented.

3. A data is treated by W-Edit as a unit called a trace. Multiple traces from

different output files can be viewed simultaneously in single or several windows; traces can
be copied and moved between charts & windows. Trace arithmetic can be performed on
existed tracing to create new ones.
4. Chart views can be panned back & forth and zoomed in & out, including
specifying the exact X-Y coordinate range.
5. Properties of axes, traces, rides, charts, text &colours can be customized.
DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S

A.1.4 LAYOUT (L-EDIT):

It is a tool that represents the masks that are used to fabricate an integrated circuit. It
describes a layout design in terms of files, cells& mask primitives. On the layout level, the
component parameters are totally different from schematic level.

So it provide user to analyze

the response of the circuit before forwarding it to
the time consuming &costly process of
fabrication. There are rules for designing layout
diagram of a schematic circuit using which user
can compare the output response with the expected
one.
 DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S

By
KOTHURI SRAVANI

TITLE: DESIGN OF LOW AREA LOW POWER COMBINATIONAL

CIRCUITS USING CNTFET’S

Submission date:01-December-2022 11:55 PM (UTC+05:30)

Submission ID: 1368431478
File name: M.tech.docx (1899.14K)
Word count: 10525
Character count: 65256
 DESIGN OF LOW AREA LOW POWER COMBINATIONAL CIRCUITS USING CNTFET’S

ORIGINALITY
REPORT

19 %
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2
https://jglobal.jst.go.jp/en/detail?JGLOBAL_ID=202002259857958152
Publication 2%
3
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5 %
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1%
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 DESIGN OF LOW AREA LOW POWER COMBINATIONAL
CIRCUITS USING CNTFET’S
KOTHURI SRAVANI, M.PRIYANKA
1 2

M. tech, Dept. of ECE, Eluru College of Engineering and Technology, ELURU, AP

1

Assistant Professor, Dept. of ECE, Eluru College of Engineering and Technology, ELURU, AP
2

ABSTRACT: Embedded systems, Internet of Things (IoT) gadgets, and portable electronic devices
have all become highly popular in recent years. The majority of them run on batteries. The major goal
of this project is to reduce battery usage while also providing an energy-efficient solution for low-
power portable electronics and embedded systems. Using 32nm CNFET’s, the project proposes
ternary combinational circuits. This study employs a power supply that provides two voltage supplies
(Vdd and Vdd/2) and so reduces the overall energy consumption in the circuit to reduce energy
consumption by exploiting the unary operator of ternary systems. This proposed design show the
improvements in the 25% in transistor count and 98% in energy consumption reduction’s.
Keywords: CNTFET’s, Unary operators, Ternary combinational circuit
INTRODUCTION:
In terms of circuit design, it is important to note that MVL methods are not germane only to
implementations that encode logic values as more than two discrete voltage or current signals, but that
MVL methods are also important as models for the initial design of logic circuits whether they are
implemented with binary or MVL signal levels. The issue of whether the ultimate realization of a logic
circuit is binary or not depends on the underlying technology and is independent of the use of MVL.
As an example, complementary metal oxide semiconductor (CMOS)-based logic circuitry is generally
implemented in binary logic since technology issues make binary the best choice. The point here is
that this is merely an issue of the encoding of logic values and, as the following circuit examples
indicate, the use of MVL concepts in the design stage often leads to circuits that exhibit better
characteristics than would be obtained if only binary-valued logic were utilized. There are two kinds of
MVL circuits based on MOS technology, namely the current-mode MVL circuits and the voltage
mode MVL circuits. Voltage-mode MVL circuits have been achieved in multi threshold CMOS
design. The carbon nanotube (CNT) FET (CNTFET) is a promising alternative to the bulk silicon
transistor for low-power and high- performance design due to its ballistic transport and low OFF-
current properties. A multi threshold CMOS design relies on body effects using different bias voltages
to the base or the bulk terminal of the transistors. In a CNTFET, the threshold voltage of the transistor
is determined by the diameter of the CNT. Therefore, a multi threshold design can be accomplished by
employing CNTs with different diameters (and, therefore, chirality) in the CNTFETs. A resistive-load
CNTFET-based ternary logic design. However, in this configuration, large OFF- chip resistors (of at
least 100 MΩ values) are needed due to the current requirement of the CNTFETs. The MVL relies on
and eliminates the large resistors by employing active load with p-type CNTFETs in the ternary logic
gates.
TERNARY HALH ADDER(THA):
A THA is a combinational digital circuit that accepts two1-bit ternary inputs and provides two outputs
SUM and CARRY. A new technique was introduced for voltage mode MVL using CNFETs with
resistive pull-ups. A sum gate was designed to perform ternary addition on two inputs IN1 andIN2 to
provide the sum output was carried out using CNFET switch pull-up resistors. and ternary full adder,
and multiplier designs and analysis are presented as examples of the application of these ternary gates
design technique. For the arithmetic circuit design, a modified ternary logic circuit design technique is
used to speed up and reduce power consumption of the circuits. Themodified ternary logic design uses
both ternary logic gates and binary logic gates based on the previous ternary logic design structures to
take advantage of the two logic design styles’ merits. Figure 1.1 shows
the schematic diagram and the symbol of sum operator. SUM output for different combination of two
1- bitternary inputs can be obtained

Fig 1.1: schematic diagram of ternary half adder

TERNARY MULTIPLIER(TMUL):
Integrated Circuit (IC) technologies, implemented using binary logic systems have been dominating
the hardware for many decades. From the Moore’s Law, it can be understood that we cannot shrink the
transistor sizes perpetually. Hence, have to come up with new technologies i.e. beyond CMOS
technologies. since, in submicron and nano range, the CMOS devices have reliability issues. It is also
noted that for a particular circuit, ternary logic system, theoretically requires lesser chip area, reduced
interconnects and it has faster operating speeds when compared to the radix-2 system. Carbon
Nanotube Field Effect Transistor (CNFET) has been widely used for the implementation of the ternary
logic circuits. CNFET uses a single carbon nanotube (CNT) or an array of carbon nanotubes which are
analogous to bulk silicon in MOSFETs. The single-walled CNT behaves as conducting or semi-
conducting path/channel depending on the chirality vector, which is given by the atom arrangement
angle along the tube. Using CMOS devices, ternary logic circuits it has been shown that the
performance of CMOS- based circuit designs can be improved by adding MVL blocks to binary
designs. A 2-bit ternary ALU design is designed, where negative voltage levels were used to indicate
the third state. Various intriguing designs for single trit addition and single trit multiplication. A
ternary logic system is a multi valued logic (MVL) system with three logic levels which correspond to
logic 0, logic1 and logic 2. In a balanced or ternary neutral system, the three logic levels are identified
as -1, 0 and 1.
Fig 2: Block diagram of TMUL

In fig 1.2 block diagram of the ternary multiplier with unary operators as shown above unary
operators are the one input and the one output logic devices out will be fixed in this work 5 unary
operators are used.
 EXISTING SYSTEM:
MULTI-TRIT MULTIPLIER:
A single-trit multiplier can be realized with 26 CNTFETs. The select signal B for carry and product,
requires 9 CNTFETs while 8 CNTFETs are required for the internal logic of the two multiplexers. The
complete circuit. The overall CNTFET requirement is therefore 26. the existed multiplier is based on
the classical Wallace tree structure. The multiplier includes ternary half-adders and two custom full-
adder configurations, named F A1 and F A2 which are modifications of the traditional ternary full
adder.

fig 2.1: single-trit multiplier CNTFET-based

realization

In fig2.1 represents the single trit multiplier based on the CNTFET realisation using 26- transistors
which lesser compared to the previous works and it do have low PDP and transistor count

TERNARY HALF ADDER:

Table 2.1: Truth for ternary half adder

In the fig 2.2 shows ternary half adder and table2 shows truth table of the ternary half adder is shown
A ternary multiplexer requiring only 15 CNTFETs can be realized utilizing unary operators for the
seleced signal. The truth table for a ternary multiplexer is given where
S is the select signal and D0, D1 and D2 are the data lines. where SP is the output of a positive ternary
inverter and SN is the output of a negative ternary inverter. It is worth noting that the select signals SP
and SN are the positive and negative ternary inverters, each of which requires
The main drawback of the existing model is due use of single voltage source the heat is increased
within the circuit called JOULE POWER effect. In proposed model two voltages are used to reduce the
JOULE POWER effect.
PROPOSED UNARY OPERATORS
This project uses CNTFET transistors and unbalanced ternary logic system (Low: 0, Middle: 1, High:
2) that is equivalent to (0, Vdd /2, Vdd ). The circuit’s total power consumption is divided into two
types: static power and dynamic power. This project uses a power supply that generates two voltage
supplies Vdd and Vdd /2 to remove these two transistors and accordingly decrease the overall energy
consumption in the circuit. A ternary multiplexer requiring only 15 CNTFETs can be realized utilizing
unary operators for the select signal. The truth table for a ternary multiplexer is given. where S is the
select signal and D0, D1 and D2 are the data lines. where SP is the output of a positive ternary inverter
and SN is the output of a negative ternary inverter. It is worth noting that the select signals SP and SN
are the positive and negative ternary inverters, each of which requires 2 CNTFETs.

Fig 3.1: Proposed unary operators

Table 3.1 CNTFET operation

In fig 3.1 and table 3.1shows proposed five unary operators with D1 and D2 diameter and CNTFET
operation for D1 and D2 is shown
Table 32: Truth table for unary operators
In table 4.1.2 the unary operators shown which shows the on and off conditions of the transistors.

PROPOSED TERNARY HALF ADDER:

Half adders and 1-trit multipliers are employed in bigger structures like arithmetic processing units and
are critical components in VLSI circuits. As a result, increasing the efficiency of these circuits can
increase the performance of bigger processing units.
Two input variables and two output variables comprise a half-adder circuit. The cumulative
number is used as an input variable, while sum and carry are used as output variables. The author
devised a novel method that did not require the use of a decoder in order to solve the problem. THA's
design the use of a decoder is no longer necessary. Unary functions are created. The computation of
the unary functions transistor-level circuits The ternary output from these routines is provided by low-
power encoders. A one-trit THA combines two ternary inputs and produces two ternary values (Sum
and Carry).
Based on unary operators, TGs, and two voltage supplies (Vdd, Vdd /2), this research
presents a THA with 36 CNFETs. From the input "A" to the output "Sum," the maximum
propagation delay exists in this. When the input "A" moves from 1 to 2, "B" = 2, and the Sum
changes from 0 to 1, this route is

Fig 4.1: proposed THA design

In fig 4.1 the ternary half adder design for the proposed design is shown with red dotted line called
Critical path

Table 4.2: truth table for ternary half adder

In table 4.2 the ternary half adder is given shows the on and off conditions the transistors input “A”
changes from 1 to 2, “B” = 2, and the sum changes from 0 to 1
TERNARY MULTIPLIER
 Fig 4.2: Proposed ternary multiplier

Fig 4.2 represents the proposed ternary multiplier with 23 transistors with lower power and low PDP
compared to the existing work
The base multiplier is based on the classic Wallace approach. Uses 3: 1 multiplexer and ternary unary
operator logic. This article describes the design of a low power single trit multiplier Describes the use
of CNFETs. The
simulation data for this design shows that the power delay product (PDP) is significantly lower With a
new design of single trit multiplier. 1-trit TMUL multiplies two ternary inputs and two outputs. 3
values (Product & Carry).
This proposed TMUL with 23 CNFETs. Use unary operator, TG, and two power supplies (Vdd, Vdd /
2) In the figure 4.2.2 The red dotted line is the critical path between the input `` A`` and output ``
Product``. Occurs when `` A`` Change state from 1 to 2, "B" = 1 and product It changes from 1 to 2.
Two cascade TGs that create more propagation delay.

SIMULA
TION
RESULT
S FOR
THA
Ternary half adder is designed using Tanner tool designed in the s-edit tool as shown in the figure
5.1.1.1.

Fig 5.1.1.1: schematic diagram of ternary half adder

Ternary Half adder is designed by 36-transistors using CNTFET’s based on unary operators, TG’s
and two voltage supplies (vdd, vdd/2). The maximum propagation delay in this design takes place
from the input “A” to the output “sum”. This is referred as the critical path.
 Fig 5.1.1.2: test bench circuit for ternary half adder

In this test bench circuit interconnections are done and the measuring devices are connected externally
to find the power, delay and internal noise in the circuit.
Temperature sweep is added to find the parameters with respect to the desire temperature. Measure
inverting delay component’s one is connect to the input side of the test bench and another is connected
to the output side. Print power is used to print the power consumed by the circuit with respect to
temperature as shown in the figure 5.1.1.2.

Fig 5.1.1.3: transient analysis of the ternary half adder

Transient analysis of the ternary half adder is observed in w-edit tool to obtain the two inputs and sum,
carry, four print voltage components are used connect to the output side of the test bench hence the
“A”, “B”
“sum” and “carry” are observed in the w-edit tool interface as shown in the figure 5.1.1.3
 Fig 5.1.1.4: power results of ternary half adder
To find the power, Print Power measuring device is added to the test bench and when we run the
simulation power values with respect to the different temperatures were obtained because temperature
sweep is included in the circuit. Average power consumed at temp 0 is 1.393995e+001 watts and max
and min are 2.411675e+001 and 0 respectively at time 1.1e-008 for max power as shown in the figure
5.1.1.4.
 Fig 5.1.1.5: delay results for ternary half adder

To find the delay, Measure inverting delay component is connect to the test bench the simulated output
waveforms are obtained with respect to the temperature and the total delay in the design is 8.7ps. And
the simulated result obtained is lesser compared to the existing design and the Powe Delay Product is
0.78 (*10^-18 j). which is much lesser than any existing designs mentioned in the above as shown in
the figure 5.1.1.5.
RESULTS FOR TMUL:
Ternary multiplier is designed using Tanner tool designed in the s-edit tool as shown in the figure
5.1.2.1.
 Fig 5.1.2.1: schematic design of TMUL

Ternary Multiplier is designed by 23-transistors using CNTFET’s based on unary operators, TG’s and
two voltage supplies (vdd, vdd/2). The maximum propagation delay in this design takes place from the
input “A” to the output “sum”. This is referred as the critical path.
 Fig 5.1.2.2: test bench circuit for ternary multiplier

In this test bench circuit interconnections are done and the measuring devices are connected externally
to find the power, delay and internal noise in the circuit. Temperature sweep is added to find the
parameters with respect to the desire temperature. Measure inverting delay component’s one is connect
to the input side of the test bench and another is connected to the output side. Print power is used to
print the power consumed by the circuit with respect to temperature as shown in the figure 5.1.2.2.

Fig 5.1.2.3: transient analysis of the ternary multiplier

 Transient analysis of the ternary multiplier is observed in w-edit tool to obtain the two inputs and
sum, carry, four print voltage components are used connect to the output side of the test bench hence
the “A”, “B”
“product” and “carry” are observed in the w-edit tool interface as shown in the figure 5.1.2.3

Fig 5.1.2.4: power results for ternary multiplier

To find the power, Print Power measuring device is added to the test bench and when we run the
simulation power values with respect to the different temperatures were obtained because temperature
sweep is included in the circuit. Average power consumed at temp 0 is 7.772772e+001 watts and max
and min are 1.344613e+001 and 0 respectively at time 1.10206e-008 for max power as shown in the
figure 5.1.2.4.
An UGC-CARE Approved Group-I Journal www.ijearst.co.in

Fig 5.1.2.5: delay results for ternary multiplier

To find the delay, Measure inverting delay component is connect to the test bench the simulated
output waveforms are obtained with respect to the temperature and the total delay in the design is
5.14ps. And the simulated result obtained is lesser compared to the existing design and the Powe
Delay Product is 0.21 (*10^-18 j). which is much lesser than any existing designs mentioned in the
above as shown in the figure

CONCLUSION AND FUTURE SCOPE:

This project proposed novel 32 nm channel CNFET-based designs of eight Unary Operators to layout
a Ternary Half Adder with 36 transistors and a Ternary
Multiplier with 23 transistors. To obtain the objective, the layout system hired specific strategies to
lower the general strength intake withinside the circuit via way of means of the use of unary operators,
voltage resources Vdd and Vdd /2, and transmission gates.
After simulating the proposed design the use of TANAR T-SPICE, the proposed circuits performed a
decrease PDP towards all the checkout circuits for distinctive simulation parameters, PVT variations,
and noise outcomes studies. In addition, the proposed designs proved to have a better noise tolerance
and better robustness to technique variations.
This is aligned with the primary motive of this work to lessen battery consumption, offer an energy-
green implementation for low-electricity transportable electronics and embedded devices By using
CNTFET’s we reduce the power consumption. By decreasing the diameter of CNTFET we can reduce
the total energy consumed in the circuit.
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RESEARCH SCIENCE AND TECHNOLOGY
Volume.04, IssueNo.01, August-2022, Pages: 735-750
 An UGC-CARE Approved Group-I Journal www.ijearst.co.in

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Copyright @ 2022ijearst. All rights reserved.

INTERNATIONAL JOURNAL OF ENGINEERING IN ADVANCED
RESEARCH SCIENCE AND TECHNOLOGY
Volume.04, IssueNo.01, August-2022, Pages: 735-750
An UGC-CARE Approved Group-I Journal www.ijearst.co.in

Copyright @ 2022ijearst. All rights reserved.

INTERNATIONAL JOURNAL OF ENGINEERING IN ADVANCED
RESEARCH SCIENCE AND TECHNOLOGY
Volume.04, IssueNo.01, August-2022, Pages: 735-750