Application Note 29

October 1988

Some Thoughts on DC/DC Converters

Jim Williams and Brian Huffman

INTRODUCTION
Many systems require that the primary source of DC power In the worst case, the noise precludes analog circuitry
be converted to other voltages. Battery driven circuitry is from achieving desired performance levels (for further
an obvious candidate. The 6V or 12V cell in a laptop com- discussion see Appendix A, “The 5V to ±15V Converter
puter must be converted to different potentials needed for — A Special Case”). The 5V to ±15V DC/DC conversion
memory, disc drives, display and operating logic. In theory, requirement is ubiquitous, and presents a good starting
AC line powered systems should not need DC/DC converters point for a study of DC/DC converters.
because the implied power transformer can be equipped
with multiple secondaries. In practice, economics, noise 5V TO ±15V CONVERTER CIRCUITS
requirements, supply bus distribution problems and other
constraints often make DC/DC conversion preferable. A Low Noise 5V to ±15V Converter
common example is logic dominated, 5V powered systems
Figure 1’s design supplies a ±15V output from a 5V input.
utilizing ±15V driven analog components.
Wideband output noise measures 200 microvolts peak-
The range of applications for DC/DC converters is large, to-peak, a 100× reduction over typical designs. Efficiency
with many variations. Interest in converters is commensu- at 250mA output is 60%, about 5% to 10% lower than
rately quite high. Increased use of single supply powered conventional types. The circuit achieves its low noise
systems, stiffening performance requirements and battery performance by minimizing high speed harmonic content
operation have increased converter usage. in the power switching stage. This forces the efficiency
Historically, efficiency and size have received heavy em- trade-off noted, but the penalty is small compared to the
phasis. In fact, these parameters can be significant, but benefit.
often are of secondary importance. A possible reason The 74C14 based 30kHz oscillator is divided into a 15kHz
behind the continued and overwhelming attention to size 2-phase clock by the 74C74 flip-flop. The 74C02 gates and
and efficiency in converters proves surprising. Simply 10k-0.001µF delays condition this 2-phase clock into non-
put, these parameters are (within limits) relatively easy to overlapping, 2-phase drive at the emitters of Q1 and Q2
achieve! Size and efficiency advantages have their place, (Figure 2, Traces A and B, respectively). These transistors
but other system-oriented problems also need treatment. provide level shifting to drive emitter followers Q3-Q4. The
Low quiescent current, wide ranges of allowable inputs, Q3-Q4 emitters see 100Ω-0.003µF filters, slowing drive
substantial reductions in wideband output noise and cost to output MOSFETs Q5-Q6. The filter’s effects appear at
effectiveness are important issues. One very important the gates of Q5 and Q6 (Traces C and D, respectively). Q5
converter class, the 5V to ±15V type, stresses size and and Q6 are source followers, instead of the conventional
efficiency with little emphasis towards parameters such common source connection. This limits transformer rise
as output noise. This is particularly significant because time to the gate terminals filtered slew rate, resulting in
wideband output noise is a frequently encountered problem
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered
with this type of converter. In the best case, the output noise trademarks of Linear Technology Corporation. All other trademarks are the
mandates careful board layout and grounding schemes. property of their respective owners.

an29f

AN29-1
Application Note 29
22k
1N5817

+ +
100 10

74C14 +V POINT 3 2
Q
CK 74C74 “A” LT1054 1N5817
D (SEE TEXT) D3
Q BOOST 5 8 1N5817
OUTPUT 5VIN
0.001
≈17VDC
BOOST + (4.5V TO 5.5V)
47 D2
CLK-NON 10k 1N5817
OVERLAP
GENERATOR 0.001
74C02
4
5V TURBO BURST

10k D 6 MUR 120

Q5
(ALL)
74C02 0.001
S
1 7 470
74C14
74C14 2 8 0.001
+15
LT1086
+ + OUT
74C14 Q3 100µF 124* 10µF
74C14 3 9
φ1 Q1
100Ω 100
L1
+
10µF 1.37k* OUT
0.003 D1 OUTPUT
150k 1k COMMON
1N5817 S 100µF
15kHz, 5µs 10k +
Q6
NON-OVERLAP
DIRVERS-
D –15
LEVEL SHIFTS EDGE LT337A
SHAPING 5V OUT
φ2 100Ω 1µF
Q2 249*
Q4
+
= ±15 COMMON
100
10k = +5 GROUND 10µF 2.74k*
0.003
+
150k 1k –4VDC * = 1% FILM RESISTOR
FET = MTP3055E-MOTOROLA
AN29 F01
PNP = 2N3906
22µF NPN = 2N3904
+
L1 = PULSE ENGINEERING, INC. #PE-61592
= FERRITE BEAD, FERRONICS #21-110J

Figure 1. Low Noise 5V to ±15V Converter

put. The 470Ω-0.001µF damper in L1’s output maintains

A = 20V/DIV loading during switching, aiding low noise performance.
B = 20V/DIV The ferrite beads in the gate leads eliminate parasitic RF
oscillations associated with follower configurations.
C = 20V/DIV

D = 20V/DIV The source follower configuration eases controlling L1’s

edge rise times, but complicates gate biasing. Special
E = 10V/DIV
provisions are required to get the MOSFETs fully turned
F = 10V/DIV on and off. Source follower connected Q5 and Q6 require
AN29 F02
voltage overdrive at the gates to saturate. The 5V primary
HORIZ = 20µs/DIV
supply cannot provide the specified 10V gate — channel
Figure 2. 5V to ±15V Low Noise Converter Waveforms bias required for saturation. Similarly, the gates must be
pulled well below ground to turn the MOSFETs off. This
well controlled waveforms at the sources of Q5 and Q6 is so because L1’s behavior pulls the sources negative
(Traces E and F, respectively). L1 sees complimentary, when the devices turn off. Turn-off bias is bootstrapped
slew limited drive, eliminating the high speed harmonics from the negative side of Q6’s source waveform. D1 and
normally associated with this type converter. L1’s output the 22µF capacitor produce a –4V potential for Q3 and Q4
is rectified, filtered and regulated to obtain the final out- to pull down to. Turn-on bias is generated by a 2-stage
an29f

AN29-2
 Application Note 29
boost loop. The 5V supply is fed via D3 to the LT®1054 less than 30µV of output noise. This is almost 7× lower
switched capacitor voltage converter (switched capacitor than the previous circuit and approaches a 1000× improve-
voltage converters are discussed in Appendix B, “Switched ment over conventional designs. The trade off is efficiency
Capacitor Voltage Converters — How They Work”). The and complexity.
LT1054 configuration, set up as a voltage doubler, initially
A1 is set up as a 16kHz Wein bridge oscillator. The single
provides about 9V boost to point “A” at turn-on. When
power supply requires biasing to prevent A1’s output from
the converter starts running L1 produces output (“Turbo
saturating at the ground rail. This bias is established by
Boost” on schematic) at windings 4-6 which is rectified by
returning the undriven end of the Wein network to a DC
D2, raising the LT1054’s input voltage. This further raises
potential derived from the LT1009 reference. A1’s output
point “A” to the 17V potential noted on the schematic.
is a pure sine wave (Figure 5, Trace A) biased off ground.
These internally generated voltages allow Q5 and Q6 to A1’s gain must be controlled to maintain sine wave output.
receive proper drive, minimizing losses despite their source A2 does this by comparing A1’s rectified and filtered posi-
follower connection. Figure 3, an AC-coupled trace of the tive output peaks with an LT1009 derived DC reference.
15V converter output, shows 200µVP-P noise at full power A2’s output, biasing Q1, servo controls A1’s gain. The
(250mA output). The –15V output shows nearly identi- 0.22µF capacitor frequency compensates the loop, and the
cal characteristics. Switching artifacts are comparable in thermally mated diodes minimize errors due to rectifier
amplitude to the linear regulators noise. Further reduction temperature drift. These provisions fix A1’s AC and DC
in switching based noise is possible by slowing Q5 and output terms against supply and temperature changes.
Q6 rise times. This, however, necessitates reducing clock
A1’s output is AC coupled to A3. The 2k –820Ω divider
rate and increasing non-overlap time to maintain available
re-biases the sine wave, centering it inside A3’s input
output power and efficiency. The arrangement shown
common mode range even with supply shifts. A3 drives a
represents a favorable compromise between output noise,
power stage, Q2-Q5. The stages common emitter outputs
available output power, and efficiency.
and biasing permit 1VRMS (3VP-P) transformer drive, even
at VSUPPLY = 4.5V. At full converter output loading the
stage delivers 3 ampere peaks but the waveform is clean
(Trace  B), with low distortion (Trace C). The 330µF coupling
capacitor strips DC and L3 sees pure AC. Feedback to A3 is
A = 100µV/DIV
(AC-COUPLED)
taken at the Q4-Q5 collectors. The 0.1µF unit at this point
suppresses local oscillations. L3’s secondary RC network
adds additional high frequency damping.
Without control of quiescent current the power stage
HORIZ = 5µs/DIV AN29 F03
will encounter thermal runaway and destroy itself. A4
measures DC output current across Q5’s emitter resistor
Figure 3. Output Noise of the Low Noise 5V to ±15V Converter.
Appendix H Shows a Modern IC Low Noise Regulator and servo controls Q6 to fix quiescent current. A divided
portion of the LT1009 reference sets the servo point at
Ultralow Noise 5V to ±15V Converter A4’s negative input and the 0.33µF feedback capacitor
stabilizes the loop.
Residual switching components and regulator noise set
Figure 1’s performance limits. Analog circuitry operating L3’s rectified and filtered outputs are applied to regulators
at the very highest levels of resolution and sensitivity may designed for low noise. A5 and A7 amplify the LT1021’s
require the lowest possible converter noise. Figure 4’s filtered 10V output up to 15V. A6 and A8 provide the –15V
converter uses sine wave transformer drive to reduce output. The LT1021 and amplifiers give better noise perfor-
harmonics to negligible levels. The sine wave transformer mance than three terminal regulators. The Zener-resistor
drive combines with special output regulators to produce network clips overvoltages due to start-up transients.

an29f

AN29-3
 5VIN
(4.5V TO 5.5V)

AN29-4
+
0.01 22µF L4
1k POWER 100µH 4.99k*
16kHz AMP
OSCILLATOR
+
1N4001 22µF
220Ω –
1k A5 A7
8 430Ω 68Ω 10k*
+ 0.01 5V 1/2 LT1013 LT1010
+ Q4
A1 MJE2955 + L1
1k 47µF 220Ω 8 47µF 25µH
LT1006 1µF 2k Q2
10k 50Ω 1µF
8 2N2219 5k
+
– + 0.1 330µF† 15VOUT
0.22 OUT
+
680Ω A3
820Ω L3 LT1021 0.1
Application Note 29

LT1006
+
270Ω 0.1 8 5 330Ω
IN 10V
– Q3 50Ω OUT
(SELECTED
VALUE— 2N2905 19V COMMON
1k* 4 0.005 * *
SEE TEXT) 430Ω Q5 UNREG
MJE3055
Q1 100Ω +
1 3 * * 220µF 330Ω 10k*
2k 0.22 Q6 1N4001
200k 0.1Ω
750Ω* 1k 10k
220µF
–19V + 1N5260B
0.22 UNREG
10k*
– +
A4 –15VOUT
1/2 LT1013 1/2 LT1013 IQ 4 L2
1k CONTROL – 47µF
A2 + 5V – 25µH
LOOP A6 A8
+
OSCILLATOR LT1009 0.33
10k 10k 620Ω 1/2 LT1013 LT1010
STAB. LOOP 2.5
THERMALLY + 0.1
MATED
3.1k 20k
AN29 F04

L1, L2 = PULSE ENGINEERING, INC. #PE-92100

L3 = PULSE ENGINEERING, INC. #PE-65064
L4 = PULSE ENGINEERING, INC. #PE-92108
= 1N4148
*
= 1N4934
UNMARKED NPN = 2N3904
* = 1% METAL FILM RESISTOR
† = THF337K006P1G

= +5 GROUND
= ±15 COMMON

Figure 4. Ultralow Noise Sine Wave Drive 5V to ±15V Converter

an29f
 Application Note 29
The leftmost logic inverter produces a 20kHz clock (Trace  A,
A = 2V/DIV
Figure 7) which feeds a logic network composed of addi-
tional inverters, diodes and the 74C90 decade counter. The
B = 2V/DIV counter output (Trace B) combines with the logic network
to present alternately phased clock bursts (Traces  C and D)
C = 1% DISTORTION
to the base resistors of Q1 and Q2. When φ1 (Trace B)
is unclocked it resides in its high state, biasing Q2 and
B = 20µV/DIV
Q4 on. Q4’s collector effectively grounds the “bottom” of
L1 (Trace H). During this interval φ2 (Trace A) puts clock
HORIZ = 50µs/DIV AN29 F05
bursts into Q1’s base resistor. If the –15V output is too
Figure 5. Waveforms for the Sine Wave Driven Converter. low servo comparator C1A’s output (Trace E) is high, and
Note that Output Noise (Trace D) is Only 30µVP-P Q1’s base can receive pulsed bias. If the converse is true
the comparator will be low, and the bias gated away via
L1 and L2 combine with their respective output capaci-
Q1’s base diode. When Q1 is able to bias, Q3 switches,
tors to aid low noise characteristics. These inductors are
resulting in negative going flyback events at the “top” of
outside the feedback loop, but their low copper resistance
L1 (Trace G). These events are rectified and filtered to
does not significantly degrade regulation. Trace D, the 15V
produce the –15V output. C1A regulates by controlling
output at full load, shows less than 30µV (2ppm) of noise.
the number of clock pulses that switch the Q1-Q3 pair.
The most significant trade-off in this design is efficiency.
The LT1004 serves as a reference. Trace J, the AC-coupled
The sine wave transformer drive forces substantial power
–15V output, shows the effect of C1A’s regulating action.
loss. At full output (75mA), efficiency is only 30%.
The output stays within a small error window set by C1A’s
Before use, the circuit should be trimmed for lowest switched control loop. As input voltage and loading con-
distortion (typically 1%) in the sine wave delivered to ditions change C1A adjusts the number of clock pulses
L3. This trim is made by selecting the indicated value at allowed to bias Q1-Q3, maintaining loop control.
A1’s negative input. The 270Ω value shown is nominal,
When the φ1 and φ2 signals reverse state the operating
with a typical variance of ±25%. The sine wave’s 16kHz
sequence reverses. Q3’s collector (Trace G) is pulled high
frequency is a compromise between the op amps avail-
with Q2-Q4 switching controlled by C1B’s servo action.
able gain bandwidth, magnetics size, audible noise, and
Operating waveforms are similar to the previous case.
minimization of wideband harmonics.
Trace  F is C1B’s output, Trace H is Q4’s collector (L1’s “bot-
Single Inductor 5V to ±15V Converter tom”) and Trace I is the AC-coupled 15V output. Although
the two regulating loops share the same inductor they
Simplicity and economy are another dimension in 5V to operate independently, and asymmetrical output loading is
±15V conversion. The transformer in these converters is not deleterious. The inductor sees irregularly spaced shots
usually the most expensive component. Figure 6’s unusual of current (Trace K), but is unaffected by its multiplexed
drive scheme allows a single, 2-terminal inductor to replace operation. Clamp diodes prevent reverse biasing of Q3
the usual transformer at significant cost savings. Trade- and Q4 during transient conditions. The circuit provides
offs include loss of galvanic isolation between input and ±25mA of regulated power at 60% efficiency.
output and lower power output. Additionally, the regulation
technique employed causes about 50mV of clock related Low Quiescent Current 5V to ±15V Converter
output ripple.
A final area in 5V to ±15V converter design is reduction
The circuit functions by periodically and alternately allowing of quiescent current. Typical units pull 100mA to 150mA
each end of the inductor to flyback. The resultant positive of quiescent current, unacceptable in many low power
and negative peaks are rectified and filtered. Regulation systems.
is obtained by controlling the number of flyback events
during the respective output’s flyback interval.
an29f

AN29-5
Application Note 29
150k*

5V
12.4k*
+ 300Ω
C1A 10k 5V
HP5082-2810
1/2 LT1018
–
2k
32k 100Ω
Q3
φ2 2N5023
10k 4.7k
Q1 –15VOUT
2N3906 +
1000pF 100
5
L1
145µH
74C90 10k
÷10
5V

12 φ1 4.7k
Q2
15VOUT
2N3904 +
100Ω 100
Q4
2N3507
5V 2k 137k*

300Ω +
10k C1B
1/2 LT1018
– 12.4k*

1k AN29 F06
5V
LT1004
= 1N4148 1.2V
* = 1% METAL FILM RESISTOR

= 74C14

L1 = PULSE ENGINEERING, INC. # PE-92105

Figure 6. Single Inductor 5V to ±15V Regulated Converter

Figure 8’s design supplies ±15V outputs at 100mA while

consuming only 10mA quiescent current. The LT1070
A = 5V/DIV switching regulator (for a complete description of this
device, see Appendix C, “Physiology of the LT1070”) drives
B = 5V/DIV
L1 in flyback mode. A damper network clamps excessive
C = 10V/DIV flyback voltages. Flyback events at L1’s secondary are
D = 10V/DIV half-wave rectified and filtered, producing positive and
E = 10V/DIV
negative outputs across the 47µF capacitors. The positive
F = 10V/DIV
G = 20V/DIV
16V output is regulated by a simple loop. Comparator
H = 20V/DIV
C1A balances a sample of the positive output with a 2.5V
reference obtained from the LT1020. When the 16V out-
I = 0.05V/DIV (AC-COUPLED) put (Trace A, Figure 9) is too low, C1A switches (Trace B)
J = 0.05V/DIV (AC-COUPLED)
high, turning off the 4N46 opto-isolator. Q1 goes off, and
K = 1A/DIV
AN29 F07
the LT1070’s control pin (VC) pulls high (Trace C). This
HORIZ = 100µs/DIV
causes full duty cycle 40kHz switching at the VSW pin
Figure 7. Waveforms for the Single Inductor, Dual-Output, (Trace D). The resultant energy into L1 forces the 16V
Regulated Converter output to ramp quickly positive, turning off C1A’s output.
an29f

AN29-6
 Application Note 29
5VIN
(4.5V TO 5.5V) 16V PRE-REG

1N4148 1.2M* – 9 3
L1 GND VIN
C1A
1.2k 1 9 + 216k* 1/2 LT1017
8
–1N OUT
2 15VOUT
2W 0.47
47µF + LT1070 0.001µF
100mA
8 2.5M*
5 11
COMP FB +
+ PNP
2.5V COMP 500k* 10µF
MUR120 47µF 20M
+IN REF OUT NPN
3 7
7 4 6
0.001µF +
1N4148 10µF
VIN VSW 82k 10k 3M* 500k* 100k
5V
NC FB LT1070 4N46
–15VOUT
VC GND 100mA
Q2
VN2222
10k 470k TO TO 16V
–16V UNREG
REF OUT PRE-REG
Q1 10k 0.002
2N3906 470k 1.5k
390k
TO 3.2M –
–16V UNREG
OPTIONAL C1B
L1 = PULSE ENGINEERING, INC. # PE-61592 1/2 LT1017
(SEE TEXT)
* = 1% FILM RESISTOR UPDATE TO 1.5M +
= +5 GROUND Burst Mode® regulators –15V
can achieve lower IQ 5.6M
= ±15 COMMON
47k

AN29 F08

Figure 8. Low IQ, Isolated 5V to ±15V Converter

A = 100mV/DIV
tends to follow the regulated –16V line, but regulation
(AC-COUPLED ON is poor. The LT1020’s auxiliary onboard comparator is
16VDC LEVEL)
compensated to function as an op amp by the RC damper
B = 20V/DIV
at Pin 5. This amplifier linearly regulates the –16V line.
C = 2V/DIV MOSFET Q2 provides low dropout current boost, sourcing
the –15V output. The –15V output is stabilized with the
D = 20V/DIV op amp by comparing it with the 2.5V reference via the
HORIZ = 5ms/DIV AN29 F09
500k-3M current summing resistors. 1000pF capacitors
frequency compensate each regulating loop. This converter
Figure 9. Waveforms for the Low IQ 5V to ±15V Converter
functions well, providing ±15V outputs at 100mA with
The 20M value combined with the 4N46’s slow response only 10mA quiescent current. Figure 10 plots efficiency
(note the delay between C1A going high and the VC pin versus a conventional design over a range of loads. For
rise) gives about 40mV of hysteresis. The LT1070’s on- high loads results are comparable, but the low quiescent
off duty cycle is load dependent, saving significant power circuit is superior at lower current.
when the converter is lightly loaded. This characteristic A possible problem with this circuit is related to the poor
is largely responsible for the 10mA quiescent current. regulation of the –16V line. If the positive output is lightly
The opto-isolator preserves the converters input-output loaded L1’s magnetic flux is low. Heavy negative output
isolation. The LT1020, a low quiescent current regulator loading under this condition results in the –16V line falling
with low dropout, further regulates the 16V line, giving below its output regulators dropout value. Specifically, with
the 15V output. The linear regulation eliminates the 40mV no load on the 15V output only 20mA is available from
ripple and improves transient response. The –16V output the –15V output. The full 100mA is only available from
an29f

AN29-7
Application Note 29
100 output (the VC pin) uses an RC damper for stable loop
90 compensation.
80
70
LOW QUIESCENT This circuit works well but pulls 9mA of quiescent current.
CURRENT DESIGN
If battery capacity is limited by size or weight this may be
EFFICIENCY (%)

60
50 too high. How can this figure be reduced while retaining
40
CONVENTIONAL
DESIGN
high current performance?
30
VIN
20 6V L1*
50µH
10
0
0 10 20 30 40 50 60 70 80 90 100 MUR8100
VIN VOUT
OUTPUT CURRENT (mA) VSW
+ 12V
AN29 F10
LT1070 470µF 10.7k

Figure 10. Efficiency vs Load for the Low IQ Converter FB

GND VC
1.24k
the –15V output when the 15V output is supplying more 1k
than 8mA. This restriction is often acceptable, but some +
AN29 F11

situations may not tolerate it. The optional connection in 1µF *PULSE ENGINEERING, INC
#PE-51515
Figure 8 (shown in dashed lines) corrects the difficulty.
C1B detects the onset of –16V line decay. When this oc- Figure 11. 6V to 12V, 2 Amp Converter with 9mA Quiescent Current
curs its output pulls low, loading the 16V line to correct
the problem. The biasing values given permit correction A solution is suggested by considering an auxiliary VC pin
before the negative linear regulator drops out. function. If the VC pin is pulled within 150mV of ground the
IC shuts down, pulling only 50 microamperes. Figure 12’s
MICROPOWER QUIESCENT CURRENT CONVERTERS special loop exploits this feature, reducing quiescent cur-
rent to only 150 microamperes. The technique shown is
Many battery-powered applications require very wide particularly significant, with broad implication in battery
ranges of power supply output current. Normal conditions powered systems. It is easily applied to a wide variety of
require currents in the ampere range, while standby or DC/DC converters, meeting an acknowledged need across
“sleep” modes draw only microamperes. A typical laptop a wide spectrum of applications.
computer may draw 1 to 2 amperes running while need-
ing only a few hundred microamps for memory when Figure 12’s signal flow is similar to Figure 11, but additional
turned off. In theory, any DC/DC converter designed circuitry appears between the feedback divider and the VC
for loop stability under no-load conditions will work. In pin. The LT1070’s internal feedback amplifier and reference
practice, a converter’s relatively large quiescent current are not used. Figure 13 shows operating waveforms under
may cause unacceptable battery drain during low output no-load conditions. The 12V output (Trace A) ramps down
current intervals. over a period of seconds. During this time comparator
A1’s output (Trace B) is low, as are the 74C04 paralleled
Figure 11 shows a typical flyback based converter. In this inverters. This pulls the VC pin (Trace C) low, putting the
case the 6V battery is converted to a 12V output by the IC in its 50µA shutdown mode. The VSW pin (Trace D) is
inductive flyback voltage produced each time the LT1070’s high, and no inductor current flows. When the 12V output
VSW pin is internally switched to ground (for commentary drops about 20mV, A1 triggers and the inverters go high,
on inductor selection in flyback converters see Appendix  D, pulling the VC pin up and turning on the regulator. The
“Inductor Selection for Flyback Converters”). An internal VSW pin pulses the inductor at the 40kHz clock rate, caus-
40kHz clock produces a flyback event every 25µs. The ing the output to abruptly rise. This action trips A1 low,
energy in this event is controlled by the IC’s internal er- forcing the VC pin back into shutdown. This “bang-bang”
ror amplifier, which acts to force the feedback (FB) pin to control loop keeps the 12V output within the 20mV ramp
a 1.23V reference. The error amplifiers high impedance
an29f

AN29-8
 Application Note 29
–
6VIN A2 “LOW BATT”
(4.5V TO 8V) 1/2 LT1017
3.6M* +
+
47µF L1 1.2M*
50µH MUR405
12VOUT
+ C1 R1 R7
VSW
2700µF 1M* 100k

LT1070 FB NC C3
1500pF

VC GND
R2
120k*

6V

R6 – UPDATE
200Ω A1 Micropower regulators using
R3
+
1/2 LT1017
2M Burst Mode operation are available
C2 +
47µF

10pF**
R4
R5
10k
180k
6V
LT1004
** = OPTIONAL. SEE TEXT
1.2V
= 1N4148 AN29 F12

* = 1% METAL FILM RESISTOR

= 74C04

L1 = PULSE ENGINEERING, INC. # PE-51515

Figure 12. 6V to 12V, 2 Amp Converter with 150µA Quiescent Current

hysteresis window set by R3-R4. Diode clamps prevent A = 0.02V/DIV

(AC-COUPLED)
VC pin overdrive. Note that the loop oscillation period of
4 to 5 seconds means the R6-C2 time constant at VC is B = 5V/DIV
not a significant term. Because the LT1070 spends almost
all of the time in shutdown, very little quiescent current
C = 2V/DIV
(150µA) is drawn.
D = 10V/DIV
Figure 14 shows the same waveforms with the load in- AN29 F13
HORIZ = 1s/DIV
creased to 3mA. Loop oscillation frequency increases to
keep up with the loads sink current demand. Now, the VC Figure 13. Low IQ Converter Waveforms with No Load
pin waveform (Trace C) begins to take on a filtered ap- (Traces B and D Retouched for Clarity)
pearance. This is due to R6-C2’s 10ms time constant. If

an29f

AN29-9
Application Note 29
the load continues to increase, loop oscillation frequency A = 0.02V/DIV
(AC-COUPLED)
will also increase. The R6-C2 time constant, however,
is fixed. Beyond some frequency, R6-C2 must average B = 5V/DIV

loop oscillations to DC. Figure 15 shows the same circuit

points at 1 ampere loading. Note that the VC pin is at DC, C = 2V/DIV
and repetition rate has increased to the LT1070’s 40kHz
clock frequency. Figure 16 plots what is occurring, with D = 10V/DIV

a pleasant surprise. As output current rises, loop oscilla- HORIZ = 20ms/DIV AN29 F14

tion frequency also rises until about 500Hz. At this point

Figure 14. Low IQ Converter Waveforms at Light Loading
the R6-C2 time constant filters the VC pin to DC and the
LT1070 transitions into “normal” operation. With the VC
pin at DC it is convenient to think of A1 and the invert-
ers as a linear error amplifier with a closed-loop gain set A = 0.02V/DIV
by the R1-R2 feedback divider. In fact, A1 is still duty
B = 5V/DIV
cycle modulating, but at a rate far above R6-C2’s break
frequency. The phase error contributed by C1 (which was
selected for low loop frequency at low output currents) is C = 2V/DIV

dominated by the R6-C2 roll off and the R7-C3 lead into D = 10V/DIV
A1. The loop is stable and responds linearly for all loads HORIZ = 20µs/DIV AN29 F15

beyond 80mA. In this high current region the LT1070 is

desirably “fooled” into behaving like Figure 11’s circuit. Figure 15. Low IQ Converter Waveforms at 1 Amp Loading
A formal stability analysis for this circuit is quite complex,
but some simplifications lend insight into loop operation.
550
At 100µA loading (120kΩ) C1 and the load form a decay 500
LINEAR REGION

time constant exceeding 300 seconds. This is orders of 450

EXTENDS TO
2.5A
magnitude larger than R7-C3, R6-C2, or the LT1070’s 400
LOOP FREQUENCY (Hz)

40kHz commutation rate. As a result, C1 dominates the 350

loop. Wideband A1 sees phase shifted feedback, and very 300

low frequency oscillations similar to Figure 13’s occur1. 250

IQ = 150µA
200
Although C1’s decay time constant is long, its charge 150
0.2Hz

time constant is short because the circuit has low sourc- 100
ing impedance. This accounts for the ramp nature of the 50
oscillations. 0
0 20 40 60 80 100

Increased loading reduces the C1 load decay time con- OUTPUT (mA)

stant. Figure 16’s plot reflects this. As loading increases,

AN29 F16

the loop oscillates at a higher frequency due to C1’s de- Figure 16. Figure 12’s Loop Frequency vs Output Current.
creased decay time. When the load impedance becomes Note Linear Loop Operation Above 80mA
low enough C1’s decay time constant ceases to dominate 1Some layouts may require substantial trace area to A1’s inputs. In such
the loop. This point is almost entirely determined by R6 cases the optional 10pF capacitor shown ensures clean transitions at A1’s
and C2. Once R6 and C2 “take over” as the dominant time output.
constant the loop begins to behave like a linear system. 2“Zero Compensation” for all you technosnobs out there.

In this region (e.g. above about 75mA, per Figure 16) the
LT1070 runs continuously at its 40kHz rate. Now, the R7-
C3 time constant becomes significant, performing as a
simple feedback lead2 to smooth output response. There is
an29f

AN29-10
 Application Note 29
constant decay3 (“rattling” is perhaps more appropriate)
A = 10V/DIV is visible as Trace B approaches steady state between the
4th and 5th vertical divisions.
A2 functions as a simple low-battery detector, pulling low
B = 0.1V/DIV when VIN drops below 4.8V.
(AC-COUPLED)
Figure 18 plots efficiency versus output current. High
HORIZ = 5ms/DIV AN29 F17
power efficiency is similar to standard converters. Low
power efficiency is somewhat better, although poor in
Figure 17. Load Transient Response for Figure 12’s
Low IQ Regulator the lowest ranges. This is not particularly bothersome,
as power loss is very small.
100 This loop provides a controlled, conditional instability
90 instead of the more usually desirable (and often elusive)
80
unconditional stability. This deliberately introduced char-
70 TYPICAL OPERATING
REGION acteristic lowers converter quiescent current by a factor of
EFFICIENCY (%)

60
60 without sacrificing high power performance. Although
50
15mA demonstrated in a boost converter, it is readily exportable
40
30
3mA to other configurations. Figure 19a’s step-down (buck
20
650µA TYPICAL STANDBY
mode) configuration uses the same basic loop with almost
10
IQ = 150µA REGION no component changes. P-channel MOSFET Q1 is driven
0 from the LT1072 (a low power version of the LT1070) to
0 0.5 1 1.5 2 2.5
convert 12V to a 5V output. Q2 and Q3 provide current
OUTPUT CURRENT (A)
AN29 F18
limiting, while Q4 supplies turn off drive to Q1. the lower
output voltage mandates slightly different hysteresis bias-
Figure 18. Efficiency vs Output Current for Figure 12.
Standby Efficiency is Poor, But Power Loss Approaches ing than Figure 12, accounting for the 1MΩ value at the
Battery Self Discharge comparators positive input. In other respects the loop and
its performance are identical. Figure 19b uses the loop in
a fundamental trade-off in the selection of the R7-C3 lead a transformer based multi-output converter. Note that the
network values. When the converter is running in its linear floating secondaries allow a –12V output to be obtained
region they must dominate the DC hysteresis deliberately with a positive voltage regulator.
generated by R3-R4. As such, they have been chosen for
the best compromise between output ripple at high load Low Quiescent Current Micropower 1.5V to 5V
and loop transient response. Converter
Despite the complex dynamics transient response is quite Figure 20 extends our study of low quiescent current con-
good. Figure 17 shows performance for a step from no verters into the low voltage, micropower domain. In some
load to 1 ampere. When Trace A goes high a 1 ampere load circumstances, due to space or reliability considerations, it
appears across the output (Trace B). Initially, the output is preferable to operate circuitry from a single 1.5V cell. This
sags almost 150mV due to slow loop response time (the eliminates almost all ICs as design candidates. Although
R6-C2 pair delay VC pin response). When the LT1070 comes it is possible to design circuitry which runs directly from
on (signaled by the 40kHz “fuzz” at the bottom extreme a single cell (see LTC® Application Note 15, “Circuitry For
of Trace B) response is reasonably quick and surprisingly Single Cell Operation”) a DC/DC converter permits using
well behaved considering circuit dynamics. The multi-time higher voltage ICs. Figure 20’s design converts a single
3Once again, “multi-pole settling” for those who adore jargon.

an29f

AN29-11
Application Note 29
Q1 L1
12VIN 0.4Ω IRF-9531 100µH
(8V TO 16V) 5VOUT
+
100Ω 1k MUR405 2700µF 1500pF
Q4
Q2 2N3904
1M 1M* 100k
2N3906

+
10µF VIN VSW 340k*

LT1072 FB NC

VC GND

2k
Q3
2N3904
12VIN

–
1N4148
200Ω 10k
1/2 LT1017
+ + 10k 470k
47µF 12VIN
1N4148

10pF** LT1004
1N4148 1.2V

AN29 F19a

L1 = PULSE ENGINEERING, INC. # PE-92108

** = OPTIONAL. SEE TEXT UPDATE
* = 1% FILM RESISTOR Burst Mode regulators
can achieve lower IQ
= 74C04

Figure 19a. The Low Quiescent Current Loop Applied to a Buck Converter

1.5V cell to a 5V output with only 125µA quiescent current. outputs (Trace C), forcing energy into L1. The paralleled
Oscillator C1A’s output is a 2kHz square wave (Trace D, outputs minimize saturation losses. L1’s flyback pulses,
Figure 21). The configuration is conventional, except that rectified and stored in the 47µF capacitor, form the circuits
the biasing accommodates the narrow common mode DC output. C1B on-off modulates C2 at whatever duty
range dictated by the 1.5V supply. To maintain low power, cycle is required to maintain the circuits 5V output. The
C1A’s integrating capacitor is small, with only 50mV of LT1004 is the reference, with the resistor divider at C1B’s
swing. The parallel connected sides of C2 drive L1. When positive input setting the output voltage. Schottky clamping
the 5V output (Trace A) coasts down far enough C1B of C2’s outputs prevents negative going overdrives due to
goes low (Trace B), pulling both C2 positive inputs close parasitic L1 behavior.
to ground. C1A’s clock now appears at the paralleled C2

an29f

AN29-12
 Application Note 29
MUR120
LT1086 12V
L1 7 + +
• 470µF 1.2k 10µF
12VIN 8 11k

22µF 9
+
MUR120
LT1086
4 10 1.2k
• + +
470µF 10µF
• 11k
2 11
2k –12V
2W 0.2µF MBR360 VOUT
5V
3 5 + C1 1A
• 2700µF
L1
•
1 6
MUR120 R3 R1 R7
1M 1M* 10k

VIN VSW 74C04 (5)

C3
LT1071 FB NC 12VIN 0.005

GND VC R6 –
200Ω A1 R2
1/2 LT1017 453k*
+ C2 +
47µF

10pF**

R4 R5
1N4148 1N4148 10k 180k
12VIN
LT1004
L1 = PULSE ENGINEERING, INC. # PE-65108 1.2
* = 1% FILM RESISTOR AN29 F19b
** = OPTIONAL. SEE TEXT

Figure 19b. Multi-Output, Transformer Coupled Low Quiescent Current Converter

The 1.2V LT1004 reference biasing is bootstrapped to the requiring more battery power. Decrease in battery voltage
5V output, permitting circuit operation down to 1.1V. A produces similar behavior. Figure 22 plots available output
10M bleed to supply ensures start-up. The 1M resistors current versus battery voltage. Predictably, the highest
divide down the 1.2V reference, keeping C1B inside com- power is available with a fresh cell (e.g., 1.5V to 1.6V),
mon mode limits. C1B’s positive feedback RC pair sets although regulation is maintained down to 1.15V for 250µA
about 100mV hysteresis and the 22pF unit suppresses loading. The plot shows that the test circuit continued to
high frequency oscillation. regulate below this point, but this cannot be relied on in
The micropower comparators and very low duty cycles at practice (LT1017 VMIN = 1.15V). The low supply voltage
makes saturation and other losses in this circuit difficult
light load minimize quiescent current. The 125µA figure
to control. As such, efficiency is about 50%.
noted is quite close to the LT1017’s steady-state currents.
As load increases the duty cycle rises to meet the demand,

an29f

AN29-13
Application Note 29
VIN
HP5082-2810 5VOUT
(1.1V TO 2V)
NC L1
4 3 0.001
3.9M
4.3M*
+
– NC 47µF 10M
5 2 +
150pF C1A 1.5M 240k – 22pF
C1B
1/2 LT1017 6 1 1/2 LT1017
+ C2B
150k 1/2 LT1017 – 360k
+ 619k*
3.9M 2M 1M*
1.5V
1M* 10M
470k
VIN
LT1004
1.2V
10M 390k
* = 1% METAL FILM RESISTOR 1.5V
PNP = 2N3906
NPN = 2N3904 –
L1 = TRIAD # SP-29 C2A
1/2 LT1017
+ HP-5082-2810

1N4148

HP5082-2810
+ 0.001
2.2µF

4 1 620k + 10M 47k

OPTIONAL FOR
NEGATIVE 22pF C1B
OUTPUT 1.5V –
(SEE TEXT) 5

C2B 5.1M 1.2M* 10k

6 3
VIN
47µF LT1004
+
C2A 1.2V
TO 390kΩ
OF C2B
AN29 F20

Figure 20. 800µA Output 1.5V to 5V Converter

850
800 IQ = 125µA
OUTPUT (µA) AVAILABLE AT VOUT = 5V

750
700
650 VOUT = 5V
600 EFFICIENCY ≈ 50%
A = 100mV/DIV 550
(AC-COUPLED ON 500
5VDC LEVEL) 450
400
B = 2V/DIV 350
300
250
200
C = 2V/DIV 150 LT1017
100 GUARANTEED MINIMUM
50 OPERATING VOLTAGE
D = 2V/DIV 0
0 1.05 1.15 1.25 1.35 1.45 1.55
AN29 F21
HORIZ = 5ms/DIV INPUT VOLTAGE (V)
AN29 F22

Figure 21. Waveforms for Low Power 1.5V to 5V Converter Figure 22. Output Current Capability vs Input Voltage for Figure 20
an29f

AN29-14
 Application Note 29
The optional connection in Figure 20 (shown in dashed at high power. If lowest quiescent current is necessary the
lines) takes advantage of the transformers floating second- technique detailed back in Figure 12 is applicable.
ary to furnish a –5V output. Drive circuitry is identical, but
The circuit is essentially a flyback regulator, similar to
C1B is rearranged as a current summing comparator. The
Figure 11. The LT1070’s low saturation losses and ease
LT1004’s bootstrapped positive bias is supplied by L1’s
of use permit high power operation and design simplic-
primary flyback spikes.
ity. Unfortunately, this device has a 3V minimum supply
200mA Output 1.5V to 5V Converter requirement. Bootstrapping its supply pin from the 5V
output is possible, but requires some form of start-up
Although useful, the preceding circuit is limited to low mechanism. Dual comparator C1 and the transistors form
power operation. Some 1.5V powered systems (survival a start-up loop. When power is applied C1A oscillates
2-way radios, remote, transducer fed data acquisition (Trace A, Figure 24) at 5kHz. Q1 biases, driving Q2’s base
systems, etc.) require much more power. Figure 23’s hard. Q2’s collector (Trace B) pumps L1, causing voltage
design supplies a 5V output with 200mA capacity. Some step-up flyback events. These events are rectified and
sacrifice in quiescent current is made in this circuit. This is stored in the 500µF capacitor, producing the circuit’s DC
predicated on the assumption that it operates continuously output. C1B is set up so it (Trace C) goes low when circuit
22
+
1.5VIN
L1 220µF
25µH
+ 1N5823
5VOUT
Q2 +
VIN VSW 500µF
2N3507
LT1070 3.74k*
FB
VC GND
665Ω* OPTIONAL IF
VSUPPLY CAN EXCEED 1.7V
1k 1.5VIN
+ +V
6.8µF 10k
47k
1.5VIN 1k
2Ω
1N4148
10k 100Ω Q1
2N2907 75k
TO
1.5V LT1004
0.01 C1B “+”
1.2V
– INPUT
100k
1k
C1A
1/2 LT1018
+
AN29 F23
68k 200k
1.5VIN 576Ω*
–
HP5082-2810 UPDATE
C1B
1/2 LT1018 LT1172 can be used
100k
39k +
1.5VIN
in place of LT1070
47k
L1 = PULSE ENGINEERING, INC. # PE-92100
* = 1% METAL FILM RESISTOR

Figure 23. 200mA Output 1.5V to 5V Converter

an29f

AN29-15
Application Note 29
output crosses about 4.5V. When this occurs C1A’s integra- 200mA. Start-up slope decreases, but starting still occurs.
tion capacitor is pulled low, stopping it from oscillating. The abrupt slope increase (6th vertical division) is due to
Under these conditions Q2 can no longer drive L1, but the overlapping operation of the start-up loop and the LT1070.
LT1070 can. This behavior is observable at the LT1070’s
Figure 27 plots input-output characteristics for the circuit.
VSW pin (the junction of L1, Q2’s collector and the LT1070),
Note that the circuit will start into all loads with VBATTERY =
Trace D. When the start-up circuit goes off, the LT1070 VIN
1.2V. Start-up is possible down to 1.0V at reduced loads.
pin has adequate supply voltage and it begins operation.
Once the circuit has started, the plot shows it will drive full
This occurs at the 4th vertical division of the photograph.
200mA loads down to VBATTERY = 1.0V. Reduced drive is
There is some overlap between start-up loop turn-off and possible down to VBATTERY = 0.6V (a very dead battery)!
LT1070 turn-on, but it has no detrimental effect. Once the Figures 28 and 29, dynamic XY crossplot versions of
circuit is running it functions similarly to Figure 11. Figure 27, are taken at 20 and 200 milliamperes, respec-
The start-up loop must be carefully designed to function tively. Figure 30 graphs efficiency at two supply voltages
over a wide range of loads and battery voltages. Start-up over a range of output currents. Performance is attrac-
currents exceed 1 ampere, necessitating attention to Q2’s tive, although at lower currents circuit quiescent power
saturation and drive characteristics. The worst case is a degrades efficiency. Fixed junction saturation losses are
nearly depleted battery and heavy output loading. Figure 25 responsible for lower overall efficiency at the lower supply
shows circuit output starting into a 100mA load at VBATTERY voltage. Figure 31 shows quiescent current increasing as
= 1.2V. The sequence is clean, and the LT1070 takes over at supply decays. Longer inductor current charge intervals
the appropriate point. In Figure 26, loading is increased to are necessary to compensate the decreased supply voltage.

A = 5V/DIV

B = 10V/DIV

C = 2V/DIV VERT = 1V/DIV

D = 1V/DIV
(AC-COUPLED ON
5VDC LEVEL)
AN29 F26
HORIZ = 2ms/DIV AN29 F24
HORIZ = 2ms/DIV

Figure 24. High Power 1.5V to 5V Converter Start-Up Sequence Figure 26. High Power 1.5V to 5V Converter Turn-On Into a
200mA Load at VBATT = 1.2V
MINIMUM INPUT VOLTAGE TO MAINTAIN VOUT = 5V

1.5
1.4
1.3
1.2
1.1 START
1.0
VERT = 1V/DIV 0.9
0.8 RUN
0.7
0.6
0.5
0.4
AN29 F25
HORIZ = 2ms/DIV 0.3
0.2
0.1
Figure 25. High Power 1.5V to 5V Converter Turn-On Into a 0
100mA Load at VBATT = 1.2V 0 20 40 60 80 100 120 140 160 180 200
OUTPUT CURRENT (mA) AN29 F27

Figure 27. Input-Output Data for Figure 23

an29f

AN29-16
 Application Note 29
100
VOUT = 5V
90
80
VERT = OUTPUT 70 VIN = 1.5V
= 1V/DIV

EFFICIENCY (%)
60
VIN = 1.2V
50
40

AN29 F28 30
HORIZ = INPUT = 0.15V/DIV
20
10
Figure 28. Input-Output XY Characteristics of the
1.5V to 5V Converter at 20mA Loading 0
0 20 40 60 80 100 120 140 160 180 200
OUTPUT CURRENT (mA)
AN29 F30

Figure 30. Efficiency vs Operating Point for Figure 23

1.50

VERT = OUTPUT 1.45

= 1V/DIV 1.40

SUPPLY VOLTAGE (V)

1.35
1.30
1.25
AN29 F29
HORIZ = INPUT = 0.15V/DIV
1.20
1.15
Figure 29. Input-Output XY Characteristics of the
1.5V to 5V Converter at 200mA Loading 1.10
1.05
1.00
50 55 60 65 70 75 80
HIGH EFFICIENCY CONVERTERS QUIESCENT CURRENT (mA)
AN29 F31

High Efficiency 12V to 5V Converter Figure 31. IQ vs Supply Voltage for Figure 23
Efficiency is sometimes a prime concern in DC/DC con-
verter design (see Appendix E, “Optimizing Converters Figure 33 shows the operating waveforms. Q5 drives the
for Efficiency”). In particular, small portable computers synchronous rectifier, Q2, when the VSW pin (Trace A) is
frequently use a 12V primary supply which must be con- turned “off”. Q2 is turned off through D1 and D2 when the
verted down to 5V. A 12V battery is attractive because it VSW pin is “on”. To turn on Q1, the gate (Trace B) must
offers long life when all trade-offs and sources of loss are be driven above the input voltage. This is accomplished
considered. Figure 32 achieves 90% efficiency. This circuit by bootstrapping the capacitor, C1, off the drain of Q2
can be recognized as a positive buck converter. Transistor (Trace  C). C1 charges up through D1 when Q2 is turned on.
Q1 serves as the pass element. The catch diode is replaced When Q2 is turned off, Q3 is able to conduct, providing a
with a synchronous rectifier, Q2, for improved efficiency. path for C1 to turn Q1 on. During this time, current flows
The input supply is nominally 12V but can vary from 9.5V through Q1 (Trace D) through the inductor (Trace E) and
to 14.5V. Power losses are minimized by utilizing low into the load. To turn Q1 off, the VSW pin must be “off”.
source-to-drain resistance, 0.028Ω, NMOS transistors Q5 is now able to turn on Q4 and the gate of Q1 is pulled
for the catch diode and pass element. The inductor, Pulse low through D3 and the 50Ω resistor. This resistor is used
Engineering PE-92210K, is made from a low loss core to reduce the voltage noise generated by fast switching
material which squeezes a little more efficiency out of the characteristics of Q1. When Q2 is conducting (Trace F),
circuit. Also, keeping the current sense threshold voltage Q1 must be off. The efficiency will be decreased if both
low minimizes the power lost in the current limit circuit. transistors are conducting at the same time. The 220Ω
an29f

AN29-17
Application Note 29
12VIN
(9.5V TO 14.5V)
47pF 0.018Ω

50k 100Ω
Q7** 1N4148
1k 2N3906
Q8**
2N3906 5k 5k
R1
619Ω Q5 Q3 C1
2N2222 2N2222 0.1µF
+ D1 D3
220µF VIN 1N4148 1N4148
VSW Q1
E1
P50N05E
LT1072CN8
L1
E2 FB 100µH VOUT
GND VC 5V
50Ω
5A
1N4148 3.01k*
+
1000µF
Q6 100Ω Q9 1k*
2N2222 2N2222 D2
1k 220Ω 220Ω
1N4148
LT1004-2.5 Q4 Q2
9k 3.5k 1µF VN2222 P50N05E
AN29 F32

L1 = PULSE ENGINEERING, INC. # PE-92210K

* = 1% FILM RESISTORS
** = USE MATCHING OF 20mV AT 200µA
= P50N05E IRFZ44
(MOTOROLA) (INTERNATIONAL RECTIFIER)

Figure 32. 90% Efficiency Positive Buck Converter with Synchronous Switch

A = 20V/DIV 100

B = 20V/DIV SYNC SWITCHES

90

C = 20V/DIV
EFFICIENCY (%)

PMOS AND DIODES

80 (SEE FIGURE 42)
D = 2A/DIV

70 PNP AND DIODES

E = 2A/DIV (SEE FIGURE 42)

F = 2A/DIV 60

AN29 F33
HORIZ = 10µs/DIV
50
0 1 2 3 4 5
Figure 33. Waveforms for 90% Efficiency Buck Converter ILOAD (A)
AN29 F34

resistors and D2 are used to minimize the overlap of the

switch cycles. Figure 34 shows the efficiency versus load Figure 34. Efficiency vs Load for Figure 32. The Synchronous
Switches Give Higher Efficiency than Simple FET or Bipolar
plot for the circuit as shown. The other plots are for non- Transistors and Diodes
synchronously switched buck regulators (see indicated
Figures). 0.018Ω sense resistor exceeds 124mV, Q8 is turned on.
Short circuit protection is provided by Q6 through Q9. The LT1072’s VSW pin goes off when the VC pin is pulled
A 200µA current source is generated from an LT1004, below 0.9V. This occurs when Q8 forces Q9 to saturate.
Q6 and the 9k resistor. This current flows through R1 An RC damper suppresses line transients that might
and generates a threshold voltage of 124mV for the prematurely turn on Q8.
comparator, Q7 and Q8. When the voltage drop across the

an29f

AN29-18
 Application Note 29
MBR1060

4
+ 5VOUT
L1 1000µF 100mA TO 1A
• (SEE TEXT)
5

MBR1060
12VIN
680Ω 0.47µF 2k 8 3
• +
22µF

MBR360 0.1µF 1
• 6 3.40k*
VIN
+ VSW 1k
100µF LT1070
FB
GND VC

1k 1.07k*

1µF
AN29 F35

L1 = PULSE ENGINEERING, INC. # PE-65066

* = 1% FILM RESISTORS
MBR1060 = MOTOROLA

Figure 35. High Efficiency Flux Sensed Isolated Converter

High Efficiency, Flux Sensed Isolated Converter

Figure 35’s 75% efficiency is not as good as the previous A = 10V/DIV
circuit, but it has a fully floating output. This circuit uses
a bifilar wound flux sensing secondary to provide isolated
B = 10V/DIV
voltage feedback. In operation the LT1070’s VSW pin (Trace
A, Figure 36) pulses L1’s primary, producing identical wave- C = 10V/DIV
forms at the floating power and flux sensing secondaries
(Traces B and C). Feedback occurs from the flux sense
AN29 F36
HORIZ = 5µs/DIV

winding via the diode and capacitive filter. The 1k resis- Figure 36. Waveforms for Flux Sensed Converter
tor provides a bleed current, while the 3.4k-1.07k divider
sets output voltage. The diode partially compensates the This ringing is not deleterious to circuit operation, and the
diode in the power output winding, resulting in an overall network is optional. Below about 10% loading non-ideal
temperature coefficient of about 100ppm/°C. The oversize transformer behavior introduces significant regulation er-
diode aids efficiency, although significant improvement ror. Regulation stays within ±100mV from 10% to 100%
(e.g., 5% to 10%) is possible if synchronous rectification of output rating, with excursion exceeding 900mV at no
is employed, as in Figure 32. The primary damper network load. Figure 37’s circuit trades away isolation for tight
is unremarkable, although the 2k-0.1µF network has been regulation with no output loading restrictions. Efficiency
added to suppress excessive ringing at low output current. is the same.

an29f

AN29-19
Application Note 29
MBR1060
5VOUT
12VIN
L1 1A
680Ω 0.47µF 8 4
• +
1000µF

MBR360 1 • 5 3.01k*
VIN
+ VSW
100µF LT1070
FB
GND VC

1k 1k*

1µF
AN29 F37

L1 = PULSE ENGINEERING, INC. # PE-65067

* = 1% FILM RESISTORS

Figure 37. Non-Isolated Version of Figure 35

WIDE RANGE INPUT CONVERTERS

Wide Range Input –48V to 5V Converter Figure 39 shows operating waveforms at the VSW pin.
Trace A is the voltage and Trace B the current. Switching
Often converters must accommodate a wide range of
is crisp, with well controlled waveforms. A higher current
inputs. Telephone lines can vary over considerable toler-
version of this circuit appears in LTC Application Note 25,
ances. Figure 38’s circuit uses an LT1072 to supply a 5V
“Switching Regulators For Poets.”
output from a telecom input. The raw telecom supply is
nominally –48V but can vary from –40V to –60V. This range 3.5V to 35VIN–5VOUT Converter
of voltages is acceptable to the VSW pin but protection is
required for the VIN pin (VMAX = 60V). Q1 and the 30V Figure 40’s approach has an even wider input range. In
Zener diode serve this purpose, dropping VIN’s voltage to this case it produces either a –5V or 5V output (shown in
acceptable levels under all line conditions. dashed lines). This circuit is an extension of Figure 11’s
basic flyback topology. The coupled inductor allows the
Here the “top” of the inductor is at ground and the LT1072’s option for buck, boost, or buck-boost converters. This
ground pin at –V. The feedback pin senses with respect circuit can operate down to 3.5V for battery applications
to the ground pin, so a level shift is required from the 5V while accepting 35V inputs.
output. Q2 serves this purpose, introducing only –2mV/°C
drift. This is normally not objectionable in a logic supply. Figure 41 shows the operating waveforms for this circuit.
It can be compensated with the optional appropriately During the VSW (Trace A) “on” time, current flows through
scaled diode-resistor shown in Figure 38. the primary winding (Trace B). No current is transferred
to the secondary because the catch diode, D1, is reverse
Frequency compensation uses an RC damper at the VC biased. The energy is stored in the magnetic field. When
pin. The 68V Zener is a type designed to clamp and absorb the switch is turned “off” D1 forward biases and the energy
excessive line transients which might otherwise damage is transferred to the secondary winding. Trace C is the
the LT1072 (VSW maximum voltage is 75V) voltage seen on the secondary and Trace D is the current

an29f

AN29-20
 Application Note 29

3k
1/2W
+ 220Ω
Q1 L1
100µF 1k
2N5550 100µH OPTIONAL
LOW DRIFT FEEDBACK
1N5936 CONNECTION (SEE TEXT)
68V**
30V
2.2µF FROM
+ * 5VOUT 5V OUTPUT
+ 3.9k
0.5A
3.01k
330µF
VIN VSW 1% 1%

Q2 Q2
LT1072HV 2N5401 2N5401
FB TO
GND VC FB PIN
Q3
1.1k 2N5401
2k
1%
0.22 1k 3.01k
INPUT 1% 1%
–48V TO
(–40V TO –60V) * –48V
MUR410 (MOTOROLA)
AN29 F38

**
1.5KE68A (MOTOROLA)

L1 = PULSE ENGINEERING, INC. # PE-92108

Figure 38. Wide Range Input Converter

flowing through it. This is not an ideal transformer so

not all of the primary windings energy is coupled into the
secondary. The energy left in the primary winding causes A = 50V/DIV

the overvoltage spikes seen on the VSW pin (Trace E). This
phenomenon is modeled by a leakage inductance term B = 0.5A/DIV
which is placed in series with the primary winding. When
the switch is turned “off” current continues to flow in the
inductor causing the snubber diode to conduct (Trace F). HORIZ = 5µs/DIV AN29 F39

The snubber diode current falls to zero as the inductor

Figure 39. Waveforms for Wide Range Input Converter
loses its energy. The snubber network clamps the voltage
spike. When the snubber diode current reaches zero, the Wide Range Input Positive Buck Converter
VSW pin voltage settles to a potential related to the turns
ratio, output voltage and input voltage.4 Figure 42 is another example of a positive buck converter.
This is a simpler version compared to the synchronous
The feedback pin senses with respect to ground, so Q1 switch buck, Figure 32. However, efficiency isn’t as high
through Q3 provides the level shift from the –5V output. (see Figure 34). If the PMOS transistor is replaced with
Q1 introduces a –2mV/°C drift to the circuit. This effect can a Darlington PNP transistor (shown in dashed lines)
be compensated by a circuit similar to the one shown in efficiency decreases further.
Figure 38. Line regulation is degraded due to Q3’s output
4Application Note AN19, “LT1070 Design Manual,” page 25
impedance. If this is a problem, an op amp must be used
to perform the level shift (see AN19, Figure 29).

an29f

AN29-21
Application Note 29
VIN = 3.5V TO 35V
5V
0.68µF 510Ω 1k* 1k*
3
1W • 1% 1%
n=1 L1 Q3 Q2 MBR360
MBR360 4 2N3906 2N3906 5VOUT
VIN (MOTOROLA) VIN L1 1A
3 2
+ VSW +
100µF n=1 1000µF
LT1070
FB 4 • 1
VSW 3.01k*
GND VC
FB
1k 1k*
1k*
1µF
Q1
2N2222
L1 = PULSE ENGINEERING, INC. # PE-65050 2
* = 1% FILM RESISTORS
+ OPTIONAL (SEE TEXT)
AN29 F40

L1 n=1 1000µF 3.32k*

1%
• 1
–5VOUT
1A
D1
MBR360

Figure 40. Wide Range Input Positive-to-Negative Flyback Converter

current does not instantly rise. As the magnetic field builds

A = 20V/DIV up, the current builds. This is seen in the inductor current
B = 4A/DIV waveform (Trace D). When the VSW pin is “off,” Q2 is able
to conduct and turns Q1 off. Current can no longer flow
C = 10V/DIV
through Q1, instead D2 is conducting (Trace E). During
D = 4A/DIV
this period some of the energy stored in the inductor will
be transferred to the load. Current will be generated from
E = 20V/DIV
the inductor as long as there is any energy in it. This can
F = 2A/DIV
be seen in Figure 43a. This is known as continuous mode
operation. If the inductor is completely discharged, no
AN29 F41
A, B, C, D HORIZ = 10µs/DIV
E, F HORIZ = 1µs/DIV
current will be generated (see Figure 43b). When this
Figure 41. Waveforms for Wide Range Input Positive
–5V Output Flyback Converter
happens neither switch, Q1 or D2, is conducting. The
inductor looks like a short and the voltage on the cathode
Figure 43a shows the operating waveforms for this circuit. of D2 will settle to the output voltage. These “boingies”
The pass transistor’s (Q1) drive scheme is similar to the one can be seen in Trace B of Figure 43b. This is known as
shown in Figure 32. During the VSW (Trace A) “on” time, discontinuous mode operation. Higher input voltages
the gate of the pass transistor is pulled down through D1. can be handled with the gate-source Zener clamped by
This forces Q1 to saturate. Trace B is the voltage seen on D2. The 400 milliwatt Zener’s current must be rescaled
the drain of Q1 and Trace C is the current passing through by adjusting the 50Ω value. Maximum gate-source volt-
Q1. The supply current flows through the inductor (Trace D) age is 20V. The circuit will function up to 35VIN. At inputs
and into the load. During this time energy is being stored beyond 35V all semiconductor breakdown voltages must
in the inductor. When voltage is applied to the inductor, be considered.

an29f

AN29-22
 Application Note 29
Q1
IRF9Z30 L1
0.1Ω (HEAT SINK) 170µH
VIN 5VOUT
12V TO 35V 5A
1k D2
1k D2
Q2 12V
2N3906 MBR735
2N2222A 1N759
(MOTOROLA)
D1 (OPT)
1N4148 100µF
+

51Ω
1W
3.01k*
VIN VSW
+
100µF E1 FB
LT1072CN8
1k*
E2
GND VC

1N4148

1k
2N2222
1k
5.1k 100pF
1µF

AN29 F42

2N6667
L1 = PULSE ENGINEERING, INC # PE-92113 (HEAT SINK)
* = 1% FILM RESISTORS
1k
OPTIONAL 2N2222
(SEE TEXT)

1N4148
100Ω
1W

Figure 42. Positive Buck Converter

A = 10V/DIV A = 10V/DIV

B = 10V/DIV B = 10V/DIV

C = 0.5A/DIV
C = 2A/DIV
D = 0.5A/DIV
D = 2A/DIV
E = 2A/DIV E = 0.5A/DIV

AN29 F43a
HORIZ = 10µs/DIV HORIZ = 10µs/DIV AN29 F43b

Figure 43a. Waveforms for Wide Range Input Positive Buck Figure 43b. Waveforms for Wide Range Input Positive Buck
Converter (Continuous Mode) Converter (Discontinuous Mode)

an29f

AN29-23
Application Note 29
L1 D4
Q1 MBR360
IRF9Z30 330µH
28V NOMINAL 28V
(15V TO 35V) D3 250mA
1k MBR360
+
7.5V 1000µF
Q2 (MOTOROLA)
2N2222A 1N755

1N4148

220Ω
1W
+ D1
D2
100µF MBR360
1N4148

26.1k
VIN VSW
E1 FB
LT1072CN8
1.21k*
E2
GND VC

1k

1µF

AN29 F44

L1 = PULSE ENGINEERING, INC # PE-52627

* = 1% FILM RESISTORS

Figure 44. Positive Buck-Boost Converter

Buck-Boost Converter
A = 20V/DIV
The buck boost topology is useful when the input volt-
age can either be higher or lower than the output. In this B = 10V/DIV

example, Figure 44, this is accomplished with a single

C = 20V/DIV
inductor instead of a transformer, as in Figure 40 (optional).
However, the input voltage range only extends down to D = 2A/DIV
15V and can reach to 35V. If the maximum 1.25A switch E = 2A/DIV
current rating of the LT1072 is exceeded an LT1071 or F = 2A/DIV
LT1070 can be used instead. At high power levels package HORIZ = 10µs/DIV AN29 F45

thermal characteristics should be considered.

Figure 45. Waveforms for Positive Buck-Boost Converter
The operation of the circuit is similar to the positive buck
converter, Figure 42. The gate drive to the pass transistor Figure 42). In this case, the inductor has the input voltage
is derived the same way except the gate-source voltage is applied across it, except for a Vbe and saturation losses.
clamped. Remember, the gate-source maximum voltage D4 is reverse biased and blocks the output capacitor from
rating is specified at ±20V. Figure 45 shows the operating discharging into the VSW pin. When the VSW pin is “off” Q1
waveforms. When the VSW pin is “on” (Trace A), the pass and D2 cease to conduct. Since the current in the inductor
transistor, Q1, is saturated. The gate voltage (Trace B) is (Trace E) continues to flow, D3 and D4 are forward biased
clamped by the Zener diode. Trace C is the voltage on the and the energy in the inductor is transferred into the load.
drain of Q1 and Trace D is the current through it. This Trace F is the current through D3. Also, D2 keeps Q1 from
is where the similarities between the two circuits end. staying on if the circuit is operating in buck mode. D1, on
Notice the inductor is pulled to within a diode drop, D2 the other hand, blocks current from flowing into the gate
above ground, instead of being tied to the output (see drive circuit when operating in boost mode.

an29f

AN29-24
 Application Note 29
VREF ≈ 1.8V
Q1 L1
2N6667 335µH LT1083
INPUT IN OUT OUTPUT
+ +
MR1122 10,000µF 470 ADJ 240* 10µF
10k

28V 1N914
2k
1k 0.001
VREF ≈ 1.8V

1M
4N28

10k AN29 F46

+
LT1011 L1 = PULSE ENGINEERING, INC. # PE-51518
10k * = 1% FILM RESISTOR
4
– 28V
1 1N914

Figure 46. High Power Linear Regulator with Switching Pre-Regulator

at a minimal value, regardless of line, load or output setting

A = 200mV/DIV
(AC-COUPLED) changes. Although this approach is not quite as efficient as
B = 50V/DIV a classical switching regulator, it offers lower noise and the
fast transient response of the linear regulator. The LT1083
C = 20V/DIV
functions in the conventional fashion, supplying a regulated
output at 7.5A capacity. The remaining components form
D = 5A/DIV
the switched-mode dissipation limiting control. This loop
HORIZ = 500µs/DIV AN29 F47
forces the potential across the LT1083 to equal the 1.8V
value of VREF . The opto-isolator furnishes a convenient
Figure 47. Switching Pre-Regulated Linear Regulators Waveforms
way to single end the differentially sensed voltage across
the LT1083. When the input of the regulator (Trace A,
Wide Range Switching Pre-Regulated Linear
Figure 47) decays far enough, the LT1011 output (Trace B)
Regulator
switches low, turning on Q1 (Q1 collector is Trace C). This
In a sense, linear regulators can be considered extraor- allows current flow (Trace D) from the circuit input into the
dinarily wide range DC/DC converters. They do not face 10,000µF capacitor, raising the regulator’s input voltage.
the dynamic problems switching regulators encounter
When the regulator input rises far enough, the comparator
under varying ranges of input and output. Excess energy
goes high, Q1 cuts off and the capacitor ceases charg-
is simply dissipated at heat. This elegantly simplistic
ing. The MR1122 damps the flyback spike of the current
energy management mechanism pays dearly in terms of
limiting inductor. The 0.001µF-1M combination sets loop
efficiency and temperature rise. Figure 46 shows a way a
hysteresis at about 100mVP-P . This free-running oscil-
linear regulator can more efficiently control high power
lation control mode substantially reduces dissipation in
under widely varying input and output conditions.
the regulator, while preserving its performance. Despite
The regulator is placed within a switched-mode loop that changes in the input voltage, different regulated outputs or
servo-controls the voltage across the regulator. In this load shifts, the loop always ensures minimum dissipation
arrangement the regulator functions normally while the in the regulator.
switched-mode control loop maintains the voltage across it

an29f

AN29-25
Application Note 29
100
POUT = 85W
90 POUT = 12W
VOUT = 12V VIN = 15V
80 POUT = 105W
70 VOUT = 15V VIN = 28V POUT = 35W
POUT = 15W VOUT = 5V VIN = 15V

EFFICIENCY (%)
60 POUT = 5W
POUT = 35W
50 VIN = 28V
VOUT = 5V
40 POUT = 5W
30 VOUT = 5V VIN = 15V LT1083 WITH NO PRE-REGULATOR. THEORETICAL LIMITS ONLY.
20 DISSIPATION LIMITED

10 VOUT = 5V VIN = 28V LT1083 WITH NO PRE-REGULATOR. THEORETICAL LIMITS ONLY.

DISSIPATION LIMITED
0
0 1 2 3 4 5 6 7
OUTPUT (A) AN29 F48

Figure 48. Efficiency vs Output Current for Figure 46 at Various Operating Points

Figure 48 plots efficiency at various operating points. Junc- 15V

22µF
tion losses and the loop enforced 1.8V across the LT1083 + 0.1µF
are relatively small at high output voltages, resulting in 2000V
*
good efficiency. Low output voltages do not fare as well, L1
3 7
but compare very favorably to the theoretical data for the 1k VOUT
0.47
LT1083 with no pre-regulator. At the higher theoretical 1/2W
1 8
1000V
5W
dissipation levels the LT1083 will shut down, precluding MUR120
practical operation. 10M
15V 1%
(SEE NOTES)

HIGH VOLTAGE CONVERTERS VIN VSW

FB
LT1072 12.4k 1%
High Voltage Converter—1000VOUT , Nonisolated (IDEAL VALUE–PAD AS REQUIRED
FOR 1000VOUT)
GND VC
Photomultiplier tubes, ion generators, gas-based detec-
2µF
tors, image intensifiers and other applications need high
voltages. Converters frequently supply these potentials. L1 = PULSE ENGINEERING, INC. # PE-6197
Generally, the limitation on high voltage is transformer 10M = MAX-750-22 VICTOREEN, INC.
*
insulation breakdown. A transformer is almost always = SEMTEC, FM-50

used because a simple inductor forces excessive volt-

Figure 49. Nonisolated 15V to 1000V Converter
ages on the semiconductor switch. Figure 49’s circuit,
reminiscent of Figure 11’s basic flyback configuration, is LT1072’s internal error amplifier and reference are replaced
a 15V to 1000VOUT converter. The LT1072 controls out- with galvanically isolated equivalents. Power for these
put by modulating the flyback energy into L1, forcing its components is bootstrapped from the output via source
feedback (FB) pin to 1.23V (the internal reference value). follower Q1 and its 2.2M ballast resistor. A1 and the LT1004,
In this example loop compensation is heavily overdamped micropower components, minimize dissipation in Q1 and
by the VC pin capacitor. L1’s damper network limits flyback its ballast. Q1’s gate bias, tapped from the output divider
spikes within the VSW pin’s 75V rating. string, produces about 15V at its source. A1 compares the
scaled divider output with the LT1004 reference. The error
Fully Floating, 1000VOUT Converter signal, A1’s output, drives the opto-coupler. Photocurrent
Figure 50 is similar to Figure 49 but features a fully floating is kept low to save power. The opto-coupler output pulls
output. This provision allows the output to be referenced down on the VC pin, closing a loop. Frequency compensa-
off system ground, often desirable for noise or biasing tion at the VC pin and A1 stabilizes the loop.
reasons. Basic loop action is as before, except that the
an29f

AN29-26
 Application Note 29
1000VOUT
15VIN L1 5W
3 7 0.1µF 0.1 2.2M
1k 0.47 2000V 10M (SEE NOTES)
1%
1 8 D
MUR120 Q1
VN2222
S
VIN VSW 200k*
NC FB 180k 7 200k
LT1072 8 + 5k
A1 OUTPUT
VC GND LT1006 10k ADJUST
3.6k –
4N46 4
LT1004
10k*
1.2V
1M
1k
AN29 F50
0.68
2µF

= INPUT GROUND

= OUTPUT COMMON
* = 1% METAL FILM RESISTOR
10M = VICTOREEN MAX-750-22
= SEMTEC, FM-50
L1 = PULSE ENGINEERING, INC. # PE-6197

Figure 50. Isolated Output 15V to 1000V Converter

The transformers isolated secondary and optical feedback domain. Some ceramic materials will transfer electrical
produce a regulated, fully galvanically floating output. energy with galvanic isolation. Conventional magnetic
Common mode voltages of 2000V are acceptable. transformers work on an electrical-magnetic-electrical
basis using the magnetic domain for electrical isolation.
20,000VCMV Breakdown Converter The acoustic transformer uses an acoustic path to get
Figure 50’s common mode breakdown limits are imposed isolation. The high voltage breakdown and low electrical
by transformer and opto-coupler restrictions. Isolation conductance associated with ceramics surpasses isolation
amplifiers, transducer measurement at high common mode characteristics of magnetic approaches. Additionally, the
voltages (e.g., winding temperature of a utility company acoustic transformer is simple. A pair of leads bonded to
transformer and ESD sensitive applications) require high each end of the ceramic material forms the device. Insula-
breakdowns. Additionally, very precise floating measure- tion resistance exceeds 1012Ω, with primary-secondary
ments, such as signal conditioning for high impedance capacitances of 1pF to 2pF. The material and its physical
bridges, can require extremely low leakage to ground. configuration determine its resonant frequency. The device
may be considered as a high Q resonator, similar to a quartz
Achieving high common mode voltage capability with crystal. As such, drive circuitry excites the device in the
minimal leakage requires a different approach. Magnet- positive feedback path of a wideband gain element. Unlike
ics is usually considered the only approach for isolated a crystal, drive circuitry is arranged to pass substantial
transfer of appreciable amounts of electrical energy. current through the ceramic, maximizing power into the
Transformer action is, however, achievable in the acoustic transformer.

an29f

AN29-27
Application Note 29
2k

15V 15V
– 2k
0.002 Q1
LT1011 2N3904
+
1N4148
100Ω * = 1% METAL FILM RESISTOR
PIEZOCERAMIC TRANSFORMERS
470pF PRIMARY AVAILABLE FROM CHANNEL
INDUSTRIES, INC. SANTA BARBARA, CA.
1k PIEZOCERAMIC
15V TRANSFORMER

680Ω 1N4148 10V

3 2
VIN VOUT FLOATING
OUTPUT
SECONDARY 1.5M*
LT1020 0.001µF
+ +
10µF 11 100µF
GND FB
500k*
FLOATING
OUTPUT
AN29 F51 COMMON

Figure 51. 15V to 10V Converter with 20,000V Isolation

A = 10V/DIV

VIN
1 8
B = 20mA/DIV + 2µF
2 7
+ C1 LT1054
3 6
10µF
4 5 –VOUT
C = 20V/DIV 100µF
C2
+
AN29 F52
HORIZ = 2µs/DIV AN29 F53

Figure 52. Waveforms for the 20,000V Isolation Converter Figure 53. A Basic Switched-Capacitor Converter

In Figure 51, the piezo-ceramic transformer is in the LT1011 transitions. The transformer looks like a highly resonant
comparators positive feedback loop. Q1 is an active pull-up filter to the resultant acoustic wave propagated in it. The
for the LT1011, an open-collector device. The 2k-0.002µF secondary voltage (Trace C) is sinusoidal. Additionally, the
path biases the negative input. Positive feedback occurs at transformer has voltage gain. The diode and 10µF capaci-
the transformers resonance, and oscillation commences tor convert the secondary voltage to DC. The LT1020 low
(Trace A, Figure 52 is Q1’s emitter). Similar to quartz quiescent current regulator gives a stabilized 10V output.
crystals, the transformer has significant harmonic and Output current for the circuit is a few milliamperes. Higher
overtone modes. The 100Ω-470pF damper suppresses currents are possible with attention to transformer design.
spurious oscillations and “mode hopping.” Drive current
(Trace B) approximates a sine wave, with peaking at the

an29f

AN29-28
 Application Note 29
2
3.5V ≤ VIN ≤ 15V
CIN = COUT = 100µF
•
1N4001 1N4001
VOLTAGE LOSS (V)

+VOUT
TJ = 125°C + + 1 8
1 100µF 10µF
2 7
3 LT1054 6
TJ = –55°C –VIN
• 4 5
TJ = 25°C

• INDICATES GUARANTEED TEST POINT AN29 F55

0 2µF
0 10 20 30 40 50 60 70 80 90 100 +
OUTPUT CURRENT (mA)
AN29 F54

Figure 54. Losses for the Basic Switched-Capacitor Converter Figure 55. Switched-Capacitor –VIN to +VOUT Converter

VIN ≥ 6V

9 3
GND VIN
8 2 5VOUT
–IN OUT
100mA
LT1020 500k* 0.001µF
5 11
COMP
REF COMP
FB +
1 8 10k PNP 500k* 10µF
+IN OUT NPN
+ 2 7 0.002 7 4 6
10µF LT1054
3 6 0.001µF +
10µF
1M* 499k* 100k
4 5
–5VOUT
+ 100µF AN29 F56 75mA
VN2222

100k

Figure 56. High Current Switched-Capacitor 6V to ±5V Converter

SWITCHED-CAPACITOR BASED CONVERTERS

Inductors are used in converters because they can store so C1 is “flipped” during the discharge interval, produc-
energy. This stored magnetic energy, released and ex- ing a negative output at C2. Continuous clocking allows
pressed in electrical terms, is the basis of converter opera- C2 to charge to the same absolute value as C1. Junction
tion. Inductors are not the only way to store energy with and other losses preclude ideal results, but performance
efficient release expressed in electrical terms. Capacitors is quite good. This circuit will convert VIN to –VOUT with
store charge (already an electrical quantity) and as such, losses shown in Figure 54. Adding an external resistive
can be used as the basis for DC/DC conversion. Figure 53 divider allows regulated output (see Appendix B).
shows how simple a switched-capacitor based converter
can be (the fundamentals of switched-capacitor based With some additional steering diodes this configuration
conversion are presented in Appendix B, “Switched-Capaci- can effectively run “backwards” (Figure 55), converting
tor Voltage Converters—How They Work”). The LT1054 a negative input to a positive output. Figure 56’s variant
provides clocked drive to charge C1. A second clock phase gives low dropout linear regulation for 5V and –5V out-
discharges C1 into C2. The internal switching is arranged puts from 6VIN. The LT1020-based dual output regulation
an29f

AN29-29
Application Note 29
scheme is adapted from Figure 8. Figure 57 uses diode High Power Switched-Capacitor Converter
steering to get voltage boost, providing ≈2VIN. Bootstrap-
Figure 61 shows a high power switched-capacitor converter
ping this configuration with Figure 54’s basic circuit leads
with a 1A output capacity. Discrete devices permit high
to Figure 58, which converts a 5V input to 12V and –12V
power operation.
outputs. As might be expected output current capacity is
traded for the voltage gain, although 25mA is still available. The LTC1043 switched-capacitor building block provides
Figure 59, another boost converter, employs a dedicated non-overlapping complementary drive to the Q1-Q4 power
version of Figure 58 (the LT1026) to get regulated ±7V MOSFETs. The MOSFETs are arranged so that C1 and
from a 6V input. The LT1026 generates unregulated ±11V C2 are alternately placed in series and then in parallel.
rails from the 6V input with the LT1020 and associated During the series phase, the 12V supply current flows
components (again, purloined from Figure 8) producing through both capacitors, charging them and furnishing
regulation. Current and boost capacity are reduced from load current. During the parallel phase, both capacitors
Figure 58’s levels, but the regulation and simplicity are deliver current to the load. Traces A and B, Figure 62, are
noteworthy. Figure 60 combines the LT1054’s clocked the LTC1043-supplied drives to Q3 and Q4, respectively.
switched-capacitor charging with classical diode voltage Q1 and Q2 receive similar drive from Pins 3 and 11. The
multiplication, producing positive and negative outputs. diode-resistor networks provide additional non-overlap-
At no load ±13V is available, falling to ±10V with each ping drive characteristics, preventing simultaneous drive
side supplying 10mA. to the series-parallel phase switches. Normally, the output
VIN
would be one-half of the supply voltage, but C1 and its
3.5V TO 15V associated components close a feedback loop, forcing
1N4001 1N4001 the output to 5V. With the circuit in the series phase, the
+
+ + + output (Trace C) heads rapidly positive. When the output
VOUT
100µF 10µF 2µF
exceeds 5V, C1 trips, forcing the LTC1043 oscillator pin
–
1 8 (Trace D) high. This truncates the LTC1043’s triangle wave
VIN = 3.5V TO 15V 2 7 oscillator cycle. The circuit is forced into the parallel phase
LT1054
VOUT ≈ 2VIN – (VL + 2VDIODE)
VL = LT1054 VOLTAGE LOSS
3 6 and the output coasts down slowly until the next LTC1043
4 5 clock cycle begins. C1’s output diode prevents the triangle
AN29 F57
down-slope from being affected and the 100pF capacitor
Figure 57. Voltage Boost Switched-Capacitor Converter provides sharp transitions. The loop regulates the output to

VIN = 5V

+
5µF
1N914 1N914
VOUT ≈ 12V
IOUT = 25mA
1 8 + +
100µF 10µF
+ 2
LT1054
7 1 8
10µF #1 20k
3 6 + 2 7
LT1054 1N5817
2N2219 10µF #2
4 5 3 6
100µF 5µF
+
1k
+ VOUT ≈ –12V
4 5
IOUT = 25mA
100µF
+
AN29 F58

Figure 58. Switched-Capacitor 5V to ±12V Converter

an29f

AN29-30
 Application Note 29
5V by feedback controlling the turn-off point of the series Williams, J., “Power Conditioning Techniques for Batter-
phase. The circuit constitutes a large scale switched-ca- ies,” Linear Technology Corporation, Application Note 8.
pacitor voltage divider which is never allowed to complete
Tektronix, Inc., CRT Circuit, Type 453 Operating Manual,
a full cycle. The high transient currents are easily handled
p. 3-16.
by the power MOSFETs and overall efficiency is 83%.
Pressman, A. I., “Switching and Linear Power Supply,
REFERENCES Power Converter Design,” Hayden Book Co., Hasbrouck
Heights, New Jersey, 1977, ISBN 0-8104-5847-0.
Williams, J., “Conversion Techniques Adopt Voltages to
your Needs,” EDN, November 10, 1982, p. 155. Chryssis, G., “High Frequency Switching Power Supplies,
Theory and Design,” McGraw Hill, New York, 1984, ISBN
Williams, J., “Design DC/DC Converters to Catch Noise 0-07-010949-4.
at the Source,” Electronic Design, October 15, 1981, p.
229. Sheehan, D., “Determine Noise of DC/DC Converters,”
Electronic Design, September 27, 1973.
Nelson, C., “LT1070 Design Manual,” Linear Technology
Corporation, Application Note 19. Bright, Pittman, and Royer, “Transistors as On-Off Switches
in Saturable Core Circuits,” Electronic Manufacturing,
Williams, J., “Switching Regulators for Poets,” Linear October, 1954.
Technology Corporation, Application Note 25.

1µF +
≈11V NO LOAD

1 8 9 3
2 7 +
+ 1µF 8
GND VIN
2
1µF LT1026 7VOUT
3 6 –IN OUT
6VIN 20mA
4 5 LT1020 500k* 0.001µF
5 11
1µF
COMP
REF COMP
FB +
100k PNP 270k* 100µF
+IN OUT NPN
+
0.002µF 7 4 6

0.001µF +
10µF
1M* 360k* 100k
–7VOUT
AN29 F59 20mA
VN2222 *1% METAL FILM RESISTOR

100k
≈–11V NO LOAD

Figure 59. Switched-Capacitor Based 6V to ±7V Converter

1 8
10µF 10µF 5V
2 7
+
+ +
3 LT1054 6
C1
10µF 4 5

+VOUT
+
+
+ 10µF 10µF
100µF 10µF 100µF
+ +
–VOUT

+ + AN29 F60

= 1N4148 10µF 10µF

Figure 60. Switched-Capacitor Charge Pump Based Voltage Multiplier

an29f

AN29-31
Application Note 29
12VIN 12VIN

8 22k
2k –
6 C1 LT1004
LT1011 1.2V REFERENCE
+
LTC1043 1

7 8 4
12VIN
100pF
1k S
11 Q1
D S Q3 D VOUT
5V
+ 1A
470µF 1k 470µF 38k
12

12k
13 14 12V

12V 6 5
S Q2 D
1k D
2 Q4
S
1k

3 AN29 F61

18 15
12VIN ALL DIODES ARE 1N4148
Q1, Q2, Q3 = IRF9531 P-CHANNEL
17
Q4 = IRF533 N-CHANNEL

16 4 12V
180pF

Figure 61. High Power Switched-Capacitor Converter

A = 20V/DIV

B = 20V/DIV

C = 0.1V/DIV
(AC-COUPLED)

D = 10V/DIV
AN29 F62
HORIZ = 20µs/DIV

Figure 62. Waveforms for Figure 61

an29f

AN29-32
 Application Note 29
APPENDIX A Figure A1 is a conceptual schematic of a typical converter.
The 5V input is applied to a self-oscillating configuration
The 5V to ±15V Converter—A Special Case composed of transistors, a transformer and a biasing
Five volt logic supplies have been standard since the intro- network. The transistors conduct out of phase, switching
duction of DTL logic over twenty years ago. Preceding and (Figure A2, Traces A and C are Q1’s collector and base,
during DTL’s infancy the modular amplifier houses stan- while Traces B and D are Q2’s collector and base) each
dardized on ±15V rails. As such, popular early monolithic time the transformer saturates.5 Transformer saturation
amplifiers also ran from ±15V rails (additional historical causes a quickly rising, high current to flow (Trace E).
perspective on amplifier power supplies appears in AN11’s This current spike, picked up by the base drive winding,
appended section, “Linear Power Supplies—Past, Present switches the transistors. Transformer current abruptly
and Future”). The 5V supply offered process, speed and drops and then slowly rises until saturation again forces
density advantages to digital ICs. The ±15V rails provided switching. This alternating operation sets transistor duty
a wide signal processing range to the analog components. cycle at 50%. The transformers secondary is rectified,
These disparate needs defined power supply requirements filtered and regulated to produce the output.
for mixed analog-digital systems at 5V and ±15V. In sys- This configuration has a number of desirable features. The
tems with large analog component populations the ±15V complementary high frequency (typically 20kHz) square
supply was and still is usually derived from the AC line. wave drive makes efficient use of the transformer and allows
Such line derived ±15V power becomes distinctly undesir- relatively small filter capacitors. The self-oscillating primary
able in predominantly digital systems. The inconvenience, drive tends to collapse under overload, providing desir-
difficulty and cost of distributing analog rails in heavily able short-circuit characteristics. The transistors switch
digital systems makes local generation attractive. 5V to in saturated mode, aiding efficiency. This hard switching,
±15V DC/DC converters were developed to fill this need combined with the transformer’s deliberate saturation does,
and have been with us for about as long as 5V logic. however, have a drawback. During the saturation interval
a significant, high frequency current spike is generated
5This type of converter was originally described by Royer, et al. See
References.

5VIN
INPUT
FILTER

Q1 LINEAR
5 REGULATORS
OUTPUT
+VREG 15V
Q2 POWER
SWITCHING
6
1

C1 R2 OUT
R1 COMMON
2
–VREG –15V
BASE BIASING + AN29 FA1
AND DRIVE +
3

Figure A1. Conceptual Schematic of a Typical 5V to ±15V Converter

an29f

AN29-33
Application Note 29

A = 20V/DIV
A = 10V/DIV
B = 20V/DIV
C = 2V/DIV
D = 2V/DIV B = 2A/DIV

E = 5A/DIV

F = 0.02V/DIV C = 10mV/DIV

AN29 FA2
HORIZ = 5µs/DIV HORIZ = 500ns/DIV AN29 FA3

Figure A2. Typical 5V to ±15V Saturating Converters Waveforms Figure A3. Switching Details of Saturating Converter

(again, Trace E). This spike causes noise to appear at the drive, ensuring transistor saturation under heavy loading
converter outputs (Trace F is the AC-coupled 15V output). but wasting power at lighter loads. Adaptive bias schemes
Additionally, it pulls significant current from the 5V supply. will mitigate this problem, but increase complexity and
The converters input filter partially smooths the transient, almost never appear in converters of this type.
but the 5V supply is usually so noisy the disturbance is The noise problem is, however, the main drawback of this
acceptable. The spike at the output, typically 20mV high, is approach to 5V to ±15V conversion. Careful design, layout,
a more serious problem. Figure A3 is a time and amplitude filtering and shielding (for radiated noise) can reduce noise,
expansion of Figure A2’s Traces B, E and F. It clearly shows but cannot eliminate it.
the relationship between transformer current (Trace B,
Figure A3), transistor collector voltage (Trace A, Figure A3) Some techniques can help these converters with the noise
and the output spike (Trace C, Figure A3). As transformer problem. Figure A4 uses a “bracket pulse” to warn the
current rises, the transistor starts coming out of satura- powered system when a noise pulse is about to occur.
tion. When current rises high enough the circuit switches, Ostensibly, noise sensitive operations are not carried
causing the characteristic noise spike. This condition is out during the bracket pulse interval. The bracket pulse
exacerbated by the other transistors concurrent switching, (Trace A, Figure A5) drives a delayed pulse generator
causing both ends of the transformer to simultaneously which triggers (Trace B) the flip-flop. The flip-flop output
conduct current to ground. biases the switching transistors (Q1 collector is Trace C).
The output noise spike (Trace D) occurs within the bracket
Selection of transistors, output filters and other techniques pulse interval. The clocked operation can also prevent
can reduce spike amplitude, but the converters inherent transformer saturation, offering some additional noise
operation ensures noisy outputs. reduction. This scheme works well, but presumes the
This noisy operation can cause difficulties in precision powered system can tolerate periodic intervals where
analog systems. IC power supply rejection at the high critical operations cannot take place.
harmonic spike frequency is low, and analog system er- In Figure A6 the electronic tables are turned. Here, the
rors frequently result. A 12-bit SAR A-to-D converter is host system silences the converter when low noise is
a good candidate for such spike-noise caused problems. required. Traces B and C are base and collector drives
Sampled data ICs such as switched capacitor filters and for one transistor while Traces D and E show drive to the
chopper amplifiers often show apparent errors which are other device. The collector peaking is characteristic of
due to spike induced problems. “Simple” DC circuits can saturating converter operation. Output noise appears on
exhibit baffling “instabilities” which in reality are spike Trace F. Trace A’s pulse gates off the converter’s base bias,
caused problems masquerading as DC shifts. stopping switching. This occurs just past the 6th vertical
The drive scheme is also responsible for high quiescent division. With no switching, the output linear regulator sees
current consumption. The base biasing always supplies full the filter capacitor’s pure DC and noise disappears.

an29f

AN29-34
 Application Note 29
OVERLAP PULSE
OUTPUT

Q Q1 TO
OVERLAP 5V
DELAYED ÷2 RECTIFIERS,
PULSE
PULSE FLIP-FLOP FILTERS AND
GENERATOR
REGULATORS
Q Q2

AN29 FA4

Figure A4. Overlap Generator Provides a “Bracket Pulse” Around Noise Spikes

A = 5V/DIV

B = 20V/DIV

A = 5V/DIV C = 1A/DIV

B = 10V/DIV
D = 20V/DIV
C = 5V/DIV
E = 1A/DIV

D = 20mV/DIV
F = 50mV/DIV
(AC-COUPLED ON
15V LEVEL)
AN29 FA5
HORIZ = 500ns/DIV HORIZ = 20µs/DIV AN29 FA6

Figure A5. Waveforms for the Bracket Pulse Based Converter Figure A6. Detail of the Strobed Operation Converter

This arrangement also works nicely but assumes the control Other methods involve clock synchronization, timing skew-
pulse can be conveniently generated by the system. It also ing and other schemes which prevent noise spikes from
requires larger filter capacitors to supply power during the coinciding with sensitive operations. While useful, none
low noise interval. of these arrangements offer the flexibility of the inherently
noise free converters shown in the text.

APPENDIX B

Switched Capacitor Voltage Converters—How They

Work
To understand the theory of operation of switched capacitor If the switch is cycled f times per second, the charge
converters, a review of a basic switched capacitor building transfer per unit time (i.e., current) is:
block is helpful.
1 = f • Q = f • C1(V1 – V2)
In Figure B1, when the switch is in the left position,
To obtain an equivalent resistance for the switched-
capacitor C1 will charge to voltage V1. The total charge
capacitor network we can rewrite this equation in terms
on C1 will be Q1 = C1V1. The switch then moves to the
of voltage and impedance equivalence:
right, discharging C1 to voltage V2. After this discharge
time, the charge on C1 is Q2 = C1V2. Note that charge V1– V2 V1– V2
1= =
has been transferred from the source, V1, to the output, 1 REQUIV
V2. The amount of charge transferred is: fC1

Q = Q1 – Q2 = C1(V1 – V2)
an29f

AN29-35
Application Note 29
A new variable, REQUIV , is defined such that REQUIV = 1/fC1. a minimum. Figure B3 shows the block diagram of the
Thus, the equivalent circuit for the switched-capacitor LT1054 switched-capacitor converter.
network is as shown in Figure B2. The LT1054 and other
The LT1054 is a monolithic, bipolar, switched-capacitor volt-
switched-capacitor converters have the same switching
age converter and regulator. It provides higher output cur-
action as the basic switched-capacitor building block. Even
rent then previously available converters with significantly
though this simplification doesn’t include finite switch
lower voltage losses. An adaptive switch drive scheme
on-resistance and output voltage ripple, it provides an
optimizes efficiency over a wide range of output currents.
intuitive feel for how the device works.
Total voltage loss at 100mA output current is typically 1.1V.
These simplified circuits explain voltage loss as a func- This holds true over the full supply voltage range of 3.5V
tion of frequency. As frequency is decreased, the output to 15V. Quiescent current is typically 2.5mA.
impedance will eventually be dominated by the 1/fC1 term
The LT1054 also provides regulation. By adding an external
and voltage losses will rise.
resistive divider, a regulated output can be obtained. This
Note that losses also rise as frequency increases. This is output will be regulated against changes in input voltage
caused by internal switching losses which occur due to and output current. The LT1054 can also be shut down by
some finite charge being lost on each switching cycle. This grounding the feedback pin. Supply current in shutdown
charge loss per-unit-cycle, when multiplied by the switching is less than 100µA.
frequency, becomes a current loss. At high frequency this
The internal oscillator of the LT1054 runs at a nominal
loss becomes significant and voltage losses again rise.
frequency of 25kHz. The oscillator pin can be used to ad-
The oscillators of practical converters are designed to just the switching frequency, or to externally synchronize
run in the frequency band where voltage losses are at the LT1054.

V1 V2 VREF VIN

f 6 8

2.5V
C1 C2 RL REF
R
AN29 FB1 +
DRIVE
Figure B1. Switched-Capacitor Building Block
1 –
CAP+ 2
FEEDBACK/
SHUTDOWN +
REQUIV CIN*
V1 V2 Q
R OSC
Q CAP– 4
1
REQUIV = C2 RL
fC1
7 DRIVE DRIVE
OSC
AN29 FB2
3 GND
*EXTERNAL CAPACITORS +
Figure B2. Switched-Capacitor Equivalent Circuit COUT*

5 –VOUT

DRIVE

AN29 FB3

Figure B3. LT1054 Switched-Capacitor Converter Block Diagram

an29f

AN29-36
 Application Note 29
APPENDIX C conditions. Finally, it allows simple pulse-by-pulse current
limiting to provide maximum switch protection under out-
Physiology of the LT1070 put overload or short conditions. A low dropout internal
The LT1070 is a current mode switcher. This means that regulator provides a 2.3V supply for all internal circuitry on
switch duty cycle is directly controlled by switch current the LT1070. This low dropout design allows input voltage
rather than by output voltage. Referring to Figure C1, the to vary from 3V to 60V with virtually no change in device
switch is turned on at the start of each oscillator cycle. It performance. A 40kHz oscillator is the basic clock for all
is turned off when switch current reaches a predetermined internal timing. It turns on the output switch via the logic
level. Control of output voltage is obtained by using the and driver circuitry. Special adaptive antisat circuitry de-
output of a voltage-sensing error amplifier to set current tects onset of saturation in the power switch and adjusts
trip level. This technique has several advantages. First, driver current instantaneously to limit switch saturation.
it has immediate response to input voltage variations, This minimizes driver dissipation and provides very rapid
unlike ordinary switchers which have notoriously poor turn-off of the switch.
line transient response. Second, it reduces the 90° phase A 1.2V bandgap reference biases the positive input of
shift at mid-frequencies in the energy storage inductor. the error amplifier. The negative input is brought out for
This greatly simplifies closed-loop frequency compensa- output voltage sensing. This feedback pin has a second
tion under widely varying input voltage or output load function; when pulled low with an external resistor,

SWITCH
VIN 16V OUT

2.3V FLYBACK
REG ERROR
AMP

5A
40kHz LOGIC DRIVER 75V
OSC
SWITCH

MODE ANTI-SAT
SELECT

COMP

–
FB
ERROR VC
+ AMP
+
CURRENT 0.02Ω
AMP
SHUTDOWN –
CIRCUIT GAIN ≈ 6

1.24V REF
+
0.15V

AN29 FC1

Figure C1. LT1070 Internal Details

an29f

AN29-37
Application Note 29
it programs the LT1070 to disconnect the main error The error signal developed at the comparator input is
amplifier output and connects the output of the flyback brought out externally. This pin (VC) has four different
amplifier to the comparator input. The LT1070 will then functions. It is used for frequency compensation, current
regulate the value of the flyback pulse with respect to the limit adjustment, soft-starting, and total regulator shut-
supply voltage. This flyback pulse is directly proportional down. During normal regulator operation this pin sits at a
to output voltage in the traditional transformer-coupled voltage between 0.9V (low output current) and 2.0V (high
flyback topology regulator. By regulating the amplitude output current). The error amplifiers are current output
of the flyback pulse the output voltage can be regulated (gm) types, so this voltage can be externally clamped
with no direct connection between input and output. The for adjusting current limit. Likewise, a capacitor-coupled
output is fully floating up to the breakdown voltage of external clamp will provide soft-start. Switch duty cycle
the transformer windings. Multiple floating outputs are goes to zero if the VC pin is pulled to ground through a
easily obtained with additional windings. A special delay diode, placing the LT1070 in an idle mode. Pulling the VC
network inside the LT1070 ignores the leakage inductance pin below 0.15V causes total regulator shutdown with only
spike at the leading edge of the flyback pulse to improve 50µA supply current for shutdown circuitry biasing. For
output regulation. more details, see Linear Technology Application Note 19,
Pages 4-8.

APPENDIX D

Inductor Selection for Flyback Converters

A common problem area in DC/DC converter design is the Figure D1 shows a typical flyback based converter utilizing
inductor, and the most common difficulty is saturation. An the LT1070 switching regulator. A simple approach may
inductor is saturated when it cannot hold any more magnetic be employed to determine the appropriate inductor. A very
flux. As an inductor arrives at saturation it begins to look useful tool is the #845 inductor kit6 shown in Figure D2.
more resistive and less inductive. Under these conditions This kit provides a broad range of inductors for evaluation
current flow is limited only by the inductor’s DC copper in test circuits such as Figure D1.
6Available from Pulse Engineering, Inc., P.O. Box 12235, San Diego, CA
resistance and the source capacity. This is why saturation
92112, 619-268-2400
often results in destructive failures.
While saturation is a prime concern, cost, heating, size, 22µF
+
5VIN TEST
INDUCTOR
availability and desired performance are also significant.
Electromagnetic theory, although applicable to these issues,
can be confusing, particularly to the non-specialist. VIN VSW
GND LT1070 MBR735 (MOTOROLA)
10.7k
Practically speaking, an empirical approach is often a VC FB 12V OUTPUT

good way to address inductor selection. It permits real +

1k
time analysis under actual circuit operating conditions 1.24k 470µF
+
using the ultimate simulator—a breadboard. If desired, 1µF
inductor design theory can be used to augment or confirm AN29 FD1

experimental results.
Figure D1. Basic LT1070 Flyback Converter Test Circuit

an29f

AN29-38
 Application Note 29
Figure D3 was taken with a 450µH value, high core capac- The described procedure narrows the inductor choice
ity inductor installed. Circuit operating conditions such as within a range of devices. Several were seen to produce
input voltage and loading are set at levels appropriate to acceptable electrical results, and the “best” unit can be
the intended application. Trace A is the LT1070’s VSW pin further selected on the basis of cost, size, heating and other
voltage while Trace B shows its current. When VSW pin parameters. A standard device in the kit may suffice, or a
voltage is low, inductor current flows. The high induc- derived version can be supplied by the manufacturer.
tance means current rises relatively slowly, resulting in
Using the standard products in the kit minimizes specifica-
the shallow slope observed. Behavior is linear, indicating
tion uncertainties, accelerating the dialogue between user
no saturation problems. In Figure D4, a lower value unit
and inductor vendor.
with equivalent core characteristics is tried. Current rise
is steeper, but saturation is not encountered. Figure D5’s
selected inductance is still lower, although core char-
acteristics are similar. Here, the current ramp is quite A = 20V/DIV

pronounced, but well controlled. Figure D6 brings some

informative surprises. This high value unit, wound on a
low capacity core, starts out well but heads rapidly into
saturation, and is clearly unsuitable. B = 1A/DIV

AN29 FD4
HORIZ = 5µs/DIV

Figure D4. Waveforms for 170µH, High Capacity Core Unit

A = 20V/DIV

B = 1A/DIV

Figure D2. Model 845 Inductor Selection Kit from Pulse

Engineering, Inc. (Includes 18 Fully Specified Devices) AN29 FD5
HORIZ = 5µs/DIV

Figure D5. Waveforms for 55µH, High Capacity Core Unit

A = 20V/DIV

A = 20V/DIV

B = 1A/DIV
B = 1A/DIV

AN29 FD3
HORIZ = 5µs/DIV

Figure D3. Waveforms for 450µH, High Capacity Core Unit HORIZ = 5µs/DIV AN29 FD6

Figure D6. Waveforms for 500µH, Low Capacity Core Inductor

(Note Saturation Effects)
an29f

AN29-39
Application Note 29
APPENDIX E

Optimizing Converters for Efficiency

Squeezing the utmost efficiency out of a converter is a device temperature rise. Appropriate tools here include
complex, demanding design task. Efficiency exceeding 80% thermal probes and (at low voltages) the perhaps more
to 85% requires some combination of finesse, witchcraft readily available human finger. At lower power (e.g., less
and just plain luck. Interaction of electrical and magnetic dissipation, even though loss percentage may be as great)
terms produces subtle effects which influence efficiency. this technique is less effective. Sometimes deliberately
A detailed, generalized method for obtaining maximum adding a known loss to the component in question and
converter efficiency is not readily described but some noting efficiency change allows loss determination.
guidelines are possible. Ohmic losses in conductors are usually only significant
Losses fall into several loose categories including junction, at higher currents. “Hidden” ohmic losses include socket
ohmic, drive, switching and magnetic losses. and connector contact resistance and equivalent series
resistance (ESR) in capacitors. ESR generally drops with
Semiconductor junctions produce losses. Diode drops
capacitor value and rises with operating frequency, and
increase with operating current and can be quite costly
should be specified on the capacitor data sheet. Consider
in low voltage output converters. A 700mV drop in a
the copper resistance of inductive components. It is often
5V output converter introduces more than 10% loss.
necessary to evaluate trade-offs of an inductors copper
Schottky devices will cut this nearly in half, but loss is still
resistance versus magnetic characteristics.
appreciable. Germanium (rarely used) is lower still, but
switching losses negate the low DC drop at high speeds. Drive losses were mentioned, and are important in obtaining
In very low power converters Germanium’s reverse leak- efficiency. MOSFET gate capacitance draws substantial AC
age may be equally oppressive. Synchronously-switched drive current per cycle, implying higher average currents as
rectification is more complex, but can sometimes simulate frequency goes up. Bipolar devices have lower capacitance,
a more efficient diode (see text Figure 32). When evaluat- but DC base current eats power. Large area devices may
ing such a scheme remember to include both AC and DC appear attractive for low saturation, but evaluate drive
drive losses in efficiency estimates. DC losses include losses carefully. Usually, large area devices only make
base or gate current in addition to DC consumption in sense when operating at a significant percentage of rated
any driver stage. AC losses might include the effects of current. Drive stages should be thought out with respect
gate (or base) capacitance, transition region dissipation to efficiency. Class A type drives (e.g., resistive pull-up
(the switch spends some time in its linear region) and or pull-down) are simple and fast, but wasteful. Efficient
power lost due to timing skew between drive and actual operation usually requires active source-sink combinations
switch action. with minimal cross conduction and biasing losses.
Transistor saturation losses are also a significant term. Switching losses occur when devices spend significant
Channel and collector-emitter saturation losses become amounts of time in their linear region relative to operating
increasingly significant as operating voltages decrease. The frequency. At higher repetition rates transition times can
most obvious way to minimize these losses is to select low become a substantial loss source. Device selection and
saturation components. In some cases this will work, but drive techniques can minimize these losses.
remember to include the drive losses (usually higher) for Magnetics design also influences efficiency. Design of
lower saturation devices in overall loss estimates. Actual inductive components is well beyond the scope of this ap-
losses caused by saturation effects and diode drops is pended section, but issues include core material selection,
sometimes difficult to ascertain. Changing duty cycles wire type, winding techniques, size, operating frequency,
and time variant currents make determination tricky. One current levels, temperature and other issues.
simple way to make relative loss judgements is to measure

an29f

AN29-40
 Application Note 29
Some of these topics are discussed in Linear Technology good efficiencies to be obtained with standard magnetics.
Application Note 19, but there is no substitute for access Custom magnetics are usually only employed after circuit
to a skilled magnetics specialist. Fortunately, the other losses have been reduced to lowest practical levels.
categories mentioned usually dominate losses, allowing

APPENDIX F

Instrumentation for Converter Design

Instrumentation for DC/DC converter design should be but introduce heavier loading. Figure F3 shows an almost
selected on the basis of flexibility. Wide bandwidths, high absurdly simple, but useful, circuit which greatly aids
resolution and computational sophistication are valuable probe loading problems. The LT1022 high speed FET op
features, but are usually not required for converter work. amp drives an LT1010 buffer. The LT1010’s output allows
Typically, converter design requires simultaneous obser- cable and probe driving and also biases the circuit’s input
vation of many circuit events at relatively slow speeds. shield. This bootstraps the input capacitance, reducing its
Single ended and differential voltage and current signals effect. DC and AC errors of this circuit are low enough for
are of interest, with some measurements requiring fully almost all converter work, with enough bandwidth for most
floating inputs. Most low level measurement involves circuits. Built into a small enclosure with its own power
AC signals and is accommodated with a high sensitivity supply, it can be used ahead of a ‘scope or DVM with good
plug-in. Other situations call for observation of small, results. Pertinent specifications appear in the diagram.
slowly changing (e.g., 0.1Hz to 10Hz) events on top of DC Figure F4 shows a simple probe filter which sets high and
levels. This range falls outside the AC-coupled cut-off of low bandwidth restrictions. This circuit, placed in series
most oscilloscopes, mandating differential DC nulling or with the ‘scope input, is useful for eliminating switching
“slide-back” plug-in capability. Other requirements include artifacts when observing circuit nodes.
high impedance probes, filters and oscilloscopes with
very versatile triggering and multi-trace capability. In our An isolated probe allows fully floating measurements,
converter work we have found a number of particularly even in the presence of high common mode voltages. It
noteworthy instruments in several categories. is often desirable to look across floating points in a circuit.
The ability to directly observe an ungrounded transistor’s
Probes saturation characteristics or monitor waveforms across a
floating shunt makes this probe valuable. One probe, the
For many measurements standard 1× and 10× scope
Signal Acquisition Technologies, Inc. Model SL-10, has
probes are fine. In most cases the ground strap may be
10MHz bandwidth and 600V common mode capability.
used, but low level measurements, particularly in the pres-
ence of wideband converter switching noise, should be Current probes are an indispensable tool in converter
taken with the shortest possible ground return. A variety design. In many cases current waveforms contain more
of probe tip grounding accessories are available, and are valuable information than voltage measurements. The
usually supplied with good quality probes (see Figure F1). clip-on types are quite convenient. Hall effect based ver-
In some cases, directly connecting the breadboard to the sions respond down to DC, with bandwidths of 50MHz.
‘scope may be necessary (Figure F2). Transformer types are faster, but roll off below several
hundred cycles (Figure F5). Both types have saturation
Wideband FET probes are not normally needed, but a
limitations which, when exceeded, cause odd results
moderate speed, high input impedance buffer probe is quite
on the CRT, confusing the unwary. The Tektronix P6042
useful. Many converter circuits, especially micropower
(and the more recent AM503) Hall type and P6022/134
designs, require monitoring of high impedance nodes. The
transformer based type give excellent results. The Hewlett-
10MΩ loading of standard 10× probes usually suffices,
Packard 428B clip-on current probe responds from DC
but sensitivity is traded away. 1× probes retain sensitivity,
an29f

AN29-41
Application Note 29

Figure F1. Proper Probing Technique for Low Level Measurements in the Presence of High Frequency Noise

Figure F2. Direct Connections to the Oscilloscope Give Best Low Level Measurements.
Note Ground Reference Connection to the Differential Plug-In’s Negative Input
an29f

AN29-42
 Application Note 29
to only 400Hz, but features 3% accuracy over a 100µA the more modern 7603), equipped with a type 1A4 (2 dual
to 10A range. This instrument, useful for determining ef- trace 7A18s required for the 7603) plug-in, has four full
ficiency and quiescent current, eliminates shunt caused capability input channels with flexible triggering and superb
measurement errors. CRT trace clarity. This instrument, or its equivalent, will
handle a wide variety of converter circuits with minimal
Oscilloscopes and Plug-Ins restrictions. The Tektronix 556 offers an extraordinary
The oscilloscope plug-in combination is an important array of features valuable in converter work. This dual
choice. Converter work almost demands multi-trace ca- beam instrument is essentially two fully independent
pability. Two channels are barely adequate, with four far oscilloscopes sharing a single CRT. Independent vertical,
preferable. The Tektronix 2445/6 offers four channels, but horizontal and triggering permit detailed display of almost
two have limited vertical capability. The Tektronix 547 (and any converters operation. Equipped with two type 1A4

18V

10k

1000pF
–
LT1022 LT1010 OUTPUT
CLIP
INPUTS
+

AN29 FF3

–18V INPUT CAPACITANCE ≈ 8pF

IB = 50pA
GBW = 8.5MHz
SLEW = 23V/µs
OFFSET VOLTAGE = 250µV
OFFSET TEMPERATURE DRIFT = 5µV/°C

Figure F3. A Simple High Impedance Probe

OUT
160pF
100kHz

0.0016
10kHz

0.016 HIGH PASS

1kHz

0.16µF
100Hz BNC OUTPUT
(TO SCOPE)
1.6µF
16k
BNC INPUT 10Hz
(TO PROBE) CSMALL
SCOPE 1M TYPICALLY
LOW PASS
9pF TO 22pF

1µF 0.1 0.01 0.001 100pF

AN29 FF4

10Hz 100Hz 1kHz 10kHz 100kHz OUT

Figure F4. Oscilloscope Filter

an29f

AN29-43
Application Note 29
plug-ins, the 556 will display eight real time inputs. The units also have selectable high and low pass filters and
independent triggering and time bases allow stable display good high frequency common mode rejection. Tektronix
of asynchronous events. Cross beam triggering is also types W, 1A5 and 7A13 are differential comparators. They
available, and the CRT has exceptional trace clarity. have calibrated DC nulling (“slideback”) sources, allow-
Two oscilloscope plug-in types merit special mention. ing observation of small, slowly moving events on top of
At low level, a high sensitivity differential plug-in is in- common mode DC.
dispensable. The Tektronix 1A7 and 7A22 feature 10µV
Voltmeters
sensitivity, although bandwidth is limited to 1MHz. The
Almost any DVM will suffice for converter work. It should
have current measurement ranges and provision for
battery operation. The battery operation allows floating
A = 100mA/DIV
measurements and eliminates possible ground loop er-
B = 100mA/DIV
rors. Additionally, a non-electronic (VOM) voltmeter (e.g.,
Simpson 260, Triplett 630) is a worthwhile addition to the
converter design bench. Electronic voltmeters are occa-
AN29 FF5
sionally disturbed by converter noise, producing erratic
HORIZ = 2ms/DIV
readings. A VOM contains no active circuitry, making it
Figure F5. Hall (Trace A) and Transformer (Trace B) Based less susceptible to such effects.
Current Probes Responding to Low Frequency

APPENDIX G

The Magnetics Issue

Magnetics is probably the most formidable issue in purveyor of switching power ICs we incur responsibility
converter design. Design and construction of suitable towards addressing the magnetics issue (our publicly
magnetics is a difficult task, particularly for the non-spe- spirited attitude is, admittedly, capitalistically influenced).
cialist. It is our experience that the majority of converter As such, it is LTC’s policy to use off-the-shelf magnetics
design problems are associated with magnetics require- in our circuits. In some cases, available magnetics serve
ments. This consideration is accented by the fact that a particular design. In other situations the magnetics have
most converters are employed by non-specialists. As a been specially designed, assigned a part number and
made available as standard product. In these endeavors
our magnetics supplier and partner is;
Pulse Engineering, Inc.
P.O. Box 12235
7250 Convoy Court
San Diego, California 92112
619-268-2400
In many circumstances a standard product is suitable
for production. Other cases may require modifications or
Figure G1. Magnetics for LTC Applications Circuits are Designed changes which Pulse Engineering can provide. Hopefully,
and Supplied as Standard Product by Pulse Engineering, Inc. this approach serves the needs of all concerned.

an29f

AN29-44
 Application Note 29
APPENDIX H

LT1533 Ultralow Noise Switching Regulator for High 15V represents the maximum allowable input supply. Many
Voltage or High Current Applications applications require higher voltage inputs; the circuit in
Figure H1 uses a cascoded3 output stage to achieve such
The LT1533 switching regulator1, 2 achieves 100µV out-
high voltage capability. This 24V to 5V (VIN = 20V–50V)
put noise by ­using closed-loop control around its output
converter is reminiscent of previous LT1533 circuits,
switches to tightly control switching transition time. Slow-
except for the presence of Q1 and Q2.4 These devices,
ing down switch transitions eliminates high frequency
interposed between the IC and the transformer, constitute
harmonics, greatly reducing conducted and radiated noise.
a cascoded high voltage stage. They provide voltage gain
The part’s 30V, 1A output transistors limit available power. while isolating the IC from their large drain voltage swings.
It is possible to exceed these limits while maintaining low
Normally, high voltage cascodes are designed to simply
noise performance by using suitably designed output
supply voltage isolation. Cascoding the LT1533 presents
stages.
special considerations b­ ecause the transformer’s instanta-
High Voltage Input Regulator neous voltage and current information must be accurately
transmitted, albeit at lower amplitude, to the LT1533. If
The LT1533’s IC process limits collector breakdown to this is not done, the regulator’s slew-control loops will
30V. A complicating factor is that the transformer causes not function, causing a dramatic output noise increase.
the collectors to swing to twice the supply voltage. Thus, The AC-compensated resistor dividers associated with the
T1
6

7
5

8
24VIN
(20V TO 50V) + 4
10µF

9
3

10
MBRS140
L1
100µH
5VOUT L3
100µH ( OPTIONAL
SEE TEXT )
1
0.002µF 10k + +
10k 220Ω 10k 220Ω 220µF 100µF
Q3
12
MPSA42 0.002µF
1k 1k
Q4 Q1 Q2 2
2N2222 +
4.7µF MBRS140
2 15 11
14 COL A COL B
VIN
4
SYNC
3
DUTY
11
1500pF SHDN
5
CT LT1533 L2
16
18k 6 PGND
RT
8
NFB 7.5k
10 1%
VC 7
FB
GND RCSL RVSL
0.01µF 2.49k
9 12 13 1%
12k 10k AN29 FH1 AN70 F40

L1, L3: COILTRONICS CTX100-3

L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR
INDUCTOR COILCRAFT B-07T TYPICAL
Q1, Q2: MTD6N15
T1: COILTRONICS VP4-0860

Figure 1H. A Low Noise 24V to 5V Converter (VIN = 20V–50V): Cascoded MOSFETs
Withstand 100V Transformer Swings, Permitting the LT1533 to Control 5V/2A Output
an29f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. AN29-45
Application Note 29
Q1–Q2 gate-drain biasing serve this purpose, preventing The follower loss limits efficiency to about 68%. Higher
transformer swings coupled via gate-channel capacitance input voltages minimize follower-induced loss, permitting
from c­ orrupting the cascode’s waveform-transfer fidelity. efficiencies in the low 70% range.
Q3 and associated components provide a stable DC termi- Figure H4 shows noise performance. Ripple measures 4mV
nation for the dividers while protecting the LT1533 from (Trace A) using a single LC section, with high frequency
the high voltage input. content just discernible. Adding the optional second LC
Figure H2 shows that the resultant cascode response is section reduces ripple to below 100µV (trace B), and high
faithful, even with 100V swings. Trace A is Q1’s source; frequency content is seen to be inside 180µV (note ×50
traces B and C are its gate and drain, respectively. Under vertical scale-factor change).
these conditions, at 2A output, noise is inside 400µV peak. 1Witt, Jeff. The LT1533 Heralds a New Class of Low Noise Switching
Regulators. Linear Technology VII:3 (August 1997).
2Williams, Jim. LTC Application Note 70: A Monolithic Switching Regulator
Current Boosting
with 100µV Output Noise. October 1997.
Figure H3 boosts the regulator’s 1A output capability 3The term “cascode,” derived from “cascade to cathode,” is applied

to over 5A. It does this with simple emitter followers to a configuration that places active devices in series. The benefit may
(Q1–Q2). Theoretically, the followers preserve T1’s voltage be higher breakdown voltage, decreased input capacitance, bandwidth
improvement or the like. Cascoding has been employed in op amps,
and current waveform information, permitting the LT1533’s power supplies, oscilloscopes and other areas to obtain performance
slew-control circuitry to function. In practice, the transis- enhancement.
tors must be relatively low beta types. At 3A collector 4This circuit derives from a design by Jeff Witt of Linear Technology Corp.

current, their beta of 20 sources ≈150mA via the Q1–Q2 5Operating the slew loops from follower base current was suggested by

base paths, adequate for proper slew-loop operation.5 Bob Dobkin of Linear Technology Corp.

A = 20V/DIV

B = 5V/DIV A = 5mV/DIV
AC-COUPLED

C = 100V/DIV B = 100µV/DIV

AN29 FH2 AN29 FH4

10µs/DIV 2µs/DIV

Figure H2. MOSFET-Based Cascode Permits the Regulator to Figure H4. Waveforms for Figure H3 at 10W Output: Trace A
Control 100V Transformer Swings While Maintaining a Low Shows Fundamental Ripple with Higher Frequency Residue
Noise 5V Output. Trace A Is Q1’s Source, Trace B Is Q1’s Gate Just Discernible. The Optional LC Section Results in Trace B’s
and Trace C Is the Drain. Waveform Fidelity Through Cascode 180µVP-P Wideband Noise Performance
Permits Proper Slew-Control Operation
1N4148
330Ω
5V 1N5817
0.05Ω

+
4.7µF
14
VIN
Q1 T1
0.003µF
L1
300µH
12V L3
33µH ( OPTIONAL FOR
LOWEST RIPPLE )
11 2 + 680Ω
SHDN COL A
4.7µF 0.05Ω + +
3 Q2 100µF 100µF
DUTY 15
4 COL B
1500pF SYNC 330Ω 1N5817
5 16 L2
CT PGND
1N4148
LT1533 13 10k
18k 6 RVSL
RT
12 10k R1
RCSL 21.5k
10 7 1%
VC FB AN29 FH3

GND NFB R2
0.01µF L1: COILTRONICS CTX300-4
9 8 2.49k L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR
1% INDUCTOR. COILCRAFT B-07T TYPICAL
L3: COILTRONICS CTX33-4
Q1, Q2: MOTOROLA D45C1
T1: COILTRONICS CTX-02-13949-X1
: FERRONICS FERRITE BEAD 21-110J

Figure H3. A 10W Low Noise 5V to 12V Converter: Q1–Q2 Provide 5A Output Capacity While Preserving the LT1533’s Voltage/Current
Slew Control. Efficiency Is 68%. Higher Input Voltages Minimize Follower Loss, Boosting Efficiency Above 71%
an29f

Linear Technology Corporation IM/GP 689 5K • PRINTED IN USA

AN29-46 1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 1989